MC100LVEL05DR2 [ONSEMI]
3.3V ECL 2-Input Differential AND/NAND; 3.3V ECL 2输入差分AND / NAND
| 型号： | MC100LVEL05DR2 |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V ECL 2-Input Differential AND/NAND |
| 文件： | 总8页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100LVEL05
3.3VꢀECL 2-Input Differential
AND/NAND
Description
The MC100LVEL05 is a 2-input differential AND/NAND gate. The
device is functionally equivalent to the MC100EL05 device and
operates from a 3.3 V supply voltage. With propagation delays and
output transition times equivalent to the EL05, the LVEL05 is ideally
suited for those applications which require the ultimate in AC
performance at low voltage power supplies.
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MARKING
DIAGRAMS*
Because a negative 2-input NAND is equivalent to a 2-input OR
function, the differential inputs and outputs of the device allows the
LVEL05 to also be used as a 2-input differential OR/NOR gate.
8
8
1
KVL05
ALYW
G
SOIC−8
D SUFFIX
CASE 751
Features
1
8
• 340 ps Propagation Delay
• High Bandwidth Output Transitions
• ESD Protection: >4 kV Human Body Model,
>200 V Machine Model
8
1
KV05
ALYWG
• The 100 Series Contains Temperature Compensation
TSSOP−8
DT SUFFIX
CASE 948R
G
1
• PECL Mode Operating Range: V = 3.0 V to 3.8 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = −3.0 V to −3.8 V
EE
• Internal Input Pulldown Resistors
• Q Output will Default LOW with All Inputs Open or at V
1
4
EE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
DFN8
MN SUFFIX
CASE 506AA
A
L
= Assembly Location
= Wafer Lot
= Year
W = Work Week
M = Date Code
• Transistor Count = 69 devices
• Pb−Free Packages are Available
Y
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 3
MC100LVEL05/D
MC100LVEL05
Table 1. PIN DESCRIPTION
PIN
FUNCTION
D
D
1
2
8
7
V
CC
0
0
D0, D0; D1, D1
Q, Q
ECL Data Inputs
ECL Data Outputs
Positive Supply
Negative Supply
Q
Q
V
CC
V
EE
EP
Exposed pad must be con-
nected to a sufficient thermal
conduit. Electrically connect
to the most negative supply or
leave floating open.
D
D
3
4
6
5
1
1
V
EE
Figure 1. Logic Diagram and Pinout Assignment
Table 2. MAXIMUM RATINGS
Symbol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
Condition 1
= 0 V
Condition 2
Rating
8 to 0
Unit
V
V
CC
V
EE
V
I
V
V
EE
= 0 V
−8 to 0
V
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ꢀ V
6 to 0
−6 to 0
V
V
EE
I
CC
V ꢁ V
CC
I
EE
I
Output Current
Continuous
Surge
50
100
mA
mA
out
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
°C
°C
A
T
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
8 SOIC
41 to 44 ± 5%
°C/W
JC
JA
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
8 TSSOP
41 to 44 ± 5%
°C/W
JC
JA
DFN8
DFN8
129
84
°C/W
°C/W
500 lfpm
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
MC100LVEL05
Table 3. LVPECL DC CHARACTERISTICS V = 3.3 V; V = 0.0 V (Note 1)
CC
EE
−40°C
25°C
Typ
18
85°C
Typ
19
Symbol
Characteristic
Power Supply Current
Min
Typ
18
Max
25
Min
Max
25
Min
Max
26
Unit
mA
mV
mV
mV
mV
I
EE
V
V
V
V
V
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
2215
1470
2135
1490
2295
1605
2420
1745
2420
1825
2275
1490
2135
1490
2345
1595
2420
1680
2420
1825
2275
1490
2135
1490
2345
1595
2420
1680
2420
1825
OH
OL
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 6)
IHCMR
Vpp < 500 mV
Vpp y 500 mV
1.2
1.5
2.9
2.9
1.1
1.4
2.9
2.9
1.1
1.4
2.9
2.9
V
V
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V . V can vary ±0.3 V.
CC
EE
2. Outputs are terminated through a 50 ohm resistor to V − 2.0 V.
CC
3. V
min varies 1:1 with V , max varies 1:1 with V . The V
range is referenced to the most positive side of the differential input signal.
IHCMR
EE
CC
IHCMR
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V min and 1V.
PP
Table 4. LVNECL DC CHARACTERISTICS V = 0.0 V; V = −3.3 V (Note 4)
CC
EE
−40°C
25°C
Typ
18
85°C
Typ
19
Symbol
Characteristic
Power Supply Current
Min
Typ
Max
Min
Max
Min
Max
26
Unit
mA
mV
mV
mV
mV
I
EE
18
25
25
V
V
V
V
V
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
−1085 −1005 −880 −1025 −955
−880 −1025 −955
−880
OH
OL
−1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620
−1165
−1810
−880 −1165
−1475 −1810
−880 −1165
−1475 −1810
−880
IH
−1475
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 6)
IHCMR
Vpp < 500 mV −2.1
Vpp y 500 mV −1.8
−0.4
−0.4
−2.2
−1.9
−0.4
−0.4
−2.2
−1.9
−0.4
−0.4
V
V
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V . V can vary ±0.3 V.
CC
EE
5. Outputs are terminated through a 50 ohm resistor to V − 2.0 V.
CC
6. V
min varies 1:1 with V , max varies 1:1 with V . The V
range is referenced to the most positive side of the differential input signal.
IHCMR
EE
CC
IHCMR
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V min and 1V.
PP
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3
MC100LVEL05
Table 5. AC CHARACTERISTICS V = 3.3 V; V = 0.0 V or V = 0.0 V; V = −3.3 V (Note 7)
CC
EE
CC
EE
−405C
Typ
TBD
260
25°C
Typ
85°C
Typ
Symbol
Characteristic
Min
Max
Min
240
Max
Min
Max
Unit
GHz
ps
f
Maximum Toggle Frequency
Propagation Delay to Output
TBD
340
TBD
max
t
t
240
440
440
250
450
PLH
PHL
t
Cycle−to−Cycle Jitter
TBD
TBD
TBD
ps
mV
ps
JITTER
V
Input Swing (Note 8)
150
100
1000
320
150
100
1000
320
150
100
1000
320
PP
t
r
t
f
Output Rise/Fall Times Q
(20% − 80%)
210
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7.
V
can vary ±0.3 V.
EE
PP
8. V (min) is the minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ≈40.
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 3.0 V
CC
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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4
MC100LVEL05
ORDERING INFORMATION
Device
†
Package
Shipping
MC100LVEL05D
SOIC−8
98 Units / Rail
98 Units / Rail
MC100LVEL05DG
SOIC−8
(Pb−Free)
MC100LVEL05DR2
MC100LVEL05DR2G
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8
(Pb−Free)
MC100LVEL05DT
MC100LVEL05DTG
TSSOP−8
100 Units / Rail
100 Units / Rail
TSSOP−8
(Pb−Free)
MC100LVEL05DTR2
MC100LVEL05DTR2G
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
MC100LVEL05MNR4
MC100LVEL05MNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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5
MC100LVEL05
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MC100LVEL05
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
PLANE
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
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7
MC100LVEL05
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
0.30
2 X
D
D2
E
E2
e
K
2.00 BSC
0.10
C
1.10
1.30
2.00 BSC
2 X
0.70
0.90
0.50 BSC
0.10
C
TOP VIEW
0.20
0.25
−−−
0.35
L
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10 C A B
8 X b
0.05
C
NOTE 3
BOTTOM VIEW
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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MC100LVEL05/D
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