MC10EL34D [ONSEMI]
5V ECL ±2, ±4, ±8 Clock Generation Chip; 5V ECL ± 2 ， ± 4 ， ± 8时钟发生器芯片
| 型号： | MC10EL34D |
| 厂家： | 
ONSEMI |
| 描述： | 5V ECL ±2, ±4, ±8 Clock Generation Chip |
| 文件： | 总8页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EL34, MC100EL34
5VĄECL ÷2, ÷4, ÷8 Clock
Generation Chip
The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The V pin, an internally
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BB
generated voltage supply, is available to this device only. For
single-ended input conditions, the unused differential input is
MARKING
DIAGRAMS
connected to V as a switching reference voltage. V may also
BB
BB
16
rebias AC coupled inputs. When used, decouple V and V via a
BB
CC
SO–16
D SUFFIX
CASE 751B
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
10EL34
AWLYWW
When not used, V should be left open.
16
BB
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
referenced to the negative edge of the clock input.
1
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
100EL34
AWLYWW
WW = Work Week
1
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
ORDERING INFORMATION
Device
Package
SO–16
SO–16
SO–16
SO–16
Shipping
MC10EL34D
48 Units / Rail
2500 Units / Reel
48 Units / Rail
The 100 Series contains temperature compensation.
MC10EL34DR2
MC100EL34D
MC100EL34DR2
• 50 ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• ESD Protection: > 1 KV HBM, > 100 V MM
2500 Units / Reel
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = –4.2 V to –5.7 V
EE
• Internal Input Pulldown Resistors on CLK(s), EN, and MR
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 191 devices
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
October, 2000 – Rev. 3
MC10EL34/D
MC10EL34, MC100EL34
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
V
CC
EN NC CLK CLK V
MR
V
EE
BB
16
15
14
13
12
11
10
9
FUNCTION TABLE
D
Q
R
CLK*
EN*
MR*
FUNCTION
Z
ZZ
X
L
H
X
L
L
Divide
÷2
Q
÷4
Q
÷8
R
R
Q
R
Hold Q
0–3
H
Reset Q
0–3
2
3
8
5
6
1
4
7
Z = Low-to-High Transition
ZZ = High-to-Low Transition
V
Q0
* All V
V
Q1
Q2
Q0
Q1
Q2
CC
CC
* Pins will default low when left open.
pins are tied together on the die.
CC
Warning: All V and V pins must be externally connected
CC
EE
to Power Supply to guarantee proper operation.
PIN DESCRIPTION
PIN
FUNCTION
CLK, CLK
EN
ECL Diff Clock Inputs
ECL Sync Enable
ECL Master Reset
ECL Diff ÷2 Outputs
ECL Diff ÷4 Outputs
ECL Diff ÷8 Outputs
Reference Voltage Output
Positive Supply
MR
Q0, Q0
Q1, Q1
Q2, Q2
V
BB
V
CC
V
EE
Negative Supply
NC
No Connect
MAXIMUM RATINGS (Note 1.)
Symbol Parameter
Condition 1
= 0 V
Condition 2
Rating
Units
V
CC
V
EE
V
I
PECL Mode Power Supply
NECL Mode Power Supply
V
V
8
V
V
EE
= 0 V
–8
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ꢀ V
6
V
V
EE
I
CC
V ꢁ V
–6
CC
I
EE
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
BB
Sink/Source
± 0.5
mA
°C
BB
TA
Operating Temperature Range
Storage Temperature Range
–40 to +85
–65 to +150
T
°C
stg
θ
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
16 SOIC
16 SOIC
130
75
°C/W
°C/W
JA
θ
Thermal Resistance (Junction to Case)
Wave Solder
std bd
16 SOIC
33 to 36
265
°C/W
°C
JC
T
<2 to 3 sec @ 248°C
sol
1. Maximum Ratings are those values beyond which device damage may occur.
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2
MC10EL34, MC100EL34
10EL SERIES PECL DC CHARACTERISTICS V = 5.0 V; V = 0.0 V (Note 1.)
CC
EE
–40°C
25°C
85°C
Symbol
Characteristic
Power Supply Current
Min
Typ
Max
39
Min
Typ
Max
39
Min
Typ
Max
39
Unit
mA
mV
mV
mV
mV
V
I
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 2.)
Output LOW Voltage (Note 2.)
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
Output Voltage Reference
3920
3050
3770
3050
3.57
3.0
4010
3200
4110
3350
4110
3500
3.7
4020
3050
3870
3050
3.65
3.0
4105
3210
4190
3370
4190
3520
3.75
4.6
4090
3050
3940
3050
3.69
3.0
4185
3227
4280
3405
4280
3555
3.81
4.6
OH
OL
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 3.)
4.6
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
0.5
0.5
0.3
IL
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with V . V can vary +0.06 V / –0.5 V.
CC
EE
2. Outputs are terminated through a 50 ohm resistor to V –2 volts.
CC
3. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential input
IHCMR
EE IHCMR
CC
IHCMR
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V min and 1V.
PP
10EL SERIES NECL DC CHARACTERISTICS V = 0.0 V; V = –5.0 V (Note 1.)
CC
EE
–40°C
Typ
25°C
85°C
Symbol
Characteristic
Power Supply Current
Min
Max
39
Min
Typ
Max
39
Min
Typ
Max
39
Unit
mA
mV
mV
mV
mV
V
I
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 2.)
Output LOW Voltage (Note 2.)
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
Output Voltage Reference
–1080 –990
–890
–980
–895
–810
–910
–815
–720
OH
OL
–1950 –1800 –1650 –1950 –1790 –1630 –1950 –1773 –1595
–1230
–1950
–1.43
–2.0
–890 –1130
–1500 –1950
–1.30 –1.35
–810 –1060
–1480 –1950
–1.25 –1.31
–720
–1445
–1.19
–0.4
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 3.)
–0.4
–2.0
–0.4
–2.0
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
0.5
0.5
0.3
IL
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with V . V can vary +0.06 V / –0.5 V.
CC
EE
2. Outputs are terminated through a 50 ohm resistor to V –2 volts.
CC
3. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential input
IHCMR
EE IHCMR
CC
IHCMR
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V min and 1V.
PP
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3
MC10EL34, MC100EL34
100EL SERIES PECL DC CHARACTERISTICS V = 5.0 V; V = 0.0 V (Note 1.)
CC
EE
–40°C
25°C
85°C
Symbol
Characteristic
Power Supply Current
Min
Typ
Max
39
Min
Typ
Max
39
Min
Typ
Max
42
Unit
mA
mV
mV
mV
mV
V
I
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 2.)
Output LOW Voltage (Note 2.)
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
Output Voltage Reference
3915
3170
3835
3190
3.62
2.2
3995
3305
4120
3445
4120
3525
3.74
4.6
3975
3190
3835
3190
3.62
2.2
4045
3295
4120
3380
4120
3525
3.74
4.6
3975
3190
3835
3190
3.62
2.2
4050
3295
4120
3380
4120
3525
3.74
4.6
OH
OL
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 3.)
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
0.5
0.5
0.5
IL
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with V . V can vary +0.8 V / –0.5 V.
CC
EE
2. Outputs are terminated through a 50 ohm resistor to V –2 volts.
CC
3. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential input
IHCMR
EE IHCMR
CC
IHCMR
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V min and 1V.
PP
100EL SERIES NECL DC CHARACTERISTICS V = 0.0 V; V = –5.0 V (Note 1.)
CC
EE
–40°C
Typ
25°C
85°C
Symbol
Characteristic
Power Supply Current
Min
Max
Min
Typ
Max
Min
Typ
Max
42
Unit
mA
mV
mV
mV
mV
V
I
39
39
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 2.)
Output LOW Voltage (Note 2.)
Input HIGH Voltage (Single Ended)
Input LOW Voltage (Single Ended)
Output Voltage Reference
–1085 –1005 –880 –1025 –955
–880 –1025 –955
–880
OH
OL
–1830 –1695 –1555 –1810 –1705 –1620 –1810 –1705 –1620
–1165
–1810
–1.38
–2.8
–880 –1165
–1475 –1810
–1.26 –1.38
–880 –1165
–1475 –1810
–1.26 –1.38
–880
–1475
–1.26
–0.4
IH
IL
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 3.)
–0.4
–2.8
–0.4
–2.8
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
0.5
0.5
0.5
IL
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with V . V can vary +0.8 V / –0.5 V.
CC
EE
2. Outputs are terminated through a 50 ohm resistor to V –2 volts.
CC
3. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential input
IHCMR
EE IHCMR
CC
IHCMR
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V min and 1V.
PP
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4
MC10EL34, MC100EL34
AC CHARACTERISTICS V = 5.0 V; V = 0.0 V or
V
= 0.0 V; V = –5.0 V (Note 1.)
CC EE
CC
EE
–40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Min
Max
Min
Max
Min
Max
Unit
GHz
ps
f
Maximum Toggle Frequency
TBD
TBD
TBD
max
t
t
Propagation
Delay to
Output
CLK to Q0
CLK to Q1,2
MR to Q
960
900
750
1200
1140
1060
960
900
750
1200
1140
1060
970
910
790
1210
1150
1090
PLH
PHL
t
t
t
t
t
Within-Device Skew (Note 2.)
Cycle–to–Cycle Jitter
Setup Time EN
100
100
100
ps
ps
ps
ps
ps
mV
ps
SKEW
JITTER
S
TBD
TBD
TBD
400
250
400
150
275
400
250
400
150
275
400
250
400
150
275
Hold Time EN
H
Set/Reset Recovery
Input Swing (Note 3.)
200
200
200
RR
V
1000
525
1000
525
1000
525
PP
t
r
t
f
Output Rise/Fall Times Q
(20% – 80%)
1. 10 Series: V can vary +0.06 V / –0.5 V.
EE
100 Series: V can vary +0.8 V / –0.5 V.
EE
2. Within-device skew is defined as identical transitions on similar paths through a device.
3. V min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
PP(
t
RR
Internal Clock
Disabled
Internal Clock
Enabled
RESET
CLK
Q0
Q1
Q2
EN
The EN signal will freeze the internal clocks to the flip–flops on the first falling edge of CLK after its assertion. The internal
dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen.
The outputs will transition to their next states in the same manner, time and relationship as they would have had the EN signal
not been asserted.
Figure 1. Timing Diagram
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5
MC10EL34, MC100EL34
Q
D
Receiver
Device
Driver
Device
Qb
Db
50
TT
50
W
W
V
TT
V
V
=
– 2.0 V
CC
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
AN1405
AN1406
AN1503
AN1504
AN1560
AN1568
AN1596
AN1650
AN1672
AND8001
AND8002
AND8020
ECLinPS Circuit Performance at Non–Standard VIH Levels
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPS I/O SPICE Modeling Kit
–
–
–
–
–
–
–
–
–
–
–
–
–
Metastability and the ECLinPS Family
Low Voltage ECLinPS SPICE Modeling Kit
Interfacing Between LVDS and ECL
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
Using Wire–OR Ties in ECLinPS Designs
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
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6
MC10EL34, MC100EL34
PACKAGE DIMENSIONS
SO–16
D SUFFIX
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
1
9
8
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–B
–
P 8 PL
M
M
B
0.25 (0.010)
G
MILLIMETERS
MIN MAX
9.80 10.00
INCHES
MIN MAX
DIM
A
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
F
K
R X 45°
B
3.80
1.35
0.35
0.40
4.00
1.75
0.49
1.25
C
D
C
F
1.27 BSC
G
J
–T
0.19
0.10
0.25
0.25
7°
0.008 0.009
0.004 0.009
J
SEATING
PLANE
–
M
K
DĂ16ĂPL
M
P
0°
0°
0.229 0.244
7°
5.80
0.25
6.20
0.50
M
S
S
A
0.25 (0.010)
T
B
R
0.010 0.019
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7
MC10EL34, MC100EL34
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MC10EL34/D
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