MC10H640FNG [ONSEMI]
68030/040 PECL to TTL Clock Driver; 68030/040 PECL到TTL时钟驱动器
| 型号： | MC10H640FNG |
| 厂家： | 
ONSEMI |
| 描述： | 68030/040 PECL to TTL Clock Driver |
| 文件： | 总9页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10H640, MC100H640
68030/040 PECL to TTL
Clock Driver
Description
The MC10H/100H640 generates the necessary clocks for the
68030, 68040 and similar microprocessors. It is guaranteed to meet the
clock specifications required by the 68030 and 68040 in terms of
part−to−partskew, within−part skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced
to +5.0 V) for the input clock. TTL clocks are typically used in present
MPU systems. However, as clock speeds increase to 50 MHz and
beyond, the inherent superiority of ECL (particularly differential
ECL) as a means of clock signal distribution becomes increasingly
evident. The H640 also uses differential PECL internally to achieve its
superior skew characteristic.
The H640 includes divide−by−two and divide−by−four stages, both
to achieve the necessary duty cycle skew and to generate MPU clocks
as required. A typical 50 MHz processor application would use an
input clock running at 100 MHz, thus obtaining output clocks at
50 MHz and 25 MHz (see Logic Diagram).
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
Features
1
• Generates Clocks for 68030/040
• Meets 030/040 Skew Requirements
• TTL or PECL Input Clock
• Extra TTL and PECL Power/Ground Pins
• Asynchronous Reset
MCxxxH640G
AWLYYWW
• Single +5.0 V Supply
• Pb−Free Packages are Available*
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Function
Reset (R): LOW on RESET forces all Q outputs LOW and all Q
outputs HIGH.
Power−Up:The device is designed to have the POS edges of the ÷ 2
and ÷ 4 outputs synchronized at power up.
Select (SEL): LOW selects the ECL input source (DE/DE). HIGH
selects the TTL input source (DT).
*For additional marking information, refer to
Application Note AND8002/D.
The H640 also contains circuitry to force a stable state of the ECL
input differential pair, should both sides be left open. In this case, the
DE side of the input is pulled LOW, and DE goes HIGH.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 8
MC10H640/D
MC10H640, MC100H640
TTL Outputs
VT VT Q1
GT GT
22 21
Q0
20
VT
19
Q0
25
24
23
Q1
Q2
Q3
Q0
18
Q2 26
GT 27
GT 28
V
BB
TTL/ECL Clock Inputs
17
16
15
14
13
12
DE
DE
VE
R
V
BB
DE
DE
÷ 2
MUX
Q3
1
DT
VT
VT
2
3
4
SEL
Q1
GE
DT
Q0
÷ 4
Q4
Q5
5
6
7
8
9
10
11
TTL Control Inputs
Q1
GT GT
Q4 Q5
VT
SEL
R
Figure 1. Pinout: PLCC−28
Figure 2. Logic Diagram
(Top View)
Table 1. PIN DESCRIPTION
PIN
FUNCTION
GT
TTL Ground (0 V)
VT
TTL V (+5.0 V)
CC
VE
GE
DE, DE
ECL V (+5.0 V)
CC
ECL Ground (0 V)
ECL Signal Input (positive ECL)
V
V
Reference Output
BB
BB
DT
TTL Signal Input
Signal Outputs (TTL)
Input Select (TTL)
Reset (TTL)
Qn, Qn
SEL
R
Table 2. DC CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
0°C
Min Max
25°C
Min Max
85°C
Min
Max Unit
Symbol
Characteristic
Condition
VE Pin
I
Power Supply Current
ECL
TTL
57
30
30
57
30
30
57
30
30
mA
mA
mA
EE
I
I
Total all VT pins
CCH
CCL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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2
MC10H640, MC100H640
Table 3. 10H PECL DC CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
0°C
25°C
85°C
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Condition
Unit
I
I
Input HIGH Current
Input LOW Current
255
175
175
mA
INH
INL
0.5
0.5
0.5
V
1
Input HIGH Voltage
Input LOW Voltage
V
= 5.0 V
E
3.83
3.05
4.16
3.52
3.87
3.05
4.19
3.52
3.94
3.05
4.28
3.555
V
IH
IL
V 1
V
1
BB
Output Reference Voltage
3.62
3.73
3.65
3.75
3.69
3.81
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. PECL levels are referenced to V and will vary 1:1 with the power supply. The values shown are for V = 5.0V.
CC
CC
Table 4. 100H PECL DC CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
0°C
25°C
85°C
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Condition
Unit
I
I
Input HIGH Current
Input LOW Current
255
175
175
mA
INH
INL
0.5
0.5
0.5
V
2
Input HIGH Voltage
Input LOW Voltage
V
= 5.0 V
E
3.835
3.19
4.12
3.525
3.835
3.19
4.12
3.525
3.835
3.19
4.12
3.525
V
IH
IL
V 2
V
2
BB
Output Reference Voltage
3.62
3.74
3.62
3.74
3.62
3.74
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. PECL levels are referenced to V and will vary 1:1 with the power supply. The values shown are for V = 5.0V.
CC
CC
Table 5. TTL DC CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
0°C
Max
25°C
85°C
Min
Min
Max
Min
Max
Symbol
Characteristic
Input HIGH Voltage
Input LOW Voltage
Condition
Unit
V
V
2.0
2.0
2.0
V
IH
IL
0.8
0.8
0.8
I
Input HIGH Current
V
V
= 2.7 V
= 7.0 V
20
100
20
100
20
100
mA
IH
IN
IN
I
Input LOW Current
V
= 0.5 V
−0.6
−0.6
−0.6
mA
V
IL
IN
V
Output HIGH Voltage
I
= −3.0 mA
= −15 mA
2.5
2.0
2.5
2.0
2.5
2.0
OH
OH
OH
I
V
V
Output LOW Voltage
I
= 24 mA
OL
0.5
0.5
0.5
V
V
OL
IK
Input Clamp Voltage
I
= −18 mA
−1.2
−1.2
−1.2
IN
I
Output Short Circuit Current
V
= 0 V
OUT
−100 −225 −100 −225 −100 −225 mA
OS
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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MC10H640, MC100H640
Table 6. AC CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
0°C
Min Max
25°C
85°C
Min
Max
Min
Max
Symbol
Characteristic
Condition
Unit
t
Propagation Delay ECL
Q0 − Q3
CL = 25 pF
4.0
6.0
4.0
6.0
4.2
6.2
ns
PLH
D to Output
t
Propagation Delay TTL
D to Output
CL = 25 pF
4.0
6.0
4.0
6.0
4.3
6.3
ns
PLH
tskwd*
Within−Device Skew
CL = 25 pF
CL = 25 pF
0.5
6.0
0.5
6.0
0.5
6.2
ns
ns
t
t
t
t
t
Propagation Delay ECL
D to Output
Q0, Q1
Q4, Q5
4.0
4.0
4.0
4.0
4.3
4.0
4.0
4.0
4.0
4.3
4.2
4.3
4.2
4.3
5.0
PLH
PLH
PLH
PLH
PD
Propagation Delay TTL
D to Output
CL = 25 pF
CL = 25 pF
CL = 25 pF
CL = 25 pF
CL = 25 pF
CL = 25 pF
6.0
6.0
6.0
6.3
6.0
6.0
6.0
6.3
6.3
6.2
6.3
7.0
ns
ns
ns
ns
ns
Propagation Delay ECL
D to Output
Propagation Delay TTL
D to Output
Propagation Delay
R to Output
All Outputs
All Outputs
t
t
Output Rise/Fall Time
0.8 V to 2.0 V
2.5
2.5
2.5
2.5
2.5
2.5
R
F
f
t
t
Maximum Input Frequency
Minimum Pulse Width
Reset Recovery Time
135
1.50
1.25
135
1.50
1.25
135
1.50
1.25
MHz
ns
max
pw
rr
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Within−Device Skew defined as identical transitions on similar paths through a device.
Table 7. VCC and CL RANGES TO MEET DUTY CYCLE REQUIREMENTS
(0°C ≤ T ≤ 85°C Output Duty Cycle Measured Relative to 1.5 V)
A
Symbol
Characteristic
Condition
Min
Nom
Max
Unit
Range of V and CL to meet mini-
V
Q0 − Q3
Q0 − Q1
4.75
10
5.0
5.25
50
V
pF
CC
CC
mum pulse width
(HIGH or LOW)
CL
= 11.5 ns at f ≤ 40 MHz
out
Range of V and CL to meet mini-
V
Q0 − Q3
4.875
15
5.0
5.125
27
V
pF
CC
CC
mum pulse width
(HIGH or LOW)
CL
= 9.5 ns at 40 < f ≤ 50 MHz
out
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MC10H640, MC100H640
10/100H640
DUTY CYCLE CONTROL
To maintain a duty cycle of ± 5% at 50MHz, limit the load capacitance and/or power supply variation as shown in Figures 3
and 4. For a ± 2.5% duty cycle limit, see Figures 5 and 6. Figures 7 and 8 show duty cycle variation with temperature. Figure 9
shows typical TPD versus load. Figure 10 shows reset recovery time. Figure 11 shows output states after power up.
Best duty cycle control is obtained with a single mP load and minimum line length.
11
10
9
11
10
9
5.25 V
CC
5 V
CC
4.75 V
CC
4.75 V
CC
5 V
CC
5.25 V
CC
0
25
50
75
85
0
25
50
LOAD (pF)
75
85
LOAD (pF)
Figure 3. Positive Pulse Width at
Figure 4. Negative Pulse Width at
25°C Ambient and 50 MHz Out
25°C Ambient and 50 MHz Out
11
10
9
11
10
9
5.125 V
CC
5 V
CC
4.875 V
CC
4.875 V
CC
5 V
CC
5.125 V
CC
0
25
50
LOAD (pF)
75
85
0
25
50
LOAD (pF)
75
85
Figure 5. Positive Pulse Width at
Figure 6. Negative Pulse Width at
25°C Ambient at 50 MHz Out
25°C Ambient at 50 MHz Out
11
10
9
11
10 pF
50 pF
25 pF
10
25 pF
10 pF
9
0°
25°
50°
75°
85°
50°
75°
85°
25°
0°
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Temperature versus Positive Pulse Width
for 100H640 at 50 MHz and VCC = +5.0 V
Figure 8. Temperature versus Negative Pulse Width
for MC100H640 @ 50 MHz and VCC = +5.0 V
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5
MC10H640, MC100H640
6.2
6.0
4.75 V
5 V
5.25 V
5.8
5.6
5.4
5.2
25
0
50
(pF)
75
85
C
LOAD
Figure 9. tPD versus Load Typical at TA = 25°C
DT
RESET, R
R
trec
R
tpw
Q0, Q1, Q2, Q3
Q0, Q1
Q4, Q5
Figure 10. MC10H/100H640 Clock Phase and
Reset Recovery Time After Reset Pulse
D
in
Q → Q
0
3
Q → Q
1
2
Q & Q
4
5
AFTER POWER UP
OUTPUTS Q & Q WILL SYNC WITH POSITIVE EDGES OF D & Q → Q & NEGATIVE EDGES OF Q & Q
1
4
5
in
0
3
0
Figure 11. Output Timing Diagram
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MC10H640, MC100H640
ORDERING INFORMATION
Device
†
Package
Shipping
MC10H640FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC10H640FNG
PLCC−28
(Pb−Free)
MC10H640FNR2
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
MC10H640FNR2G
PLCC−28
(Pb−Free)
MC100H640FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC100H640FNG
PLCC−28
(Pb−Free)
MC100H640FNR2
MC100H640FNR2G
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
PLCC−28
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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MC10H640, MC100H640
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
M
S
S
0.007 (0.180)
T
L−M
N
B
Y BRK
D
−N−
M
S
S
N
0.007 (0.180)
T
L−M
U
Z
−M−
−L−
W
D
S
S
S
N
0.010 (0.250)
T
L−M
X
G1
V
28
1
VIEW D−D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
L−M
L−M
N
M
S
S
N
0.007 (0.180)
T
L−M
H
Z
M
S
T
N
R
K1
C
E
0.004 (0.100)
G
K
SEATING
PLANE
−T−
J
M
S
S
N
0.007 (0.180)
T
L−M
F
VIEW S
G1
S
S
S
N
0.010 (0.250)
T
L−M
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
DIM MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
A
B
C
E
F
0.485
0.485
0.165
0.090
0.013
2.29
0.33
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
0.032
−−−
−−−
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
−−−
0.81
−−−
K
R
U
V
W
X
Y
Z
−−−
0.456
0.456
0.048
0.048
0.056
11.58
11.58
1.21
1.21
1.42
0.50
10
−−− 0.020
10
2
2
_
_
_
_
G1 0.410
K1 0.040
0.430
−−−
10.42
1.02
10.92
−−−
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
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MC10H640, MC100H640
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
MECL 10H is a trademark of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC10H640/D
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