MC10H641FN
更新时间：2024-09-18 02:28:38
品牌：MOTOROLA
描述：SINGLE SUPPLY PECL-TTL 1:9 CLOCK DISTRIBUTION CHIP
概述
规格参数
数据手册MC10H641FN 概述
SINGLE SUPPLY PECL-TTL 1:9 CLOCK DISTRIBUTION CHIP 单电源PECL - TTL 1 ： 9时钟分配芯片 时钟驱动器
MC10H641FN 规格参数
| 生命周期： | Transferred | 零件包装代码： | QLCC |
| 包装说明： | QCCJ, LDCC28,.5SQ | 针数： | 28 |
| Reach Compliance Code： | unknown | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.35 | Is Samacsys： | N |
| 其他特性： | PECL-TTL CLOCK DISTRIBUTOR | 系列： | 10H |
| 输入调节： | DIFFERENTIAL LATCHED | JESD-30 代码： | S-PQCC-J28 |
| JESD-609代码： | e0 | 长度： | 11.5062 mm |
| 负载电容（CL）： | 50 pF | 逻辑集成电路类型： | LOW SKEW CLOCK DRIVER |
| 最大I（ol）： | 0.024 A | 功能数量： | 1 |
| 反相输出次数： | 端子数量： | 28 | |
| 实输出次数： | 9 | 最高工作温度： | 85 °C |
| 最低工作温度： | 封装主体材料： | PLASTIC/EPOXY | |
| 封装代码： | QCCJ | 封装等效代码： | LDCC28,.5SQ |
| 封装形状： | SQUARE | 封装形式： | CHIP CARRIER |
| 电源： | 5 V | 最大电源电流（ICC）： | 65 mA |
| Prop。Delay @ Nom-Sup： | 6.4 ns | 认证状态： | Not Qualified |
| Same Edge Skew-Max（tskwd）： | 0.35 ns | 座面最大高度： | 4.57 mm |
| 子类别： | Clock Drivers | 最大供电电压 (Vsup)： | 5.25 V |
| 最小供电电压 (Vsup)： | 4.75 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | ECL |
| 温度等级： | OTHER | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | J BEND | 端子节距： | 1.27 mm |
| 端子位置： | QUAD | 宽度： | 11.5062 mm |
| Base Number Matches： | 1 |
MC10H641FN 数据手册
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PDF下载SEMICONDUCTOR TECHNICAL DATA
The MC10H/100H641 is a single supply, low skew translating 1:9 clock
driver. Devices in the Motorola H600 translator series utilize the 28–lead
PLCC for optimal power pinning, signal flow through and electrical
performance.
SINGLE SUPPLY
PECL–TTL 1:9 CLOCK
DISTRIBUTION CHIP
The device features a 24mA TTL output stage, with AC performance
specified into a 50pF load capacitance. A latch is provided on–chip. When
LEN is LOW (or left open, in which case it is pulled LOW by the internal
pulldown) the latch is transparent. A HIGH on the enable pin (EN) forces
all outputs LOW. Both the LEN and EN pins are positive ECL inputs.
The V
output is provided in case the user wants to drive the device
with a single–ended input. For single–ended use the V should be
BB
BB
connected to the D input and bypassed with a 0.01µF capacitor.
The 10H version of the H641 is compatible with positive MECL 10H
logic levels. The 100H version is compatible with positive 100K levels.
• PECL–TTL Version of Popular ECLinPS E111
• Low Skew
• Guaranteed Skew Spec
• Latched Input
• Differential ECL Internal Design
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
• V
Output for Single–Ended Use
BB
• Single +5V Supply
• Logic Enable
• Extra Power and Ground Supplies
• Separate ECL and TTL Supply Pins
Pinout: 28–Lead PLCC (Top View)
GT
Q6
VT
Q7
VT
Q8
GT
PIN NAMES
25
24
23
22
21
20
19
Pins
Function
GT
Q5
VT
Q4
VT
Q3
GT
26
27
28
18
17
16
15
14
13
12
VBB
D
GT, VT
GE, VE
D, D
TTL GND, TTL V
CC
ECL GND, ECL V
CC
Signal Input (Positive ECL)
V Reference Output
D
V
BB
BB
(Positive ECL)
VE
LEN
GE
EN
1
2
Q0–Q8
EN
LEN
Signal Outputs (TTL)
Enable Input (Positive ECL)
Latch Enable Input
(Positive ECL)
3
4
5
6
7
8
9
10
11
GT
Q2
VT
Q1
VT
Q0
GT
MECL 10H is a trademark of Motorola, Inc.
11/93
REV 3
Motorola, Inc. 1996
MC10H641 MC100H641
LOGIC DIAGRAM
TTL Outputs
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
PECL Input
D
D
D
Q
VBB
LEN
EN
DC CHARACTERISTICS (VT = VE = 5.0V ±5%)
T
A
= 0°C
T
A
= + 25°C
T
A
= + 85°C
Typ
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Max
Unit
Condition
I
Power Supply Current
PECL
24
30
24
30
24
30
mA
EE
I
I
TTL
24
27
30
35
24
27
30
35
24
27
30
35
mA
mA
CCH
CCL
TTL DC CHARACTERISTICS (VT = VE = 5.0V ±5%)
0°C
25°C
85°C
Symbol
Characteristic
Output HIGH Voltage
Min
Max
Min
2.5
Max
Min
Max
Unit
V
Condition
V
V
2.5
2.5
I
I
= –15mA
= 24mA
OH
OH
Output LOW Voltage
0.5
0.5
0.5
V
OL
OL
I
Output Short Circuit Current
–100
–225
–100
–225
–100
–225
mA
V
OUT
= 0V
OS
10H PECL DC CHARACTERISTICS
0°C
25°C
85°C
Symbol
Characteristic
Input HIGH Current
Min
Max
Min
Max
Min
Max
Unit
µA
µA
V
Condition
I
225
175
175
IH
IL
I
Input LOW Current
0.5
0.5
0.5
1
1
1
V
V
V
Input HIGH Voltage
Input LOW Voltage
Output Reference Voltage
3.83
3.05
3.62
4.16
3.52
3.73
3.87
3.05
3.65
4.19
3.52
3.75
3.94
3.05
3.69
4.28
3.55
3.81
VE = 5.0V
VE = 5.0V
VE = 5.0V
IH
IL
V
V
BB
1. PECL V , V , and V
IH IL
are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0V.
BB
MOTOROLA
2–2
MC10H641 MC100H641
100H PECL DC CHARACTERISTICS
0°C
25°C
85°C
Symbol
Characteristic
Input HIGH Curren
Min
Max
Min
Max
Min
Max
Unit
µA
µA
V
Condition
I
I
225
175
175
IH
Input LOW Current
0.5
0.5
0.5
IL
1
1
1
V
V
V
Input HIGH Voltage
Input LOW Voltage
Output Reference Voltage
3.835
3.190
3.62
4.120
3.525
3.74
3.835
3.190
3.62
4.120
3.525
3.74
3.835
3.190
3.62
4.120
3.525
3.74
VE = 5.0V
VE = 5.0V
VE = 5.0V
IH
V
IL
V
BB
1. PECL V , V , and V
IH IL
are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0V.
BB
AC CHARACTERISTICS (VT = VE = 5.0V ±5%)
T
J
= 0°C
T
J
= + 25°C
T = + 85°C
J
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Condition
1
t
t
Propagation Delay
D to Q
5.00
5.36
5.50
5.86
6.00
6.36
4.86
5.27
5.36
5.77
5.86
6.27
5.08
5.43
5.58
5.93
6.08
6.43
ns
CL = 50 pF
PLH
PHL
t
Device Skew
Part–to–Part
ps
skew
2
3
4
1000
750
350
1000
750
350
1000
750
350
CL = 50pF
CL = 50 pF
CL = 50 pF
Single V
CC
Output–to–Output
t
t
Propagation Delay
LEN to Q
4.9
5.0
6.9
7.0
4.9
4.9
6.9
6.9
5.0
5.0
7.0
7.0
ns
ns
ns
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
PLH
PHL
t
t
Propagation Delay
EN to Q
PLH
PHL
t
r
t
f
Output Rise/Fall
0.8V to 2.0V
1.7
1.6
1.7
1.6
1.7
1.6
5
f
t
t
t
Max Input Frequency
Recovery Time EN
Setup Time
65
65
65
MHz
ns
MAX
REC
S
1.25
0.75
0.75
1.25
0.75
0.75
1.25
0.75
0.75
0.50
0.50
0.50
0.50
0.50
0.50
ns
Hold Time
ns
H
1. Propagation delay measurement guaranteed for junction temperatures. Measurements performed at 50MHz input frequency.
2. Skew window guaranteed for a single temperature across a V = V = V of 4.75V to 5.25V (See Application Note in this datasheet).
CC
3. Skew window guaranteed for a single temperature and single V
4. Output–to–output skew is specified for identical transitions through the device.
5. Frequency at which output levels will meet a 0.8V to 2.0V minimum swing.
T
E
= V = V
E
CC
T
DETERMINING SKEW FOR A SPECIFIC APPLICATION
The H641 has been designed to meet the needs of very low
skew clock distribution applications. In order to optimize the
device for this application special considerations are
necessary in the determining of the part–to–part skew
specification limits. Older standard logic devices are specified
with relatively slack limits so that the device can be
guaranteed over a wide range of potential environmental
conditions. This range of conditions represented all of the
potential applications in which the device could be used. The
result was a specification limit that in the vast majority of cases
was extremely conservative and thus did not allow for an
optimum system design. For non–critical skew designs this
practice is acceptable, however as the clock speeds of
systems increase overly conservative specification limits can
kill a design.
The following will discuss how users can use the
information provided in this data sheet to tailor a part–to–part
skew specification limit to their application. The skew
determination process may appear somewhat tedious and
time consuming, however if the utmost in performance is
required this procedure is necessary. For applications which
do not require this level of skew performance a generic
part–to–part skew limit of 2.5ns can be used. This limit is good
fortheentireambienttemperaturerange,theguaranteedV
CC
(V ,V )rangeandtheguaranteedoperatingfrequencyrange.
T
E
2–3
MOTOROLA
MC10H641 MC100H641
Temperature Dependence
Figure 2 illustrates the thermal resistance (in °C/W) for the
28–lead PLCC under various air flow conditions. By reading
the thermal resistance from the graph and multiplying by the
power dissipation calculated above the junction temperature
increase above ambient of the device can be calculated.
A unique characteristic of the H641 data sheet is that the
AC parameters are specified for a junction temperature rather
than the usual ambient temperature. Because very few
designs will actually utilize the entire commercial temperature
range of a device a tighter propagation delay window can be
established given the smaller temperature range. Because
the junction temperature and not the ambient temperature is
what affects the performance of the device the parameter
limits are specified for junction temperature. In addition the
relationship between the ambient and junction temperature
will vary depending on the frequency, load and board
environment of the application. Since these factors are all
under the control of the user it is impossible to provide
specification limits for every possible application. Therefore a
baseline specification was established for specific junction
temperatures and the information that follows will allow these
to be tailored to specific applications.
70
60
50
40
30
Since the junction temperature of a device is difficult to
measure directly, the first requirement is to be able to
“translate” from ambient to junction temperatures. The
standard method of doing this is to use the power dissipation
of the device and the thermal resistance of the package. For
a TTL output device the power dissipation will be a function of
theloadcapacitanceandthefrequencyoftheoutput. Thetotal
power dissipation of a device can be described by the
following equation:
0
200
400
600
800
1000
AIRFLOW (LFPM)
Figure 2.
versus Air Flow
JA
P
(watts) = I
(no load) * V +
CC
L
D
CC
* f * C * # Outputs
V
* V
S
CC
Finally taking this value for junction temperature and
applying it to Figure 3 allows the user to determine the
propagation delay for the device in question. A more common
use would be to establish an ambient temperature range for
the H641’s in the system and utilize the above methodology
to determine the potential increased skew of the distribution
where:
V = Output Voltage Swing = 3V
S
f = Output Frequency
C = Load Capacitance
L
I
= I
+ I
network. Note that for this information if the T
versus
CC EE CCH
PD
Temperature curve were linear the calculations would not be
required. If the curve were linear over all temperatures a
simple temperature coefficient could be provided.
Figure 1 plots the I versus Frequency of the H641 with
CC
no load capacitance on the output. Using this graph and the
information specific to the application a user can determine
the power dissipation of the H641.
6.4
5
4
3
2
1
0
6.2
6.0
5.8
5.6
5.4
5.2
T
PHL
T
PLH
110
–30
–10
10
30
50
70
90
C)
130
0
10
20
30
40
50
60
70
80
JUNCTION TEMPERATURE (
°
FREQUENCY (MHz)
Figure 3. T
versus Junction Temperature
PD
Figure 1. I
versus f (No Load)
CC
MOTOROLA
2–4
MC10H641 MC100H641
V
Dependence
CC
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
TTL and CMOS devices show a significant propagation
delay dependence with V . Therefore the V
variation in a
CC CC
system will have a direct impact on the total skew of the clock
distribution network. When calculating the skew between two
devices on a single board it is very likely an assumption of
T
PLH
identicalV ’scanbemade.Inthiscasethenumberprovided
CC
in the data sheet for part–to–part skew would be overly
conservative. By using Figure 4 the skew given in the data
sheet can be reduced to represent a smaller or zero variation
in V . The delay variation due to the specified V
is ≈270ps. Therefore, the 1ns window on the data sheet can
be reduced by 270ps if the devices in question will always
experience the same V . The distribution of the propagation
delay ranges given in the data sheet is actually a composite
of three distributions whose means are separated by the fixed
difference in propagation delay at the typical, minimum and
MEASURED
variation
CC
CC
T
PHL
40
CC
THEORETICAL
0
10
20
30
50
60
70
80
90 100
maximum V
.
CC
CAPACITIVE LOAD (pF)
Figure 5. T
versus Load
PD
140
100
60
Rise/Fall Skew Determination
The rise–to–fall skew is defined as simply the difference
between the T and the T propagation delays. This
PLH
PHL
skew for the H641 is dependent on the V
device. Notice from Figure 4 the opposite relationship of T
applied to the
CC
PD
versus V
between T
and T
PLH PHL
. Because of this the
CC
rise–to–fall skew will vary depending on V . Since in all
CC
20
likelihood it will be impossible to establish the exact value for
V
, the expected variation range for V
should be used. If
CC
CC
–20
–60
–100
–140
this variation will be the ±5% shown in the data sheet the
rise–to–fall skew could be established by simply subtracting
the fastest T
1.41ns. If a tighter V
T
T
PLH
from the slowest T
; this exercise yields
PHL
PLH
PHL
range can be realized Figure 4 can be
CC
used to establish the rise–to–fall skew.
Specification Limit Determination Example
The situation pictured in Figure 6 will be analyzed as an
example. Thecentralclockisdistributedtotwodifferentcards;
on one card a single H641 is used to distribute the clock while
on the second card two H641’s are required to supply the
needed clocks. The data sheet as well as the graphical
information of this section will be used to calculate the skew
between H641a and H641b as well as the skew between all
4.75
4.85
4.95
5.05
VCC (V)
5.15
5.25
Figure 4. ∆T
versus V
CC
PD
threeofthedevices. OnlytheT
numbers can be found using the same technique. The
following assumptions will be used:
willbeanalyzed,theT
PLH
PHL
Capacitive Load Dependence
– All outputs will be loaded with 50pF
– All outputs will toggle at 30MHz
As with V
CC
the propagation delay of a TTL output is
intimately tied to variation in the load capacitance. The skew
specifications given in the data sheet, of course, assume
equal loading on all of the outputs. However situations could
arise where this is an impossibility and it may be necessary to
estimate the skew added by asymmetric loading. In addition
the propagation delay numbers are provided only for 50pF
loads, thus necessitating a method of determining the
propagation delay for alternative loads.
– The V
variation between the two boards is ±3%
CC
– The temperature variation between the three
devices is ±15°C around an ambient of 45°C.
– 500LFPM air flow
The first task is to calculate the junction temperature for the
devices under these conditions. Using the power equation
yields:
Figure 5 shows the relationship between the two
propagation delays with respect to the capacitive load on the
output. Utilizingthisgraphandthe50pFlimitsthespecification
of the H641 can be mapped into a spec for either a different
value load or asymmetric loads.
P
= I
(no load) * V +
CC
CC
D
CC
V
* V * f * C * # outputs
S L
= 1.8 * 48mA * 5V + 5V * 3V * 30MHz *
50pF * 9
= 432mW + 203mW = 635mW
2–5
MOTOROLA
MC10H641 MC100H641
Using the thermal resistance graph of Figure 2 yields a
thermal resistance of 41°C/W which yields a junction
temperature of 71°C with a range of 56°C to 86°C. Using the
the conservative worst case limits provided at the beginning
of this note. For very high performance designs, this extra
information and effort can mean the difference between going
ahead with prototypes or spending valuable engineering time
searching for alternative approaches.
T
versus Temperature curve of Figure 3 yields a
PD
propagation delay of 5.42ns and a variation of 0.19ns.
Since the design will not experience the full ±5% V
variation of the data sheet the 1ns window provided will be
unnecessarily conservative. Using the curve of Figure 4
CC
Card 1
H641a
Q0
shows a delay variation due to a ±3% V
variation of
CC
±0.075ns. Therefore the 1ns window can be reduced to
1ns – (0.27ns – 0.15ns) = 0.88ns. Since H641a and H641b
are on the same board we will assume that they will always be
ECL
TTL
Q8
at the same V ; therefore the propagation delay window will
CC
only be 1ns – 0.27ns = 0.73ns.
Putting all of this information together leads to a skew
between all devices of
H641b
ECL
Q0
Q8
0.19ns + 0.88ns
(temperature + supply, and inherent device),
TTL
while the skew between devices A and B will be only
0.19ns + 0.73ns
(temperature + inherent device only).
Card 2
In both cases, the propagation delays will be centered
H641c
ECL
around 5.42ns, resulting in the following t
windows:
PLH
Q0
Q8
T
T
= 4.92ns – 5.99ns; 1.07ns window
PLH
PLH
TTL
(all devices)
= 5.00ns – 5.92ns; 0.92ns window
(devices a & b)
Of course the output–to–output skew will be as shown in
the data sheet since all outputs are equally loaded.
Figure 6. Example Application
This process may seem cumbersome, however the delay
windows, and thus skew, obtained are significantly better than
MOTOROLA
2–6
MC10H641 MC100H641
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
M
S
S
0.007 (0.180)
T
L–M
N
B
Y BRK
D
–N–
M
S
S
0.007 (0.180)
T
L–M
N
U
Z
–M–
–L–
W
D
S
S
S
0.010 (0.250)
T
L–M
N
X
G1
V
28
1
VIEW D–D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
L–M
L–M
N
M
S
S
0.007 (0.180)
T
L–M
N
H
Z
M
S
T
N
R
K1
C
E
0.004 (0.100)
SEATING
PLANE
G
K
–T–
VIEW S
J
M
S
S
0.007 (0.180)
T
L–M
N
F
G1
S
S
S
0.010 (0.250)
T
L–M
N
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
0.485
0.485
0.165
0.090
0.013
2.29
2.79
0.33
0.48
0.050 BSC
1.27 BSC
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
–––
0.032
–––
–––
0.456
0.456
0.048
0.048
0.056
0.020
10
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
–––
0.81
–––
–––
11.58
11.58
1.21
1.21
1.42
0.50
10
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
2
2
0.410
0.040
0.430
–––
10.42
1.02
10.92
–––
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
2–7
MOTOROLA
MC10H641 MC100H641
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC10H641/D
◊
MC10H641FN 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| MC10H641FNG | ONSEMI | Single Supply PECL to TTL 1:9 Clock Distribution Chip | 获取价格 |
|
| MC10H641FNG | ROCHESTER | 10H SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, LEAD FREE, PLASTIC, LCC-28 | 获取价格 |
|
| MC10H641FNR2 | ONSEMI | Single Supply PECL to TTL 1:9 Clock Distribution Chip | 获取价格 |
|
| MC10H641FNR2 | MOTOROLA | 10H SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28 | 获取价格 |
|
| MC10H641FNR2 | ROCHESTER | 10H SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28 | 获取价格 |
|
| MC10H641FNR2G | ONSEMI | Single Supply PECL to TTL 1:9 Clock Distribution Chip | 获取价格 |
|
| MC10H641FNR2G | ROCHESTER | 10H SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, LEAD FREE, PLASTIC, LCC-28 | 获取价格 |
|
| MC10H641_06 | ONSEMI | Single Supply PECL to TTL 1:9 Clock Distribution Chip | 获取价格 |
|
| MC10H642 | ONSEMI | 68030/040 PECL-TTL CLOCK DRIVER | 获取价格 |
|
| MC10H642FN | MOTOROLA | 68030/040 PECL-TTL CLOCK DRIVER | 获取价格 |
|
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