MC14001BFL2 [ONSEMI]
IC,LOGIC GATE,QUAD 2-INPUT NOR,CMOS,SOP,14PIN,PLASTIC;
| 型号： | MC14001BFL2 |
| 厂家： | 
ONSEMI |
| 描述： | IC,LOGIC GATE,QUAD 2-INPUT NOR,CMOS,SOP,14PIN,PLASTIC 输入元件 |
| 文件： | 总12页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
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The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
MARKING
DIAGRAMS
14
PDIP–14
P SUFFIX
CASE 646
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
MC140xxBCP
AWLYYWW
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
• Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
1
14
SOIC–14
D SUFFIX
CASE 751A
140xxB
AWLYWW
• Pin–for–Pin Replacements for Corresponding CD4000 Series B
Suffix Devices
1
14
TSSOP–14
DT SUFFIX
CASE 948G
14
0xxB
ALYW
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 1.)
SS
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage Range
–0.5 to +18.0
1
14
1
V , V
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
in out
DD
SOEIAJ–14
F SUFFIX
CASE 965
MC140xxB
ALYW
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P
D
Power Dissipation,
500
mW
xx
A
WL, L
YY, Y
= Specific Device Code
= Assembly Location
= Wafer Lot
per Package (Note 2.)
T
A
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
= Year
T
stg
WW, W = Work Week
T
L
Lead Temperature
(8–Second Soldering)
DEVICE INFORMATION
1. Maximum Ratings are those values beyond which damage to the device
may occur.
Device
Description
2. Temperature Derating:
MC14001B
MC14011B
MC14023B
MC14025B
MC14071B
MC14073B
Quad 2–Input NOR Gate
Quad 2–Input NAND Gate
Triple 3–Input NAND Gate
Triple 3–Input NOR Gate
Quad 2–Input OR Gate
Triple 3–Input AND Gate
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
MC14081B
MC14082B
Quad 2–Input AND Gate
Dual 4–Input AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
August, 2000 – Rev. 2
MC14001B/D
MC14001B Series
LOGIC DIAGRAMS
NOR
NAND
OR
AND
MC14001B
MC14011B
MC14071B
MC14081B
Quad 2–Input NOR Gate
Quad 2–Input NAND Gate
Quad 2–Input OR Gate
Quad 2–Input AND Gate
1
3
2
1
3
2
1
3
2
1
3
2
5
4
6
5
4
6
5
4
6
5
4
6
8
8
8
8
10
10
10
10
9
9
9
9
12
13
12
11
13
12
13
12
11
13
11
11
MC14025B
MC14023B
MC14073B
MC14082B
Triple 3–Input NOR Gate
Triple 3–Input NAND Gate
Triple 3–Input AND Gate
Dual 4–Input AND Gate
1
2
8
1
2
8
1
2
8
2
9
9
9
3
1
4
5
9
3
4
5
3
4
5
3
4
5
6
6
6
10
13
11
12
13
11
12
13
11
12
13
11
12
10
10
10
NC = 6, 8
V
DD
= PIN 14
V
= PIN 7
FOR ALL DEVICES
SS
PIN ASSIGNMENTS
MC14023B
Triple 3–Input NAND Gate
MC14025B
Triple 3–Input NOR Gate
MC14001B
Quad 2–Input NOR Gate
MC14011B
Quad 2–Input NAND Gate
IN 1
IN 2
1
2
3
4
5
6
7
14
V
IN 1
IN 2
1
2
3
4
5
6
7
14
V
IN 1
IN 2
IN 1
IN 2
IN 3
OUT
1
2
3
4
5
6
7
14
V
IN 1
IN 2
IN 1
IN 2
IN 3
OUT
1
2
3
4
5
6
7
14
V
DD
A
A
DD
A
A
DD
A
A
B
B
DD
A
A
B
B
13 IN 2
13 IN 2
13 IN 3
12 IN 2
11 IN 1
13 IN 3
12 IN 2
11 IN 1
D
D
D
D
C
C
C
C
C
C
OUT
12 IN 1
OUT
A
12 IN 1
A
OUT
IN 1
IN 2
11 OUT
10 OUT
OUT
IN 1
IN 2
11 OUT
10 OUT
B
D
C
B
D
C
10 OUT
10 OUT
C
B
B
B
B
B
B
C
B
B
9
8
IN 2
IN 1
9
8
IN 2
IN 1
9
8
OUT
9
8
OUT
A
C
C
A
V
SS
V
SS
V
SS
IN 3
V
SS
IN 3
A
C
C
A
MC14071B
Quad 2–Input OR Gate
MC14073B
Triple 3–Input AND Gate
MC14081B
Quad 2–Input AND Gate
MC14082B
Dual 4–Input AND Gate
IN 1
IN 2
1
2
3
4
5
6
7
14
V
IN 1
IN 2
IN 1
IN 2
IN 3
OUT
1
2
3
4
5
6
7
14
V
IN 1
1
2
3
4
5
6
7
14
V
OUT
1
2
3
4
5
6
7
14
13 OUT
B
V
A
DD
A
A
B
B
DD
A
A
DD
A
DD
13 IN 2
12 IN 1
13 IN 3
12 IN 2
11 IN 1
IN 2
13 IN 2
12 IN 1
11 OUT
10 OUT
IN 1
IN 2
IN 3
IN 4
A
D
C
C
C
D
D
D
C
A
A
A
A
OUT
OUT
12 IN 4
11 IN 3
10 IN 2
A
D
A
B
OUT
IN 1
IN 2
11 OUT
10 OUT
OUT
IN 1
IN 2
B
D
B
B
10 OUT
B
B
C
B
B
C
B
B
B
B
9
8
IN 2
IN 1
9
8
OUT
9
8
IN 2
C
NC
9
8
IN 1
NC
C
A
V
SS
V
SS
IN 3
V
SS
IN 1
V
SS
C
A
C
NC = NO CONNECTION
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2
MC14001B Series
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55_C
25_C
125_C
V
Vdc
DD
(3.)
Min
Max
Min
Typ
Max
Min
Max
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
µAdc
DD
(4.) (5.)
Total Supply Current
I
T
5.0
10
15
I = (0.3 µA/kHz) f + I /N
T DD
I = (0.6 µA/kHz) f + I /N
T DD
I = (0.9 µA/kHz) f + I /N
T
(Dynamic plus Quiescent,
Per Gate, C = 50 pF)
L
DD
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25_C.
5. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
T
L
DD
SS
per package.
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3
MC14001B Series
B–SERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS (6.) (C = 50 pF, T = 25_C)
L
A
V
DD
Vdc
(7.)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Rise Time, All B–Series Gates
t
ns
TLH
t
t
t
= (1.35 ns/pF) C + 33 ns
L
TLH
TLH
TLH
5.0
10
15
—
—
—
100
50
40
200
100
80
= (0.60 ns/pF) C + 20 ns
L
= (0.40 ns/PF) C + 20 ns
L
Output Fall Time, All B–Series Gates
t
ns
ns
THL
t
t
t
= (1.35 ns/pF) C + 33 ns
L
THL
THL
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
= (0.60 ns/pF) C + 20 ns
L
= (0.40 ns/pF) C + 20 ns
L
Propagation Delay Time
t
, t
PLH PHL
MC14001B, MC14011B only
t
t
t
, t
= (0.90 ns/pF) C + 80 ns
= (0.36 ns/pF) C + 32 ns
L
5.0
10
15
—
—
—
125
50
40
250
100
80
PLH PHL
L
, t
PLH PHL
, t
= (0.26 ns/pF) C + 27 ns
PLH PHL
L
All Other 2, 3, and 4 Input Gates
t
t
t
, t
= (0.90 ns/pF) C + 115 ns
= (0.36 ns/pF) C + 47 ns
L
5.0
10
15
—
—
—
160
65
50
300
130
100
PLH PHL
L
, t
PLH PHL
, t
= (0.26 ns/pF) C + 37 ns
PLH PHL
L
8–Input Gates (MC14068B, MC14078B)
t
t
t
, t
= (0.90 ns/pF) C + 155 ns
= (0.36 ns/pF) C + 62 ns
L
5.0
10
15
—
—
—
200
80
60
350
150
110
PLH PHL
L
, t
PLH PHL
, t
= (0.26 ns/pF) C + 47 ns
PLH PHL
L
6. The formulas given are for the typical characteristics only at 25_C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
20 ns
14
V
DD
V
DD
90%
50%
10%
INPUT
INPUT
*
0 V
PULSE
OUTPUT
t
t
PLH
GENERATOR
PHL
90%
50%
10%
V
V
OH
C
L
OUTPUT
OL
INVERTING
t
t
TLH
THL
t
t
PHL
PLH
V
V
OH
7
V
SS
OUTPUT
90%
50%
10%
NON-INVERTING
*All unused inputs of AND, NAND gates must be connected to V
.
OL
DD
t
t
THL
TLH
All unused inputs of OR, NOR gates must be connected to V
.
SS
Figure 1. Switching Time Test Circuit and Waveforms
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4
MC14001B Series
CIRCUIT SCHEMATIC
NOR, OR GATES
MC14001B, MC14071B
MC14025B
One of Four Gates Shown
One of Three Gates Shown
V
DD
V
DD
14
V
DD
1, 3, 11
2, 4, 12
1, 6, 8, 13
2, 5, 9, 12
*
14
V
DD
3, 4, 10, 11
*
V
SS
9, 6, 10
V
SS
7
V
SS
V
DD
*Inverter omitted in MC14001B
8, 5, 13
7
V
SS
V
SS
*Inverter omitted in MC14025B
CIRCUIT SCHEMATIC
NAND, AND GATES
MC14023B, MC14073B
MC14011B, MC14081B
One of Three Gates Shown
One of Four Gates Shown
V
DD
14
V
DD
*
3, 4, 10, 11
2, 5, 9, 12
2, 4, 12
1, 3, 11
14
V
DD
1, 6, 8, 13
V
7
*Inverter omitted in MC14011B
SS
V
SS
*
V
DD
9, 6, 10
8, 5, 13
7
*Inverter omitted in MC14023B
V
SS
V
SS
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5
MC14001B Series
TYPICAL B–SERIES GATE CHARACTERISTICS
N–CHANNEL DRAIN CURRENT (SINK)
P–CHANNEL DRAIN CURRENT (SOURCE)
- 10
5.0
4.0
3.0
- 9.0
- 8.0
- 7.0
- 6.0
- 5.0
- 4.0
T = - 55°C
A
T = - 55°C
A
- 40°C
- 40°C
+ 25°C
+ 25°C
+ 85°C
+ 85°C
2.0
1.0
+ 125°C
- 3.0
- 2.0
- 1.0
0
+ 125°C
0
0
1.0
2.0
3.0
4.0
5.0
0
- 1.0
- 2.0
V , DRAIN-TO-SOURCE VOLTAGE (Vdc)
DS
- 3.0
- 4.0
- 5.0
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
Figure 2. VGS = 5.0 Vdc
Figure 3. VGS = – 5.0 Vdc
20
18
16
14
12
10
8.0
- 50
- 45
- 40
- 35
- 30
- 25
- 20
T = - 55°C
A
- 40°C
+ 25°C
+ 85°C
T = - 55°C
A
- 40°C
+ 125°C
+ 25°C
+ 85°C
6.0
4.0
2.0
0
- 15
- 10
- 5.0
0
+ 125°C
0
1.0
2.0 3.0 4.0 5.0
6.0
7.0 8.0
9.0 10
0
- 1.0 - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
Figure 4. VGS = 10 Vdc
Figure 5. VGS = – 10 Vdc
50
45
40
35
30
25
20
- 100
- 90
- 80
- 70
- 60
- 50
- 40
T = - 55°C
A
- 40°C
+ 25°C
T = - 55°C
A
- 40°C
+ 85°C
+ 25°C
+ 125°C
+ 85°C
15
10
5.0
0
- 30
- 20
- 10
0
+ 125°C
0
2.0
4.0 6.0 8.0 10
12
14
16
18
20
0
- 2.0 - 4.0 - 6.0 - 8.0 - 10 - 12 - 14 - 16 - 18 - 20
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
V
DS
, DRAIN-TO-SOURCE VOLTAGE (Vdc)
Figure 6. VGS = 15 Vdc
Figure 7. VGS = – 15 Vdc
These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
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6
MC14001B Series
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
5.0
10
8.0
6.0
4.0
3.0
2.0
1.0
0
SINGLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
MULTIPLE INPUT NAND, AND
4.0
2.0
0
0
1.0
2.0
3.0
4.0
5.0
0
2.0
4.0
6.0
8.0
10
V , INPUT VOLTAGE (Vdc)
in
V , INPUT VOLTAGE (Vdc)
in
Figure 8. VDD = 5.0 Vdc
Figure 9. VDD = 10 Vdc
16
DC NOISE MARGIN
SINGLE INPUT NAND, AND
14
12
10
MULTIPLE INPUT NOR, OR
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values V and V for the output(s) to
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
IL
IH
be at a fixed voltage V are given in the Electrical
O
8.0
6.0
Characteristics table. V and V are presented graphically
IL
IH
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
4.0
2.0
0
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
0
2.0
4.0
6.0
8.0
10
V , INPUT VOLTAGE (Vdc)
in
Figure 10. VDD = 15 Vdc
V
out
V
DD
V
out
V
DD
V
O
V
O
V
O
V
O
V
V
V
V
DD
DD
0
0
in
in
V
IL
V
IH
V
IL
V
IH
V
SS
= 0 VOLTS DC
(a) Inverting Function
(b) Non–Inverting Function
Figure 11. DC Noise Immunity
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7
MC14001B Series
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
1
8
7
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
INCHES
DIM MIN MAX
MILLIMETERS
A
F
MIN
18.16
6.10
3.69
0.38
1.02
MAX
18.80
6.60
4.69
0.53
1.78
A
B
C
D
F
0.715
0.240
0.145
0.015
0.040
0.770
0.260
0.185
0.021
0.070
L
N
C
G
H
J
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
---
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
---
2.41
0.38
3.43
7.87
10
–T–
SEATING
PLANE
K
L
J
K
M
N
_
_
0.015
0.039
0.38
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–A–
14
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B–
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
B
0.25 (0.010)
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN
G
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
_
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
8.75 0.337
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
–T–
SEATING
PLANE
J
M
G
J
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
M
S
S
0.25 (0.010)
T B
A
K
M
P
R
7
0
_
_
_
_
5.80
0.25
6.20 0.228
0.50 0.010
0.244
0.019
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8
MC14001B Series
PACKAGE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ąă2. CONTROLLING DIMENSION: MILLIMETER.
ąă3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
ąă4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
14X K REF
M
S
S
0.10 (0.004)
T U
V
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
–U–
ąă5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
L
N
PIN 1
IDENT.
F
7
1
ąă6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
ąă7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
K
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN
K1
MAX
0.200
0.177
0.047
0.006
0.030
–V–
A
B
4.90
4.30
---
5.10 0.193
4.50 0.169
J J1
C
1.20
---
D
0.05
0.50
0.15 0.002
0.75 0.020
F
SECTION N–N
G
H
0.65 BSC
0.026 BSC
0.50
0.09
0.09
0.19
0.19
0.60 0.020
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.024
0.008
0.006
0.012
0.010
J
J1
K
–W–
C
K1
L
6.40 BSC
_
0.252 BSC
0
0.10 (0.004)
M
0
8
8
_
_
_
SEATING
PLANE
–T–
H
G
DETAIL E
D
http://onsemi.com
9
MC14001B Series
PACKAGE DIMENSIONS
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 965–01
ISSUE O
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ąă2. CONTROLLING DIMENSION: MILLIMETER.
ąă3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
14
8
E
Q
1
H
E
_
ąă4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
M
ąă5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN
---
A
e
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
---
0.05
0.35
0.18
9.90
5.10
2.05
A
1
b
c
0.20 0.002
0.50 0.014
0.27 0.007
D
E
e
10.50 0.390
5.45 0.201
b
A
1
M
1.27 BSC
0.050 BSC
0.13 (0.005)
0.10 (0.004)
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
0.50
L
E
M
0
10
0.90 0.028
0
10
_
0.035
0.056
_
_
_
Q
1
0.70
---
Z
1.42
---
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10
MC14001B Series
ORDERING & SHIPPING INFORMATION:
ORDERING & SHIPPING INFORMATION:
Device
Package
PDIP–14
Shipping
Device
Package
PDIP–14
Shipping
2000 Units per Box
55 Units per Rail
MC14001BCP
MC14001BD
2000 Units per Box
2750 Units per Box
2500 Units / Tape & Reel
96 Units per Rail
MC14071BCP
MC14071BD
SOIC–14
SOIC–14
TSSOP–14
TSSOP–14
SOIC–14
SOIC–14
TSSOP–14
TSSOP–14
MC14001BDR2
MC14001BDT
MC14001BDTR2
MC14071BDR2
MC14071BDT
MC14071BDTR2
2500 Units / Tape & Reel
96 Units per Rail
96 Units per Rail
96 Units per Rail
MC14011BCP
MC14011BD
PDIP–14
SOIC–14
2000 Units per Box
2750 Units per Box
2500 Units / Tape & Reel
96 Units per Rail
MC14073BCP
MC14073BD
PDIP–14
SOIC–14
SOIC–14
2000 Units per Box
55 Units per Rail
MC14011BDR2
MC14011BDT
MC14011BDTEL
MC14011BDTR2
SOIC–14
MC14073BDR2
2500 Units / Tape & Reel
TSSOP–14
TSSOP–14
TSSOP–14
2000 Units / Tape & Reel
50 Units per Rail
MC14081BCP
MC14081BD
PDIP–14
SOIC–14
2000 Units per Box
55 Units per Rail
MC14081BDR2
MC14081BDT
MC14081BDTR2
SOIC–14
2500 Units / Tape & Reel
96 Units per Rail
MC14023BCP
MC14023BD
PDIP–14
SOIC–14
SOIC–14
2000 Units per Box
2750 Units per Box
TSSOP–14
TSSOP–14
2500 Units / Tape & Reel
MC14023BDR2
2500 Units / Tape & Reel
MC14082BCP
MC14082BD
PDIP–14
SOIC–14
SOIC–14
2000 Units per Box
55 Units per Rail
MC14025BCP
MC14025BD
PDIP–14
SOIC–14
SOIC–14
2000 Units per Box
2750 Units per Box
MC14082BDR2
2500 Units / Tape & Reel
MC14025BDR2
2500 Units / Tape & Reel
For ordering information on the EIAJ version of the SOIC pack-
ages, please contact your local ON Semiconductor representa-
tive.
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11
MC14001B Series
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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