MC14001B_06 [ONSEMI]
B−Suffix Series CMOS Gates; B-后缀系列CMOS门
| 型号： | MC14001B_06 |
| 厂家： | 
ONSEMI |
| 描述： | B−Suffix Series CMOS Gates |
| 文件： | 总14页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14001B Series
B−Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
http://onsemi.com
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
MARKING
DIAGRAMS
14
1
PDIP−14
P SUFFIX
CASE 646
Features
MC140xxBCP
AWLYYWWG
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range.
• Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
• Pin−for−Pin Replacements for Corresponding CD4000 Series
B Suffix Devices
• Pb−Free Packages are Available
14
SOIC−14
D SUFFIX
CASE 751A
140xxBG
AWLYWW
1
14
14
0xxB
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
14
Symbol
Parameter
Value
−0.5 to +18.0
Unit
V
SOEIAJ−14
F SUFFIX
CASE 965
MC140xxB
ALYWG
V
DC Supply Voltage Range
DD
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
1
I , I
Input or Output Current
(DC or Transient) per Pin
±10
mA
xx
A
WL, L
YY, Y
= Specific Device Code
= Assembly Location
= Wafer Lot
in out
P
Power Dissipation, per Package
(Note 1)
500
mW
D
= Year
WW, W = Work Week
T
A
Ambient Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
T
stg
T
Lead Temperature
(8−Second Soldering)
L
DEVICE INFORMATION
Device
MC14001B
MC14011B
Description
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Quad 2−Input NOR Gate
Quad 2−Input NAND Gate
MC14023B
MC14025B
MC14071B
MC14073B
Triple 3−Input NAND Gate
Triple 3−Input NOR Gate
Quad 2−Input OR Gate
Triple 3−Input AND Gate
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
MC14081B
MC14082B
Quad 2−Input AND Gate
Dual 4−Input AND Gate
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
October, 2006 − Rev. 6
MC14001B/D
MC14001B Series
LOGIC DIAGRAMS
NOR
NAND
OR
AND
MC14001B
MC14011B
MC14071B
MC14081B
Quad 2−Input NOR Gate
Quad 2−Input NAND Gate
Quad 2−Input OR Gate
Quad 2−Input AND Gate
1
3
2
1
3
2
1
3
2
1
3
2
5
4
6
5
4
6
5
4
6
5
4
6
8
8
8
8
10
10
10
10
9
9
9
9
12
13
12
11
13
12
13
12
11
13
11
11
MC14025B
MC14023B
MC14073B
MC14082B
Triple 3−Input NOR Gate
Triple 3−Input NAND Gate
Triple 3−Input AND Gate
Dual 4−Input AND Gate
1
2
8
1
2
8
1
2
8
2
9
9
9
3
4
5
1
3
4
5
3
4
5
3
4
5
6
6
6
9
10
13
11
12
13
11
12
13
11
12
13
11
12
10
10
10
NC = 6, 8
V
= PIN 14
DD
V
= PIN 7
FOR ALL DEVICES
SS
PIN ASSIGNMENTS
MC14023B
Triple 3−Input NAND Gate
MC14025B
Triple 3−Input NOR Gate
MC14001B
Quad 2−Input NOR Gate
MC14011B
Quad 2−Input NAND Gate
IN 1
IN 2
OUT
OUT
IN 1
IN 2
1
2
3
4
5
6
14
V
IN 1
IN 2
OUT
OUT
IN 1
IN 2
1
2
3
4
5
6
14
V
IN 1
IN 2
IN 1
IN 2
IN 3
OUT
1
2
3
4
5
6
14
V
IN 1
IN 2
IN 1
IN 2
IN 3
OUT
1
2
3
4
5
6
14
V
DD
A
A
A
B
DD
A
A
A
B
DD
A
A
B
B
DD
A
A
B
B
13 IN 2
12 IN 1
13 IN 2
12 IN 1
13 IN 3
12 IN 2
11 IN 1
13 IN 3
12 IN 2
11 IN 1
D
D
D
C
C
C
C
C
C
D
11 OUT
10 OUT
11 OUT
10 OUT
D
C
D
C
10 OUT
10 OUT
B
B
B
B
B
B
C
B
B
C
9
8
IN 2
IN 1
9
8
IN 2
IN 1
9
8
OUT
IN 3
9
8
OUT
IN 3
C
C
A
A
V
7
V
7
V
7
V
7
SS
C
SS
C
SS
A
SS
A
MC14071B
Quad 2−Input OR Gate
MC14073B
Triple 3−Input AND Gate
MC14081B
Quad 2−Input AND Gate
MC14082B
Dual 4−Input AND Gate
IN 1
IN 2
OUT
OUT
IN 1
IN 2
1
2
3
4
5
6
14
V
IN 1
IN 2
IN 1
IN 2
IN 3
OUT
1
2
3
4
5
6
14
V
IN 1
IN 2
OUT
OUT
IN 1
IN 2
1
2
3
4
5
6
14
V
OUT
IN 1
IN 2
IN 3
IN 4
1
2
3
4
5
6
14
13 OUT
B
V
A
A
A
B
B
B
DD
A
A
B
B
B
B
DD
A
A
A
B
DD
A
A
A
A
A
DD
13 IN 2
12 IN 1
13 IN 3
12 IN 2
11 IN 1
13 IN 2
12 IN 1
11 OUT
10 OUT
D
D
C
C
C
D
D
D
C
12 IN 4
11 IN 3
10 IN 2
B
11 OUT
10 OUT
D
C
B
B
B
10 OUT
C
B
B
9
8
IN 2
IN 1
9
8
OUT
IN 3
9
8
IN 2
NC
9
8
IN 1
NC
C
A
C
V
7
V
7
V
7
IN 1
V
SS
7
SS
C
SS
A
SS
C
NC = NO CONNECTION
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2
MC14001B Series
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
125_C
V
Vdc
DD
(2)
Min
Max
Min
Typ
Max
Min
Max
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
“0” Level
V
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
OL
V
in
= V or 0
DD
V
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
OH
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
Vdc
IH
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
OH
OH
OH
OH
15
(V = 0.4 Vdc)
(V = 0.5 Vdc)
(V = 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
OL
OL
OL
Input Current
Input Capacitance
I
15
−
−
± 0.1
−
−
±0.00001
± 0.1
−
−
± 1.0
mAdc
in
C
−
−
5.0
7.5
−
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
−
−
−
0.25
0.5
1.0
−
−
−
0.0005
0.0010
0.0015
0.25
0.5
1.0
−
−
−
7.5
15
30
mAdc
mAdc
DD
(3) (4)
Total Supply Current
I
5.0
10
15
I
I
I
= (0.3 mA/kHz) f + I /N
DD
T
T
T
T
(Dynamic plus Quiescent,
= (0.6 mA/kHz) f + I /N
DD
Per Gate, C = 50 pF)
= (0.9 mA/kHz) f + I /N
L
DD
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C − 50) Vfk
T
L
T
L
where: I is in mA (per package), C in pF, V = (V − V ) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
T
L
DD
SS
per package.
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3
MC14001B Series
B−SERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS (5) (C = 50 pF, T = 25_C)
L
A
V
DD
Vdc
(6)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Rise Time, All B−Series Gates
t
ns
TLH
t
t
t
= (1.35 ns/pF) C + 33 ns
TLH
TLH
TLH
L
5.0
10
15
−
−
−
100
50
40
200
100
80
= (0.60 ns/pF) C + 20 ns
L
= (0.40 ns/PF) C + 20 ns
L
Output Fall Time, All B−Series Gates
t
ns
ns
THL
t
t
t
= (1.35 ns/pF) C + 33 ns
THL
THL
THL
L
5.0
10
15
−
−
−
100
50
40
200
100
80
= (0.60 ns/pF) C + 20 ns
L
= (0.40 ns/pF) C + 20 ns
L
Propagation Delay Time
t
, t
PLH PHL
MC14001B, MC14011B only
t
t
t
, t
= (0.90 ns/pF) C + 80 ns
5.0
10
15
−
−
−
125
50
40
250
100
80
PLH PHL
L
, t
= (0.36 ns/pF) C + 32 ns
PLH PHL
L
, t
= (0.26 ns/pF) C + 27 ns
PLH PHL
L
All Other 2, 3, and 4 Input Gates
t
t
t
, t
= (0.90 ns/pF) C + 115 ns
5.0
10
15
−
−
−
160
65
50
300
130
100
PLH PHL
L
, t
= (0.36 ns/pF) C + 47 ns
PLH PHL
L
, t
= (0.26 ns/pF) C + 37 ns
PLH PHL
L
8−Input Gates (MC14068B, MC14078B)
t
t
t
, t
= (0.90 ns/pF) C + 155 ns
5.0
10
15
−
−
−
200
80
60
350
150
110
PLH PHL
L
, t
= (0.36 ns/pF) C + 62 ns
PLH PHL
L
, t
= (0.26 ns/pF) C + 47 ns
PLH PHL
L
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
20 ns
14
V
DD
V
DD
90%
50%
10%
INPUT
INPUT
*
0 V
PULSE
OUTPUT
t
t
PLH
GENERATOR
PHL
90%
50%
10%
V
V
OH
OL
C
L
OUTPUT
INVERTING
t
t
TLH
THL
t
t
PHL
PLH
V
V
OH
OL
7
V
SS
OUTPUT
NON−INVERTING
90%
50%
10%
*All unused inputs of AND, NAND gates must be connected to V
All unused inputs of OR, NOR gates must be connected to V
.
DD
SS
t
t
THL
TLH
.
Figure 1. Switching Time Test Circuit and Waveforms
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4
MC14001B Series
CIRCUIT SCHEMATIC
NOR, OR GATES
MC14001B, MC14071B
MC14025B
One of Four Gates Shown
One of Three Gates Shown
V
DD
V
DD
14
V
DD
1, 3, 11
2, 4, 12
1, 6, 8, 13
2, 5, 9, 12
*
14
V
DD
3, 4, 10, 11
*
V
SS
9, 6, 10
V
7
SS
V
SS
V
DD
*Inverter omitted in MC14001B
8, 5, 13
7
V
SS
V
SS
*Inverter omitted in MC14025B
CIRCUIT SCHEMATIC
NAND, AND GATES
MC14023B, MC14073B
MC14011B, MC14081B
One of Three Gates Shown
One of Four Gates Shown
V
DD
14
V
DD
*
3, 4, 10, 11
2, 5, 9, 12
2, 4, 12
1, 3, 11
14
V
DD
1, 6, 8, 13
V
7
*Inverter omitted in MC14011B
SS
V
SS
*
V
DD
9, 6, 10
8, 5, 13
7
*Inverter omitted in MC14023B
V
SS
V
SS
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5
MC14001B Series
TYPICAL B−SERIES GATE CHARACTERISTICS
N−CHANNEL DRAIN CURRENT (SINK)
P−CHANNEL DRAIN CURRENT (SOURCE)
− 10
5.0
4.0
3.0
− 9.0
− 8.0
− 7.0
− 6.0
− 5.0
− 4.0
T
A
= − 55°C
− 40°C
T
= − 55°C
A
− 40°C
+ 25°C
+ 25°C
+ 85°C
+ 85°C
2.0
1.0
+ 125°C
− 3.0
− 2.0
− 1.0
0
+ 125°C
0
0
1.0
2.0
3.0
4.0
5.0
0
− 1.0
− 2.0
V , DRAIN−TO−SOURCE VOLTAGE (Vdc)
DS
− 3.0
− 4.0
− 5.0
V
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
DS
Figure 2. VGS = 5.0 Vdc
Figure 3. VGS = − 5.0 Vdc
20
18
16
14
12
10
8.0
− 50
− 45
− 40
− 35
− 30
− 25
− 20
T
A
= − 55°C
− 40°C
+ 25°C
+ 85°C
T
= − 55°C
A
− 40°C
+ 85°C
+ 125°C
+ 25°C
6.0
4.0
2.0
0
− 15
− 10
− 5.0
0
+ 125°C
0
1.0
2.0
3.0 4.0 5.0
6.0
7.0 8.0
9.0 10
0
− 1.0 − 2.0 − 3.0 − 4.0 − 5.0 − 6.0 − 7.0 − 8.0 − 9.0 − 10
V
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
V
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
DS
DS
Figure 4. VGS = 10 Vdc
Figure 5. VGS = − 10 Vdc
50
45
40
35
30
25
20
− 100
− 90
− 80
− 70
− 60
− 50
− 40
T
A
= − 55°C
− 40°C
+ 25°C
T
A
= − 55°C
+ 25°C
− 40°C
+ 85°C
+ 85°C
+ 125°C
15
10
5.0
0
− 30
− 20
− 10
0
+ 125°C
0
2.0
4.0
6.0 8.0 10
12
14
16
18
20
0
− 2.0 − 4.0 − 6.0 − 8.0 − 10 − 12 − 14 − 16 − 18 − 20
V
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
V
, DRAIN−TO−SOURCE VOLTAGE (Vdc)
DS
DS
Figure 6. VGS = 15 Vdc
Figure 7. VGS = − 15 Vdc
These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
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6
MC14001B Series
TYPICAL B−SERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
5.0
10
8.0
6.0
4.0
3.0
2.0
1.0
0
SINGLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
MULTIPLE INPUT NAND, AND
4.0
2.0
0
0
1.0
2.0
3.0
4.0
5.0
0
2.0
4.0
6.0
8.0
10
V , INPUT VOLTAGE (Vdc)
in
V , INPUT VOLTAGE (Vdc)
in
Figure 8. VDD = 5.0 Vdc
Figure 9. VDD = 10 Vdc
16
DC NOISE MARGIN
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
14
12
10
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values V and V for the output(s) to
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
IL
IH
be at a fixed voltage V are given in the Electrical
O
8.0
6.0
Characteristics table. V and V are presented graphically
IL
IH
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
4.0
2.0
0
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
0
2.0
4.0
6.0
8.0
10
V , INPUT VOLTAGE (Vdc)
in
Figure 10. VDD = 15 Vdc
V
out
V
V
out
V
DD
DD
V
V
O
O
V
V
O
O
V
V
V
V
DD
DD
0
0
in
in
V
V
V
V
IH
IL
IH
IL
V
= 0 VOLTS DC
SS
(a) Inverting Function
(b) Non−Inverting Function
Figure 11. DC Noise Immunity
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7
MC14001B Series
ORDERING INFORMATION
Device
†
Package
Shipping
MC14001BCP
PDIP−14
25 Units / Rail
55 Units / Rail
MC14001BCPG
PDIP−14
(Pb−Free)
MC14001BD
SOIC−14
MC14001BDG
SOIC−14
(Pb−Free)
MC14001BDR2
SOIC−14
MC14001BDR2G
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
2000 Units / Tape & Reel
MC14001BDTR2
TSSOP−14*
MC14001BDTR2G
TSSOP−14*
(Pb−Free)
MC14001BFEL
SOEIAJ−14
MC14001BFELG
SOEIAJ−14
(Pb−Free)
MC14011BCP
PDIP−14
25 Units / Rail
55 Units / Rail
MC14011BCPG
PDIP−14
(Pb−Free)
MC14011BD
SOIC−14
MC14011BDG
SOIC−14
(Pb−Free)
MC14011BDR2
SOIC−14
MC14011BDR2G
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
MC14011BDTR2
TSSOP−14*
MC14011BDTR2G
TSSOP−14*
(Pb−Free)
MC14011BF
SOEIAJ−14
50 Units / Rail
MC14011BFG
SOEIAJ−14
(Pb−Free)
MC14011BFEL
SOEIAJ−14
2000 Units / Tape & Reel
MC14011BFELG
SOEIAJ−14
(Pb−Free)
MC14023BCP
PDIP−14
25 Units / Rail
55 Units / Rail
MC14023BCPG
PDIP−14
(Pb−Free)
MC14023BD
SOIC−14
MC14023BDG
SOIC−14
(Pb−Free)
MC14023BDR2
SOIC−14
2500 Units / Tape & Reel
2000 Units / Tape & Reel
MC14023BDR2G
SOIC−14
(Pb−Free)
MC14023BFEL
SOEIAJ−14
MC14023BFELG
SOEIAJ−14
(Pb−Free)
http://onsemi.com
8
MC14001B Series
ORDERING INFORMATION
Device
†
Package
Shipping
MC14025BCP
PDIP−14
25 Units / Rail
55 Units / Rail
MC14025BCPG
PDIP−14
(Pb−Free)
MC14025BD
SOIC−14
MC14025BDG
SOIC−14
(Pb−Free)
MC14025BDR2
SOIC−14
2500 Units / Tape & Reel
2000 Units / Tape & Reel
MC14025BDR2G
SOIC−14
(Pb−Free)
MC14025BFEL
SOEIAJ−14
MC14025BFELG
SOEIAJ−14
(Pb−Free)
MC14071BCP
PDIP−14
25 Units / Rail
55 Units / Rail
MC14071BCPG
PDIP−14
(Pb−Free)
MC14071BD
SOIC−14
MC14071BDG
SOIC−14
(Pb−Free)
MC14071BDR2
SOIC−14
2500 Units / Tape & Reel
96 Units per Rail
MC14071BDR2G
SOIC−14
(Pb−Free)
MC14071BDT
TSSOP−14*
MC14071BDTG
TSSOP−14*
(Pb−Free)
MC14071BDTR2
TSSOP−14*
2500 Units / Tape & Reel
2000 Units / Tape & Reel
MC14071BDTR2G
TSSOP−14*
(Pb−Free)
MC14071BFEL
SOEIAJ−14
MC14071BFELG
SOEIAJ−14
(Pb−Free)
MC14073BCP
PDIP−14
25 Units / Rail
55 Units / Rail
MC14073BCPG
PDIP−14
(Pb−Free)
MC14073BD
SOIC−14
MC14073BDG
SOIC−14
(Pb−Free)
MC14073BDR2
SOIC−14
2500 Units / Tape & Reel
2000 Units / Tape & Reel
MC14073BDR2G
SOIC−14
(Pb−Free)
MC14073BFEL
SOEIAJ−14
MC14073BFELG
SOEIAJ−14
(Pb−Free)
http://onsemi.com
9
MC14001B Series
ORDERING INFORMATION
Device
†
Package
Shipping
MC14081BCP
PDIP−14
25 Units / Rail
55 Units / Rail
MC14081BCPG
PDIP−14
(Pb−Free)
MC14081BD
SOIC−14
MC14081BDG
SOIC−14
(Pb−Free)
MC14081BDR2
SOIC−14
MC14081BDR2G
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
2000 Units / Tape & Reel
MC14081BDTR2
TSSOP−14*
MC14081BDTR2G
TSSOP−14*
(Pb−Free)
MC14081BFEL
SOEIAJ−14
MC14081BFELG
SOEIAJ−14
(Pb−Free)
MC14082BCP
PDIP−14
2000 Units / Box
55 Units / Rail
MC14082BCPG
PDIP−14
(Pb−Free)
MC14082BD
SOIC−14
MC14082BDG
SOIC−14
(Pb−Free)
MC14082BDR2
SOIC−14
2500 Units / Tape & Reel
MC14082BDR2G
SOIC−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
10
MC14001B Series
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
N
C
G
H
J
K
L
M
N
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
−T−
SEATING
PLANE
J
_
_
K
0.015
0.039
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
http://onsemi.com
11
MC14001B Series
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
1.27 BSC
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
12
MC14001B Series
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
MILLIMETERS
INCHES
K1
DIM MIN
MAX
MIN MAX
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
1.20
0.15 0.002 0.006
0.75 0.020 0.030
J J1
−−− 0.047
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
13
MC14001B Series
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
14
8
E
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
E
_
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
MILLIMETERS
INCHES
MIN
VIEW P
DIM MIN
MAX
2.05
0.20
0.50
0.20
10.50
5.45
MAX
0.081
0.008
0.020
0.008
0.413
0.215
A
e
A
−−−
0.05
0.35
0.10
9.90
5.10
−−−
0.002
0.014
0.004
0.390
0.201
c
A
1
b
c
D
E
e
b
A
1
1.27 BSC
0.050 BSC
H
M
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
0.13 (0.005)
E
0.10 (0.004)
0.50
L
E
M
0
10
10
_
0.035
0.056
0
_
_
_
Q
1
0.70
−−−
0.90
1.42
0.028
−−−
Z
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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MC14001B/D
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