MC14007UBDR2 [ONSEMI]
Dual Complementary Pair Plus Inverter; 双互补对加变频器
| 型号： | MC14007UBDR2 |
| 厂家： | 
ONSEMI |
| 描述： | Dual Complementary Pair Plus Inverter |
| 文件： | 总8页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC14007UB multi–purpose device consists of three
N–channel and three P–channel enhancement mode devices packaged
to provide access to each device. These versatile parts are useful in
inverter circuits, pulse–shapers, linear amplifiers, high input
impedance amplifiers, threshold detectors, transmission gating, and
functional gating.
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MARKING
DIAGRAMS
14
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
PDIP–14
P SUFFIX
CASE 646
MC14007UBCP
AWLYYWW
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4007A or CD4007UB
• This device has 2 outputs without ESD Protection. Anti–static
precautions must be taken.
1
14
SOIC–14
D SUFFIX
CASE 751A
14007U
AWLYWW
1
14
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
TSSOP–14
DT SUFFIX
CASE 948G
14
007U
ALYW
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
1
14
1
I , I
Input or Output Current
(DC or Transient) per Pin
±10
mA
in out
SOEIAJ–14
F SUFFIX
CASE 965
MC14007U
AWLYWW
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
T
stg
T
Lead Temperature
(8–Second Soldering)
L
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
ORDERING INFORMATION
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Device
Package
PDIP–14
SOIC–14
Shipping
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14007UBCP
MC14007UBD
MC14007UBDR2
MC14007UBDT
MC14007UBF
2000/Box
55/Rail
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
SOIC–14 2500/Tape & Reel
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
96/Rail
TSSOP–14
SOEIAJ–14
SS
DD
See Note 1.
See Note 1.
MC14007UBFEL SOEIAJ–14
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14007UB/D
MC14007UB
PIN ASSIGNMENT
D–P
S–P
1
2
3
4
5
6
7
14
V
DD
B
13 D–P
B
A
GATE
12 OUT
C
B
S–N
11 S–P
C
B
D–N
10 GATE
C
B
GATE
9
8
S–N
C
A
V
SS
D–N
A
D = DRAIN
S = SOURCE
SCHEMATIC
14 13
2
1
11
6
12
7
8
3
4
5
10
9
V
V
= PIN 14
= PIN 7
DD
SS
A
B
A
B
12
1
9
2
4
C
3
5
INPUT
V
DD
14
C
11
13
INPUT OUTPUT CONDITION
INPUT
6
8
10
1
0
A = C, B = OPEN
A = B, C = OPEN
7
V
SS
Substrates of P–channel devices internally
connected to V ; substrates of N–channel
DD
devices internally connected to V
.
SS
Figure 1. Typical Application: 2–Input Analog Multiplexer
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2
MC14007UB
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(4.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.0
2.0
2.5
—
—
—
2.25
4.50
6.75
1.0
2.0
2.5
—
—
—
1.0
2.0
2.5
O
(V = 9.0 Vdc)
O
(V = 13.5 Vdc)
O
(V = 0.5 Vdc)
“1” Level
Source
Sink
V
5.0
10
15
4.0
8.0
12.5
—
—
—
4.0
8.0
12.5
2.75
5.50
8.25
—
—
—
4.0
8.0
12.5
—
—
—
Vdc
O
IH
(V = 1.0 Vdc)
O
(V = 1.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 5.0
– 1.0
– 2.5
– 10
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
1.0
2.5
10
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (0.7 µA/kHz) f + I /6
T DD
I = (1.4 µA/kHz) f + I /6
T DD
I = (2.2 µA/kHz) f + I /6
T
(Dynamic plus Quiescent,
Per Gate) (C = 50 pF)
L
DD
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.003.
T
L
DD
SS
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3
MC14007UB
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C)
L
A
V
Vdc
DD
(8.)
Characteristic
Symbol
Min
Typ
Max
Unit
t
ns
Output Rise Time
TLH
—
—
—
t
t
t
= (1.2 ns/pF) C + 30 ns
5.0
10
15
90
180
90
TLH
TLH
TLH
L
= (0.5 ns/pF) C + 20 ns
45
35
L
= (0.4 ns/pF) C + 15 ns
70
L
t
ns
ns
ns
Output Fall Time
THL
—
—
—
t
t
t
= (1.2 ns/pF) C + 15 ns
5.0
10
15
75
40
30
150
80
THL
THL
THL
L
= (0.5 ns/pF) C + 15 ns
L
= (0.4 ns/pF) C + 10 ns
60
L
t
Turn–Off Delay Time
PLH
—
—
—
t
t
t
= (1.5 ns/pF) C + 35 ns
5.0
10
15
60
30
25
125
75
PLH
PLH
PLH
L
= (0.2 ns/pF) C + 20 ns
L
= (0.15 ns/pF) C + 17.5 ns
55
L
t
Turn–On Delay Time
PHL
—
—
—
t
t
t
= (1.0 ns/pF) C + 10 ns
5.0
10
15
60
30
25
125
75
PHL
PHL
PHL
L
= (0.3 ns/pF) C + 15 ns
L
= (0.2 ns/pF) C + 15 ns
55
L
7. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
DD
= –V
V
= V
GS
DD GS
14
14
I
OH
V = V – V
DS OH DD
I
OL
V = V
DS OL
7
V
SS
7
V
SS
All unused inputs connected to ground.
All unused inputs connected to ground.
0
–4.0
–8.0
–12
–16
–20
20
16
12
8.0
4.0
0
a
V
= 15 Vdc
GS
b
c
c
a
V
= –5.0 Vdc
b
a
GS
10 Vdc
a
T = –55°C
A
b T = +25°C
T = +125°C
b
A
c
c
A
a
b
c
T = –55°C
A
c
b
T = +25°C
A
b
T = +125°C
A
c
–15 Vdc
–0
–10 Vdc
a
a
c
b
5.0 Vdc
6.0
a
–10
–8.0
–6.0
–4.0
–2.0
0
2.0
4.0
8.0
10
V , DRAIN VOLTAGE (Vdc)
DS
V , DRAIN VOLTAGE (Vdc)
DS
Figure 2. Typical Output Source Characteristics
Figure 3. Typical Output Sink Characteristics
These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.
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4
MC14007UB
V
DD
20 ns
20 ns
V
DD
0.01 µF
CERAMIC
90%
500 µF
I
D
V
in
50%
10%
V
SS
14
V
t
t
PLH
PHL
V
in
PULSE
GENERATOR
V
OH
90%
50%
10%
V
out
V
out
C
L
7
V
OL
SS
t
t
TLH
THL
Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms
APPLICATIONS
V
The MC14007UB dual pair plus inverter, which has
access to all its elements offers a number of unique circuit
applications. Figures 1, 5, and 6 are a few examples of the
device flexibility.
DD
OUT = A+B•C
14
13
11
2
1
+V
DD
2
DISABLE
3
10
12
B
OUTPUT
8
7
1
11
9
5
INPUT 10
12 OUTPUT
3
6
C
A
4
9
8
DISABLE
6
7
Substrates of P–channel devices internally connected to V
Substrates of N–channel devices internally connected to V
;
.
DD
SS
INPUT
DISABLE
OUTPUT
Figure 6. AOI Functions Using Tree Logic
1
0
X
0
0
1
0
1
OPEN
X = Don’t Care
Figure 5. 3–State Buffer
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5
MC14007UB
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
1
8
7
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
INCHES
DIM MIN MAX
0.770 18.16
MILLIMETERS
A
F
MIN
MAX
18.80
6.60
4.69
0.53
1.78
A
B
C
D
F
0.715
0.240
0.145
0.015
0.040
0.260
0.185
0.021
0.070
6.10
3.69
0.38
1.02
L
N
C
G
H
J
K
L
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
–––
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
–––
2.41
0.38
3.43
7.87
10
–T–
SEATING
PLANE
J
K
M
N
0.015
0.039
0.38
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–A–
14
1
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B–
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
8.75 0.337
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
–T–
SEATING
PLANE
J
M
G
J
K
M
P
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
M
S
S
0.25 (0.010)
T B
A
7
0
5.80
0.25
6.20 0.228
0.50 0.010
0.244
0.019
R
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6
MC14007UB
PACKAGE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
14X K REF
M
S
S
Y14.5M, 1982.
0.10 (0.004)
T U
V
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
–U–
0.25 (0.010) PER SIDE.
L
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
N
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
S
K
0.15 (0.006) T U
A
MILLIMETERS
MAX
INCHES
K1
DIM MIN
MIN
5.10 0.193
4.50 0.169
–––
0.15 0.002
0.75 0.020
MAX
0.200
0.177
0.047
0.006
0.030
–V–
A
B
C
4.90
4.30
–––
J J1
1.20
D
F
0.05
0.50
SECTION N–N
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.50
0.09
0.09
0.19
0.19
0.60 0.020
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.024
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
SEATING
PLANE
–T–
H
G
DETAIL E
D
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 965–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
14
8
Q
1
H
E
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
A
e
DIM MIN
MAX
2.05
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
e
H
E
0.50
A
b
1
M
1.27 BSC
0.050 BSC
0.13 (0.005)
0.10 (0.004)
7.40
0.50
1.10
0
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
1.42 –––
0.323
0.033
0.059
10
0.035
0.056
L
E
M
0
Q
Z
0.70
–––
1
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7
MC14007UB
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
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Phone: 81–3–5740–2745
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)
Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)
Email: ONlit@hibbertco.com
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
For additional information, please contact your local
Sales Representative.
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