MC14011UBCPG [ONSEMI]
UB-Suffix Series CMOS Gates; UB-后缀系列CMOS门
| 型号： | MC14011UBCPG |
| 厂家： | 
ONSEMI |
| 描述： | UB-Suffix Series CMOS Gates |
| 文件： | 总8页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14001UB, MC14011UB
UB−Suffix Series
CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired. The UB set of
CMOS gates are inverting non−buffered functions.
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MARKING
Features
DIAGRAMS
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Linear and Oscillator Applications
• Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature Range
• Double Diode Protection on All Inputs
14
1
PDIP−14
P SUFFIX
CASE 646
MC140xxUBCP
AWLYYWW
• Pin−for−Pin Replacements for Corresponding CD4000 Series UB
Suffix Devices
14
• Pb−Free Packages are Available*
SOIC−14
D SUFFIX
CASE 751A
140xxU
AWLYWW
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
1
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage Range
−0.5 to +18.0
V , V
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
xx
A
WL, L
YY, Y
= Specific Device Code
= Assembly Location
= Wafer Lot
in out
DD
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
= Year
WW, W = Work Week
P
D
Power Dissipation, per Package
(Note 1)
500
mW
T
Ambient Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
A
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
T
stg
T
Lead Temperature
L
(8−Second Soldering)
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
February, 2005 − Rev. 5
MC14001UB/D
MC14001UB, MC14011UB
LOGIC DIAGRAMS
MC14001UB
Quad 2−Input
NOR Gate
MC14011UB
Quad 2−Input
NAND Gate
1
1
2
3
3
2
5
5
4
4
6
6
8
8
10
11
10
11
9
9
12
12
13
13
V
= PIN 14
= PIN 7
FOR ALL DEVICES
DD
V
SS
PIN ASSIGNMENTS
MC14001UB
MC14011UB
Quad 2−Input NOR Gate
Quad 2−Input NAND Gate
IN 1
IN 2
1
2
3
4
5
6
14
V
IN 1
IN 2
1
2
3
4
5
6
14
V
DD
A
DD
A
13 IN 2
13 IN 2
12 IN 1
A
D
D
A
D
D
OUT
12 IN 1
OUT
A
A
OUT
IN 1
IN 2
11 OUT
10 OUT
OUT
IN 1
IN 2
11 OUT
10 OUT
B
D
C
B
D
C
B
B
B
B
9
8
IN 2
IN 1
9
8
IN 2
IN 1
C
C
V
SS
7
V
SS
7
C
C
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2
MC14001UB, MC14011UB
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
125_C
V
Vdc
DD
Characteristic
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
(Note 2)
Output Voltage
“0” Level
“1” Level
“0” Level
V
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
OL
V
in
= V or 0
DD
V
in
= 0 or V
V
OH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
DD
Input Voltage
(V = 4.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.0
2.0
2.5
−
−
−
2.25
4.50
6.75
1.0
2.0
2.5
−
−
−
1.0
2.0
2.5
O
(V = 9.0 Vdc)
O
(V = 13.5 Vdc)
O
(V = 0.5 Vdc)
“1” Level
Source
Sink
I
5.0
10
15
4.0
8.0
12.5
−
−
−
4.0
8.0
12.5
2.75
5.50
8.25
−
−
−
4.0
8.0
12.5
−
−
−
Vdc
O
IH
(V = 1.0 Vdc)
O
(V = 1.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
5.0
5.0
10
– 1.2
– 0.25
– 0.62
– 1.8
−
−
−
−
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
−
−
−
−
– 0.7
– 0.14
– 0.35
– 1.1
−
−
−
−
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
−
−
−
± 0.1
−
−
±0.00001 ± 0.1
−
−
± 1.0
mAdc
in
C
−
5.0
7.5
−
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
−
−
−
0.25
0.5
1.0
−
−
−
0.0005
0.0010
0.0015
0.25
0.5
1.0
−
−
−
7.5
15
30
mAdc
mAdc
DD
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
I
T
5.0
10
15
I = (0.3 mA/kHz) f + I /N
T DD
I = (0.6 mA/kHz) f + I /N
T
DD
Per Gate C = 50 pF)
I = (0.8 mA/kHz) f + I /N
T DD
L
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C − 50) Vfk
T
L
T
L
where: I is in mH (per package), C in pF, V = (V − V ) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
T
L
DD
SS
per package.
SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25_C)
L
A
Characteristic
Symbol
V
DD
Min
Typ
Max
Unit
Vdc
(Note 6)
Output Rise Time
t
ns
TLH
THL
t
t
t
= (3.0 ns/pF) C + 30 ns
= (1.5 ns/pF) C + 15 ns
= (1.1 ns/pF) C + 10 ns
5.0
10
15
−
−
−
180
90
65
360
180
130
TLH
TLH
TLH
L
L
L
Output Fall Time
t
ns
ns
t
t
t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
= (0.55 ns/pF) C + 9.5 ns
5.0
10
15
−
−
−
100
50
40
200
100
80
THL
THL
THL
L
L
L
Propagation Delay Time
t
, t
PLH PHL
t
t
t
, t
= (1.7 ns/pF) C + 30 ns
= (0.66 ns/pF) C + 22 ns
L
= (0.50 ns/pF) C + 15 ns
L
5.0
10
15
−
−
−
90
50
40
180
100
80
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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3
MC14001UB, MC14011UB
ORDERING INFORMATION
Device
†
Package
Shipping
MC14001UBCP
PDIP−14
500 Units / Rail
500 Units / Rail
MC14001UBCPG
PDIP−14
(Pb−Free)
MC14001UBD
SOIC−14
55 Units / Rail
55 Units / Rail
MC14001UBDG
SOIC−14
(Pb−Free)
MC14001UBDR2
SOIC−14
2500 / Tape & Reel
2500 / Tape & Reel
MC14001UBDR2G
SOIC−14
(Pb−Free)
MC14011UBCP
PDIP−14
500 Units / Rail
500 Units / Rail
MC14011UBCPG
PDIP−14
(Pb−Free)
MC14011UBD
SOIC−14
55 Units / Rail
55 Units / Rail
MC14011UBDG
SOIC−14
(Pb−Free)
MC14011UBDR2
SOIC−14
2500 / Tape & Reel
2500 / Tape & Reel
MC14011UBDR2G
SOIC−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
20 ns
20 ns
V
DD
V
INPUT
DD
14
90%
50%
10%
INPUT
*
OUTPUT
PULSE
GENERATOR
0 V
V
t
t
PLH
PHL
C
L
OH
90%
50%
10%
OUTPUT
INVERTING
V
OL
7
V
SS
*All unused inputs of AND, NAND gates must be
t
t
TLH
THL
connected to V
.
DD
All unused inputs of OR, NOR gates must be
connected to V
.
SS
Figure 1. Switching Time Test Circuit and Waveforms
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4
−10
−
−
10
8.0
−ꢀ6.0
−ꢀ4.0
−ꢀ2.0
0
0
2.0
4.0
8.0
10
−
−
−
−
MC14001UB, MC14011UB
MC14001UB CIRCUIT SCHEMATIC
MC14011UB CIRCUIT SCHEMATIC
(1/4 of Device Shown)
V
DD
3
14 10
14 V
DD
1
2
8
9
3, 4, 10, 11
1, 6, 8, 13
2, 5, 9, 12
6
5
13
12
7 V
SS
4
7
11
V
SS
16
14
12
10
8.0
6.0
4.0
2.0
0
16
14
V
= 15 Vdc
V
= 15 Vdc
DD
T = +ꢀ25°C
DD
Unused input
connected to
A
Unused input
b
a
connected to
.
V
SS
.
12
V
SS
a
One input only
Both inputs
10 Vdc
10 Vdc
a T = +ꢀ125°C
A
10
b
b T = −ꢀ55°C
A
8.0
6.0
4.0
8.0
6.0
b
a
a
b
5.0 Vdc
5.0 Vdc
15 Vdc
10 Vdc
a
b
4.0
2.0
0
a
b
a
b
2.0
0
0
2.0 4.0 6.0 8.0 10 12 14 16
0
2.0 4.0 6.0 8.0 10 12 14 16
V , INPUT VOLTAGE (Vdc)
in
V , INPUT VOLTAGE (Vdc)
in
Figure 2. Typical Voltage and
Current Transfer Characteristics
Figure 3. Typical Voltage Transfer
Characteristics versus Temperature
10
8.0
6.0
4.0
2.0
0
0
2.0
4.0
6.0
8.0
c
a
15 Vdc
b
a
c
V
= −ꢀ5.0 Vdc
GS
b
V
= 10 Vdc
GS
a
b
a
b
c
T = ꢀ55°C
T = ꢀ25°C
T = ꢀ125°C
A
c
A
A
a
b
c
T = −ꢀ55°C
A
c
T = +ꢀ25°C
A
T = +ꢀ125°C
A
b
−ꢀ10 Vdc
a
c
c
−ꢀ15 Vdc
b
b
5.0 Vdc
6.0
a
a
V
DS
, DRAIN VOLTAGE (Vdc)
V
DS
, DRAIN VOLTAGE (Vdc)
Figure 4. Typical Output Source Characteristics
Figure 5. Typical Output Sink Characteristics
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5
MC14001UB, MC14011UB
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646−06
ISSUE N
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
14
1
8
7
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
B
5. ROUNDED CORNERS OPTIONAL.
A
F
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
18.80
6.60
4.69
0.53
1.78
L
0.715
0.240
0.145
0.015
0.040
N
C
−T−
SEATING
PLANE
G
H
J
K
L
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
J
K
D 14 PL
H
G
M
M
N
_
_
M
0.13 (0.005)
0.015
0.039
1.01
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6
MC14001UB, MC14011UB
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A−03
ISSUE G
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
14
8
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
P 7 PL
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
M
B
0.25 (0.010)
7
1
G
F
R X 45
_
C
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
D 14 PL
M
S
S
A
0.25 (0.010)
T
B
1.27 BSC
0.19
0.10
0
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
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7
MC14001UB, MC14011UB
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC14001UB/D
相关型号：
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