MC14015BDTEL [ONSEMI]
IC,SHIFT REGISTER,CMOS,TSSOP,16PIN,PLASTIC;
| 型号： | MC14015BDTEL |
| 厂家： | 
ONSEMI |
| 描述： | IC,SHIFT REGISTER,CMOS,TSSOP,16PIN,PLASTIC 光电二极管 |
| 文件： | 总12页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14015B
Dual 4-Bit Static
Shift Register
The MC14015B dual 4–bit static shift register is constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4–state serial–input/parallel–output registers. Each register has
independent Clock and Reset inputs with a single serial Data input.
The register states are type D master–slave flip–flops. Data is shifted
from one stage to the next during the positive–going clock transition.
Each register can be cleared when a high level is applied on the Reset
line. These complementary MOS shift registers find primary use in
buffer storage and serial–to–parallel conversion where low power
dissipation and/or noise immunity is desired.
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC14015BCP
AWLYYWW
1
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge–Clocked Flip–Flop Design —
16
1
SOIC–16
D SUFFIX
CASE 751B
14015B
AWLYWW
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive going
edge of the clock pulse.
16
• Capable of Driving Two Low–power TTL Loads or One Low–power
TSSOP–16
DT SUFFIX
CASE 948F
14
015B
ALYW
Schottky TTL Load Over the Rated Temperature Range.
1
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
16
1
Symbol
Parameter
Value
Unit
V
SOEIAJ–16
F SUFFIX
CASE 966
MC14015B
ALYW
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P
D
Power Dissipation,
500
mW
WW, W = Work Week
per Package (Note 3.)
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
ORDERING INFORMATION
T
stg
Device
Package
PDIP–16
SOIC–16
Shipping
T
Lead Temperature
L
(8–Second Soldering)
MC14015BCP
MC14015BD
2000/Box
48/Rail
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
MC14015BDR2
SOIC–16 2500/Tape & Reel
TSSOP–16 2000/Tape & Reel
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14015BDT
MC14015BF
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
high–impedance circuit. For proper operation, V and V should be constrained
in
out
MC14015BFEL
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
August, 2000 – Rev. 4
MC14015B/D
MC14015B
TRUTH TABLE
C
D
0
R
0
0
0
1
Q0
Q
n
0
Q
Q
n–1
n–1
1
1
X
X
No Change
0
No Change
0
X
X = Don’t Care
Q = Q0, Q1, Q2, or Q3, as applicable.
n
Q
= Output of prior stage.
n–1
PIN ASSIGNMENT
C
Q3
Q2
Q1
Q0
R
1
2
3
4
5
6
7
8
16
15
14
V
DD
B
D
B
R
B
B
A
A
13 Q0
12 Q1
11 Q2
10 Q3
B
B
B
A
A
A
D
A
V
SS
9
C
A
BLOCK DIAGRAM
Q0
5
4
3
7
D
Q1
Q2
9
6
C
R
Q3
10
Q0
Q1
Q2
Q3
13
12
11
2
15
D
C
1
R
14
V
= PIN 16
= PIN 8
DD
V
SS
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2
MC14015B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55_C
25_C
125_C
V
Vdc
DD
(4.)
Min
Max
Min
Typ
Max
Min
Max
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or .05 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
(V = 0.5 or 4.5 Vdc) “1” Level
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (1.2 µA/kHz)f + I
T
I = (2.4 µA/kHz)f + I
T
I = (3.6 µA/kHz)f + I
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.002.
T
L
DD
SS
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3
MC14015B
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25_C)
L
A
(8.)
Characteristic
Symbol
V
DD
Min
Typ
Max
Unit
Output Rise and Fall Time
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
= (0.75 ns/pF) C + 12.5 ns
TLH THL
L
, t
= (0.55 ns/pF) C + 9.5 ns
L
TLH THL
Propagation Delay Time
Clock, Data to Q
t
t
,
ns
PLH
PHL
t
t
t
, t
= (1.7 ns/pF) C + 225 ns
= (0.66 ns/pF) C + 92 ns
L
= (0.5 ns/pF) C + 65 ns
L
5.0
10
15
—
—
—
310
125
90
750
250
170
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Reset to Q
t
t
t
, t
= (1.7 ns/pF) C + 375 ns
= (0.66 ns/pF) C + 147 ns
L
= (0.5 ns/pF) C + 95 ns
L
5.0
10
15
—
—
—
460
180
120
750
250
170
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Clock Pulse Width
t
5.0
10
15
400
175
135
185
85
55
—
—
—
ns
MHz
µs
WH
Clock Pulse Frequency
Clock Pulse Rise and Fall Times
Reset Pulse Width
f
cl
5.0
10
15
—
—
—
2.0
6.0
7.5
1.5
3.0
3.75
t
, t
5.0
10
15
—
—
—
—
—
—
15
5
4
TLH THL
t
5.0
10
15
400
160
120
200
80
60
—
—
—
ns
WH
Setup Time
t
su
5.0
10
15
350
100
75
100
50
40
—
—
—
ns
7. The formulas given are for typical characteristics only at 25_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
V
DD
0.01 µF
CERAMIC
I
D
PULSE
GENERATOR
2
500 µF
DD
Q0
Q1
Q2
Q3
D
C
C
L
PULSE
GENERATOR
1
C
L
C
L
R
C
L
V
SS
1
f
CLOCK
DATA
50%
Figure 1. Power Dissipation Test Circuit and Waveform
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4
MC14015B
t
t
t
THL
TLH
V
DD
DATA
90%
50%
10%
INPUT
0 V
su
V
t-
DD
t
t
THL
TLH
PULSE
GENERATOR
2
V
DD
90%
50%
10%
D
C
Q0
Q1
Q2
Q3
CLOCK
INPUT
C
L
0 V
SYNC
C
L
t
t
WL
WH
PULSE
GENERATOR
1
C
L
t
t
PHL
PLH
R
C
L
90%
50%
10%
V
SS
Q0
t
t
= t
= 50% Duty Cycle
WL
WH
t
t
THL
TLH
= t
≤ 20 ns
TLH
THL
Figure 2. Switching Test Circuit and Waveforms
V
DD
PULSE
GENERATOR
2
V
DD
CLOCK
INPUT
D
C
50%
Q0
Q1
Q2
Q3
0 V
C
L
t
su
SYNC
C
L
PULSE
GENERATOR
1
C
L
t
h
R
V
C
L
DD
DATA
50%
INPUT
V
SS
0 V
Figure 3. Setup and Hold Time Test Circuit and Waveforms
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5
SINGLE BIT
V
DD
Q
RESET
CLOCK
DATA
IN
TO D OF
NEXT BIT
V
SS
DATA INPUT BUFFER
RESET INPUT BUFFER
CLOCK INPUT BUFFER
V
DD
V
DD
V
DD
CLOCK
TO 4 BITS
RESET
CLOCK
IN
DATA TO
RESET
IN
DATA
IN
TO 4 BITS
FIRST BIT
V
SS
V
SS
V
SS
MC14015B
LOGIC DIAGRAMS
SINGLE BIT
Q
C
C
C
TO D OF
NEXT BIT
DATA
C
C
C
C
C
RESET
C
C
C
COMPLETE DEVICE
5
4
3
10
Q0
Q1
Q2
Q3
DATA INPUT BUFFER
D
7
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
CLOCK INPUT BUFFER
R
R
R
R
C
R
9
6
13
12
11
2
RESET INPUT BUFFER
DATA INPUT BUFFER
Q0
Q1
Q2
Q3
D
15
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
CLOCK INPUT BUFFER
RESET INPUT BUFFER
R
R
R
R
C
R
1
V
= PIN 16
= PIN 8
DD
V
SS
14
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7
MC14015B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
–A–
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
MILLIMETERS
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.70
C
L
SEATING
PLANE
–T–
G
H
J
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
K
L
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
_
_
_
_
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
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8
MC14015B
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
B
0.25 (0.010)
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
R X 45
K
_
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
C
G
J
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
7
0
_
_
_
_
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
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9
MC14015B
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T
U
V
S
U
0.15 (0.006) T
K
K1
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
2X L/2
J1
ąă2. CONTROLLING DIMENSION: MILLIMETER.
ąă3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
B
–U–
SECTION N–N
L
J
ąă4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
PIN 1
IDENT.
8
1
ąă5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
ąă6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
ąă7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
N
0.25 (0.010)
S
0.15 (0.006) T
U
A
M
–V–
N
F
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
5.10
4.50
1.20
0.15
0.75
MAX
0.200
0.177
0.047
0.006
0.030
A
B
4.90
4.30
---
0.193
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
–W–
C
G
H
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
J
0.10 (0.004)
J1
K
DETAIL E
H
SEATING
PLANE
–T–
D
G
K1
L
6.40 BSC
0.252 BSC
0
M
0
8
8
_
_
_
_
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10
MC14015B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ISSUE O
ąă2. CONTROLLING DIMENSION: MILLIMETER.
ąă3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
16
9
L
E
Q
1
H
E
M
_
ąă4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
ąă5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
8
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
MIN
---
A
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
---
0.05
0.35
0.18
9.90
5.10
2.05
A
1
0.20 0.002
0.50 0.014
0.27 0.007
b
c
D
E
10.50 0.390
5.45 0.201
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
10
_
0.035
0.031
0
_
_
_
0.70
---
1
Z
0.78
---
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11
MC14015B
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MC14015B/D
相关型号：
MC14015BFELG
4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, LEAD FREE, EIAJ, PLASTIC, SO-16
ONSEMI
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