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MC14015BFELG [ONSEMI]

4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, LEAD FREE, EIAJ, PLASTIC, SO-16;
MC14015BFELG
型号： MC14015BFELG
厂家： ONSEMI    ONSEMI
描述：

4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, LEAD FREE, EIAJ, PLASTIC, SO-16

光电二极管 输出元件 逻辑集成电路 触发器
文件： 总10页 (文件大小：133K)
中文：  中文翻译
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MC14015B  
Dual 4−Bit Static  
Shift Register  
The MC14015B dual 4−bit static shift register is constructed with  
MOS P−Channel and N−Channel enhancement mode devices in a  
single monolithic structure. It consists of two identical, independent  
4−state serial−input/parallel−output registers. Each register has  
independent Clock and Reset inputs with a single serial Data input.  
The register states are type D master−slave flip−flops. Data is shifted  
from one stage to the next during the positive−going clock transition.  
Each register can be cleared when a high level is applied on the Reset  
line. These complementary MOS shift registers find primary use in  
buffer storage and serial−to−parallel conversion where low power  
dissipation and/or noise immunity is desired.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
1
PDIP−16  
P SUFFIX  
CASE 648  
MC14015BCP  
AWLYYWWG  
Features  
16  
• Diode Protection on All Inputs  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
• Logic Edge−Clocked Flip−Flop Design  
SOIC−16  
D SUFFIX  
CASE 751B  
14015BG  
AWLYWW  
1
• Logic state is retained indefinitely with clock level either high or  
low; information is transferred to the output only on the positive  
going edge of the clock pulse  
16  
14  
015B  
ALYW  
TSSOP−16  
DT SUFFIX  
CASE 948F  
• Capable of Driving Two Low−power TTL Loads or One Low−power  
Schottky TTL Load Over the Rated Temperature Range  
• Pb−Free Packages are Available*  
1
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
16  
1
Symbol  
Parameter  
Value  
Unit  
V
SOEIAJ−16  
F SUFFIX  
CASE 966  
V
DC Supply Voltage Range  
−0.5 to +18.0  
MC14015B  
ALYWG  
DD  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
P
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
= Year  
WW, W = Work Week  
T
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
A
G
= Pb−Free Indicator  
T
stg  
T
Lead Temperature  
(8−Second Soldering)  
L
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
*For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
in  
out  
to the range V v (V or V ) v V  
.
DD  
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 6  
MC14015B/D  
 
MC14015B  
PIN ASSIGNMENT  
BLOCK DIAGRAM  
Q0  
5
C
Q3  
Q2  
Q1  
Q0  
R
1
2
3
4
5
6
7
8
16  
15  
14  
V
DD  
B
B
7
D
D
R
Q1  
4
B
B
Q2  
3
A
A
9
6
C
13 Q0  
12 Q1  
11 Q2  
10 Q3  
B
B
B
A
R
Q3  
10  
A
A
Q0  
Q1  
Q2  
Q3  
13  
12  
11  
2
D
15  
D
C
A
V
9
C
A
SS  
1
R
14  
V
= PIN 16  
= PIN 8  
DD  
V
SS  
TRUTH TABLE  
C
D
0
R
0
0
0
1
Q0  
0
Q
n
Q
Q
n−1  
n−1  
1
1
X
X
No Change  
0
No Change  
0
X
X = Don’t Care  
Q = Q0, Q1, Q2, or Q3, as applicable.  
n
Q
= Output of prior stage.  
n−1  
ORDERING INFORMATION  
Device  
†
Package  
Shipping  
MC14015BCP  
PDIP−16  
500 Units / Rail  
500 Units / Rail  
MC14015BCPG  
PDIP−16  
(Pb−Free)  
MC14015BD  
SOIC−16  
SOIC−16  
48 Units / Rail  
MC14015BDR2  
MC14015BDR2G  
2500 Units / Tape & Reel  
2500 Units / Tape & Reel  
SOIC−16  
(Pb−Free)  
MC14015BDTR2  
MC14015BFEL  
MC14015BFELG  
TSSOP−16*  
SOEIAJ−16  
2500 Units / Tape & Reel  
2000 Units / Tape & Reel  
2000 Units / Tape & Reel  
SOEIAJ−16  
(Pb−Free)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
*This package is inherently Pb−Free.  
http://onsemi.com  
2
MC14015B  
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V  
)
SS  
− 55_C  
25_C  
125_C  
V
Vdc  
DD  
Characteristic  
Symbol  
Unit  
Min  
Max  
Min  
Typ  
Max  
Min  
Max  
(Note 2)  
Output Voltage  
“0” Level  
“1” Level  
“0” Level  
V
5.0  
10  
15  
−
−
−
0.05  
0.05  
0.05  
−
−
−
0
0
0
0.05  
0.05  
0.05  
−
−
−
0.05  
0.05  
0.05  
Vdc  
OL  
V
in  
= V or 0  
DD  
V
5.0  
10  
15  
4.95  
9.95  
14.95  
−
−
−
4.95  
9.95  
14.95  
5.0  
10  
15  
−
−
−
4.95  
9.95  
14.95  
−
−
−
Vdc  
Vdc  
V
in  
= 0 or V  
OH  
DD  
Input Voltage  
(V = 4.5 or .05 Vdc)  
V
IL  
5.0  
10  
15  
−
−
−
1.5  
3.0  
4.0  
−
−
−
2.25  
4.50  
6.75  
1.5  
3.0  
4.0  
−
−
−
1.5  
3.0  
4.0  
O
(V = 9.0 or 1.0 Vdc)  
O
(V = 13.5 or 1.5 Vdc)  
O
(V = 0.5 or 4.5 Vdc) “1” Level  
V
5.0  
10  
15  
3.5  
7.0  
11  
−
−
−
3.5  
7.0  
11  
2.75  
5.50  
8.25  
−
−
−
3.5  
7.0  
11  
−
−
−
Vdc  
O
IH  
(V = 1.0 or 9.0 Vdc)  
O
(V = 1.5 or 13.5 Vdc)  
O
Output Drive Current  
I
mAdc  
OH  
(V  
(V  
(V  
(V  
= 2.5 Vdc)  
= 4.6 Vdc)  
= 9.5 Vdc)  
= 13.5 Vdc)  
Source  
Sink  
5.0  
5.0  
10  
– 3.0  
– 0.64  
– 1.6  
– 4.2  
−
−
−
−
– 2.4  
– 0.51  
− 1.3  
− 3.4  
– 4.2  
– 0.88  
– 2.25  
– 8.8  
−
−
−
−
– 1.7  
− 0.36  
– 0.9  
− 2.4  
−
−
−
−
OH  
OH  
OH  
OH  
15  
(V = 0.4 Vdc)  
(V = 0.5 Vdc)  
(V = 1.5 Vdc)  
I
5.0  
10  
15  
0.64  
1.6  
4.2  
−
−
−
0.51  
1.3  
3.4  
0.88  
2.25  
8.8  
−
−
−
0.36  
0.9  
2.4  
−
−
−
mAdc  
OL  
OL  
OL  
OL  
Input Current  
Input Capacitance  
I
15  
−
−
−
0.1  
−
−
−
0.00001  
5.0  
0.1  
7.5  
−
−
1.0  
−
mAdc  
in  
C
pF  
in  
(V = 0)  
in  
Quiescent Current  
(Per Package)  
I
5.0  
10  
15  
−
−
−
5.0  
10  
20  
−
−
−
0.005  
0.010  
0.015  
5.0  
10  
20  
−
−
−
150  
300  
600  
mAdc  
mAdc  
DD  
Total Supply Current (Notes 3 & 4)  
(Dynamic plus Quiescent,  
Per Package)  
I
5.0  
10  
15  
I
I
I
= (1.2 mA/kHz)f + I  
= (2.4 mA/kHz)f + I  
= (3.6 mA/kHz)f + I  
T
T
T
T
DD  
DD  
DD  
(C = 50 pF on all outputs, all  
L
buffers switching)  
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.  
3. The formulas given are for the typical characteristics only at 25_C.  
4. To calculate total supply current at loads other than 50 pF:  
I (C ) = I (50 pF) + (C − 50) Vfk  
T
L
T
L
where: I is in mA (per package), C in pF, V = (V − V ) in volts, f in kHz is input frequency, and k = 0.002.  
T
L
DD  
SS  
http://onsemi.com  
3
 
MC14015B  
SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25_C)  
L
A
Characteristic  
Symbol  
V
Min  
Typ  
Max  
Unit  
DD  
(Note 6)  
Output Rise and Fall Time  
t
,
ns  
TLH  
t
t
t
, t  
= (1.5 ns/pF) C + 25 ns  
= (0.75 ns/pF) C + 12.5 ns  
L
t
THL  
5.0  
10  
15  
−
−
−
100  
50  
40  
200  
100  
80  
TLH THL  
L
, t  
TLH THL  
, t  
= (0.55 ns/pF) C + 9.5 ns  
TLH THL  
L
Propagation Delay Time  
Clock, Data to Q  
t
t
,
ns  
PLH  
PHL  
t
t
t
, t  
= (1.7 ns/pF) C + 225 ns  
= (0.66 ns/pF) C + 92 ns  
L
= (0.5 ns/pF) C + 65 ns  
L
5.0  
10  
15  
−
−
−
310  
125  
90  
750  
250  
170  
PLH PHL  
L
, t  
PLH PHL  
, t  
PLH PHL  
Reset to Q  
t
t
t
, t  
= (1.7 ns/pF) C + 375 ns  
= (0.66 ns/pF) C + 147 ns  
L
= (0.5 ns/pF) C + 95 ns  
L
5.0  
10  
15  
−
−
−
460  
180  
120  
750  
250  
170  
PLH PHL  
L
, t  
PLH PHL  
, t  
PLH PHL  
Clock Pulse Width  
t
5.0  
10  
15  
400  
175  
135  
185  
85  
55  
−
−
−
ns  
MHz  
ms  
WH  
Clock Pulse Frequency  
Clock Pulse Rise and Fall Times  
Reset Pulse Width  
f
5.0  
10  
15  
−
−
−
2.0  
6.0  
7.5  
1.5  
3.0  
3.75  
cl  
t
, t  
5.0  
10  
15  
−
−
−
−
−
−
15  
5
4
TLH THL  
t
5.0  
10  
15  
400  
160  
120  
200  
80  
60  
−
−
−
ns  
WH  
Setup Time  
t
5.0  
10  
15  
350  
100  
75  
100  
50  
40  
−
−
−
ns  
su  
5. The formulas given are for typical characteristics only at 25_C.  
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.  
V
V
DD  
DD  
0.01 mF  
CERAMIC  
I
D
PULSE  
GENERATOR  
2
500 mF  
Q0  
Q1  
Q2  
Q3  
D
C
C
L
PULSE  
GENERATOR  
1
C
L
C
L
R
C
L
V
SS  
1
f
CLOCK  
DATA  
50%  
Figure 1. Power Dissipation Test Circuit and Waveform  
http://onsemi.com  
4
 
MC14015B  
t
t
t
THL  
TLH  
V
DD  
DATA  
90%  
50%  
10%  
INPUT  
0 V  
su  
V
t −  
DD  
t
t
THL  
TLH  
PULSE  
GENERATOR  
2
V
DD  
90%  
50%  
10%  
D
C
Q0  
Q1  
Q2  
Q3  
CLOCK  
INPUT  
C
L
0 V  
SYNC  
C
L
t
t
WL  
WH  
PULSE  
GENERATOR  
1
C
L
t
t
PHL  
PLH  
R
C
L
90%  
50%  
10%  
V
SS  
Q0  
t
t
= t  
= 50% Duty Cycle  
WH  
≤ 20 ns  
THL  
WL  
t
t
THL  
TLH  
= t  
TLH  
Figure 2. Switching Test Circuit and Waveforms  
V
DD  
PULSE  
GENERATOR  
2
V
DD  
CLOCK  
INPUT  
D
C
50%  
Q0  
Q1  
Q2  
Q3  
0 V  
C
L
t
su  
SYNC  
C
L
PULSE  
GENERATOR  
1
C
t
h
L
R
V
C
DD  
DATA  
INPUT  
L
50%  
V
0 V  
SS  
Figure 3. Setup and Hold Time Test Circuit and Waveforms  
http://onsemi.com  
5
MC14015B  
CIRCUIT SCHEMATICS  
http://onsemi.com  
6
MC14015B  
LOGIC DIAGRAMS  
SINGLE BIT  
Q
C
C
C
TO D OF  
NEXT BIT  
DATA  
C
C
C
C
C
RESET  
C
C
C
COMPLETE DEVICE  
5
4
3
10  
Q0  
Q1  
Q2  
Q3  
DATA INPUT BUFFER  
D
7
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
CLOCK INPUT BUFFER  
R
R
R
R
C
R
9
6
13  
12  
11  
2
RESET INPUT BUFFER  
DATA INPUT BUFFER  
Q0  
Q1  
Q2  
Q3  
D
15  
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
CLOCK INPUT BUFFER  
RESET INPUT BUFFER  
R
R
R
R
C
R
1
V
= PIN 16  
= PIN 8  
DD  
V
SS  
14  
http://onsemi.com  
7
MC14015B  
PACKAGE DIMENSIONS  
PDIP−16  
P SUFFIX  
PLASTIC DIP PACKAGE  
CASE 648−08  
ISSUE T  
NOTES:  
−A−  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION L TO CENTER OF LEADS  
WHEN FORMED PARALLEL.  
4. DIMENSION B DOES NOT INCLUDE  
MOLD FLASH.  
16  
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.  
INCHES  
DIM MIN MAX  
0.740 0.770 18.80 19.55  
MILLIMETERS  
F
C
L
MIN MAX  
A
B
C
D
F
0.250 0.270  
0.145 0.175  
0.015 0.021  
6.35  
3.69  
0.39  
1.02  
6.85  
4.44  
0.53  
1.77  
SEATING  
PLANE  
−T−  
0.040  
0.70  
G
H
J
K
L
0.100 BSC  
2.54 BSC  
1.27 BSC  
K
M
H
J
0.050 BSC  
0.008 0.015  
0.110 0.130  
0.295 0.305  
G
0.21  
0.38  
3.30  
7.74  
10  
D 16 PL  
2.80  
7.50  
0
M
M
0.25 (0.010)  
T A  
M
S
0
10  
_
_
_
_
0.020 0.040  
0.51  
1.01  
SOIC−16  
D SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751B−05  
ISSUE J  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
−A−  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.127 (0.005) TOTAL  
IN EXCESS OF THE D DIMENSION AT  
MAXIMUM MATERIAL CONDITION.  
16  
9
8
−B−  
P 8 PL  
M
S
B
0.25 (0.010)  
1
MILLIMETERS  
INCHES  
G
DIM MIN  
MAX  
10.00  
4.00  
1.75  
0.49  
1.25  
MIN  
MAX  
0.393  
0.157  
0.068  
0.019  
0.049  
A
B
C
D
F
9.80  
3.80  
1.35  
0.35  
0.40  
0.386  
0.150  
0.054  
0.014  
0.016  
F
R X 45  
K
_
G
J
1.27 BSC  
0.050 BSC  
C
0.19  
0.10  
0
0.25  
0.25  
7
0.008  
0.004  
0
0.009  
0.009  
7
−T−  
SEATING  
PLANE  
K
M
P
R
J
_
_
_
_
M
5.80  
0.25  
6.20  
0.50  
0.229  
0.010  
0.244  
0.019  
D
16 PL  
M
S
S
0.25 (0.010)  
T
B
A
http://onsemi.com  
8
MC14015B  
PACKAGE DIMENSIONS  
TSSOP−16  
DT SUFFIX  
PLASTIC TSSOP PACKAGE  
CASE 948F−01  
ISSUE A  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
16X KREF  
M
S
S
V
ANSI Y14.5M, 1982.  
0.10 (0.004)  
T
U
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION A DOES NOT INCLUDE MOLD  
FLASH. PROTRUSIONS OR GATE BURRS.  
MOLD FLASH OR GATE BURRS SHALL NOT  
EXCEED 0.15 (0.006) PER SIDE.  
S
U
0.15 (0.006) T  
K
K1  
4. DIMENSION B DOES NOT INCLUDE  
INTERLEAD FLASH OR PROTRUSION.  
INTERLEAD FLASH OR PROTRUSION SHALL  
NOT EXCEED 0.25 (0.010) PER SIDE.  
5. DIMENSION K DOES NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08  
(0.003) TOTAL IN EXCESS OF THE K  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
16  
9
2X L/2  
J1  
B
−U−  
SECTION N−N  
L
J
PIN 1  
IDENT.  
6. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
7. DIMENSION A AND B ARE TO BE  
DETERMINED AT DATUM PLANE −W−.  
8
1
N
0.25 (0.010)  
S
0.15 (0.006) T  
U
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN MAX  
A
M
−V−  
A
B
4.90  
4.30  
−−−  
0.05  
0.50  
5.10 0.193 0.200  
4.50 0.169 0.177  
N
C
1.20  
−−− 0.047  
D
F
0.15 0.002 0.006  
0.75 0.020 0.030  
F
G
H
J
J1  
K
K1  
L
0.65 BSC  
0.026 BSC  
DETAIL E  
0.18  
0.09  
0.09  
0.19  
0.19  
0.28 0.007 0.011  
0.20 0.004 0.008  
0.16 0.004 0.006  
0.30 0.007 0.012  
0.25 0.007 0.010  
−W−  
C
6.40 BSC  
0.252 BSC  
M
0
8
0
8
_
_
_
_
0.10 (0.004)  
DETAIL E  
H
SEATING  
PLANE  
−T−  
D
G
http://onsemi.com  
9
MC14015B  
PACKAGE DIMENSIONS  
SOEIAJ−16  
F SUFFIX  
PLASTIC EIAJ SOIC PACKAGE  
CASE 966−01  
ISSUE O  
NOTES:  
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
L
16  
9
E
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.  
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE  
MOLD FLASH OR PROTRUSIONS AND ARE  
MEASURED AT THE PARTING LINE. MOLD FLASH  
OR PROTRUSIONS SHALL NOT EXCEED 0.15  
(0.006) PER SIDE.  
Q
1
H
E
E
M
_
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
1
8
L
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT  
INCLUDE DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)  
TOTAL IN EXCESS OF THE LEAD WIDTH  
DIMENSION AT MAXIMUM MATERIAL CONDITION.  
DAMBAR CANNOT BE LOCATED ON THE LOWER  
RADIUS OR THE FOOT. MINIMUM SPACE  
BETWEEN PROTRUSIONS AND ADJACENT LEAD  
TO BE 0.46 ( 0.018).  
DETAIL P  
Z
D
VIEW P  
e
A
c
MILLIMETERS  
INCHES  
MIN MAX  
−−− 0.081  
DIM MIN  
MAX  
2.05  
0.20  
0.50  
0.27  
10.50  
5.45  
A
−−−  
0.05  
0.35  
0.18  
9.90  
5.10  
A
A
1
0.002  
0.008  
0.020  
0.011  
0.413  
0.215  
1
b
0.13 (0.005)  
b
c
0.014  
0.007  
0.390  
0.201  
0.10 (0.004)  
M
D
E
e
1.27 BSC  
0.050 BSC  
H
7.40  
0.50  
1.10  
8.20  
0.85  
1.50  
0.291  
0.020  
0.043  
0.323  
0.033  
0.059  
E
L
L
E
0
10  
10  
0.035  
M
Q
0
0.028  
_
_
_
_
0.70  
−−−  
0.90  
0.78  
1
Z
−−− 0.031  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800−282−9855 Toll Free  
USA/Canada  
ON Semiconductor Website: http://onsemi.com  
Order Literature: http://www.onsemi.com/litorder  
Literature Distribution Center for ON Semiconductor  
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA  
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada  
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
Japan: ON Semiconductor, Japan Customer Focus Center  
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051  
Phone: 81−3−5773−3850  
For additional information, please contact your  
local Sales Representative.  
MC14015B/D  

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