MC14018B [ONSEMI]
Presettable Divdie-By-N Counter; 预置Divdie - N计数器
| 型号： | MC14018B |
| 厂家： | 
ONSEMI |
| 描述： | Presettable Divdie-By-N Counter |
| 文件： | 总8页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC14018B contains five Johnson counter stages which are
asynchronously presettable and resettable. The counters are
synchronous, and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input.
Data on the Jam inputs will then be transferred to their respective Q
outputs (inverted). A logic 1 on the reset input will cause all Q outputs
to go to a logic 1 state.
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MARKING
DIAGRAMS
Division by any number from 2 to 10 can be accomplished by
connecting appropriate Q outputs to the data input, as shown in the
Function Selection table. Anti–lock gating is included in the
MC14018B to assure proper counting sequence.
16
PDIP–16
P SUFFIX
CASE 648
MC14018BCP
AWLYYWW
1
• Fully Static Operation
• Schmitt Trigger on Clock Input
16
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4018B
SOIC–16
D SUFFIX
CASE 751B
14018B
AWLYWW
1
16
SOEIAJ–16
F SUFFIX
CASE 966
MAXIMUM RATINGS (Voltages Referenced to V ) (Note NO TAG)
SS
MC14018B
AWLYWW
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage Range
–0.5 to +18.0
1
V , V
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
in out
DD
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P
D
Power Dissipation,
500
mW
per Package (Note NO TAG)
ORDERING INFORMATION
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
Device
Package
PDIP–16
SOIC–16
Shipping
T
stg
T
Lead Temperature
(8–Second Soldering)
L
MC14018BCP
MC14018BD
2000/Box
48/Rail
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
MC14018BDR2
SOIC–16 2500/Tape & Reel
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
MC14018BF
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14018BFEL
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14018B/D
MC14018B
PIN ASSIGNMENT
D
1
2
3
4
5
6
7
8
16
15
14
V
DD
in
JAM 1
JAM 2
Q2
R
C
13 Q5
12 JAM 5
11 Q4
Q1
Q3
JAM 3
10 PE
V
SS
9
JAM 4
FUNCTIONAL TRUTH TABLE
Preset
Jam
Clock Reset Enable Input
Qn
0
0
0
0
1
0
0
1
1
X
X
X
0
1
X
Qn
D *
n
X
X
X
1
0
1
*D is the Data input for that stage. Stage 1
n
has Data brought out to Pin 1.
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2
MC14018B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(4.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
(V = 0.5 or 4.5 Vdc) “1” Level
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (0.3 µA/kHz) f + I
T
I = (0.7 µA/kHz) f + I
T
I = (1.0 µA/kHz) f + I
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.001.
T
L
DD
SS
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3
MC14018B
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C)
L
A
All Types
V
Vdc
DD
(8.)
Characteristic
Output Rise and Fall Time
Symbol
Unit
Min
Typ
Max
t
, t
ns
TLH THL
t
t
t
, t
= (1.35 ns/pF) C + 32 ns
= (0.6 ns/pF) C + 20 ns
L
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
TLH THL
, t
= (0.4 ns/pF) C + 20 ns
TLH THL
L
Propagation Delay Time
Clock to Q
t
t
,
ns
PLH
PHL
t
t
t
, t
= (0.90 ns/pF) C + 265 ns
= (0.36 ns/pF) C + 102 ns
L
= (0.26 ns/pF) C + 72 ns
L
5.0
10
15
—
—
—
310
120
85
620
240
170
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Reset to Q
ns
ns
ns
t
t
t
= (0.90 ns/pF) C + 325 ns
= (0.36 ns/pF) C + 132 ns
= (0.26 ns/pF) C + 81 ns
5.0
10
15
—
—
—
370
150
100
740
300
200
PLH
PLH
PLH
L
L
L
Preset Enable to Q
t
t
t
, t
= (0.90 ns/pF) C + 325 ns
= (0.36 ns/pF) C + 132 ns
L
= (0.26 ns/pF) C + 81 ns
L
5.0
10
15
—
—
—
370
150
100
740
300
200
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Setup Time
Data (Pin 1) to Clock
t
su
5.0
10
15
200
100
80
0
0
0
—
—
—
Jam Inputs to Preset Enable
5.0
10
15
200
100
80
0
0
0
—
—
—
ns
ns
Data (Jam Inputs)–to–Preset
Enable Hold Time
t
h
5.0
10
15
540
500
480
270
250
240
—
—
—
Clock Pulse Width
t
5.0
10
15
400
200
160
200
100
80
—
—
—
ns
WH
WH
Reset or Preset Enable
Pulse Width
t
5.0
10
15
290
130
110
145
65
55
—
—
—
ns
Clock Rise and Fall Time
Clock Pulse Frequency
t
, t
5.0
10
15
ns
TLH THL
No Limit
f
cl
5.0
10
15
—
—
—
2.5
6.5
8.0
1.25
3.25
4.0
MHz
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
20 ns
V
DD
90%
50%
10%
ANY INPUT
V
SS
t
t
PHL
PLH
V
OH
90%
50%
10%
ANY OUTPUT
V
OL
t
t
THL
TLH
Figure 1. Switching Time Waveforms
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4
MC14018B
1
CLOCK
0
1
0
1
0
1
0
1
0
RESET
PRESET ENABLE
JAM 1
JAM 2
1
JAM 3
DON’T CARE
UNTIL PRESET ENABLE
GOES HIGH
TIMING DIAGRAM
(Q5 Connected to Data Input)
0
1
JAM 4
JAM 5
Q1
0
1
0
1
0
1
Q2
0
1
0
Q3
1
0
Q4
1
0
Q5
FUNCTION SELECTION
Connect
Counter
Mode
Data Input
(Pin 1) to:
Comments
Divide by 10
Divide by 8
Divide by 6
Divide by 4
Divide by 2
Q5
Q4
Q3
Q2
Q1
No external
components needed.
LOGIC DIAGRAM
Divide by 9
Divide by 7
Divide by 5
Divide by 3
Q5 • Q4
Q4 • Q3
Q3 • Q2
Q2 • Q1
Gate package needed
to provide AND
function. Counter
Skips all 1’s state
JAM 1
2
JAM 2
3
JAM 3
7
JAM 4
9
JAM 5
12
CLOCK
SHAPER
CLOCK 14
S
S
S
S
S
DATA
1
D
C
Q
D
C
Q
Q
D
C
Q
P
D
C
Q
D
Q
P
C
R P
R P
R
R P
R
RESET 15
PRESET ENABLE 10
V
V
= PIN 16
= PIN 8
DD
SS
5
4
6
11
13
Q5
Q1
Q2
Q3
Q4
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5
MC14018B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
G
H
J
K
L
M
S
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
PLANE
–T–
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
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6
MC14018B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE O
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
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7
MC14018B
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MC14018B/D
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