MC14052B_技术文档

The MC14051B, MC14052B, and MC14053B analog multiplexers

are digitally–controlled analog switches. The MC14051B effectively

implements an SP8T solid state switch, the MC14052B a DP4T, and

the MC14053B a Triple SPDT. All three devices feature low ON

impedance and very low OFF leakage current. Control of analog

signals up to the complete supply voltage range can be achieved.

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MARKING

DIAGRAMS

16

• Triple Diode Protection on Control Inputs

• Switch Function is Break Before Make

PDIP–16

P SUFFIX

CASE 648

MC140XXBCP

AWLYYWW

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Analog Voltage Range (V – V ) = 3.0 to 18 V

1

DD

EE

Note: V must be

V

EE

SS

16

1

• Linearized Transfer Characteristics

SOIC–16

D SUFFIX

CASE 751B

140XXB

AWLYWW

• Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical

• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053

• For 4PDT Switch, See MC14551B

16

• For Lower R , Use the HC4051, HC4052, or HC4053 High–Speed

ON

CMOS Devices

TSSOP–16

DT SUFFIX

CASE 948F

14

0XXB

ALYW

MAXIMUM RATINGS (Note 1.)

Symbol

Parameter

Value

Unit

1

V

DD

DC Supply Voltage (Referenced

–0.5 to +18.0

V

to V , V ≥ V )

EE

SS

16

1

V , V

in out

Input or Output Voltage Range

(DC or Transient) (Referen–

–0.5 to V + 0.5

V

SOEIAJ–16

F SUFFIX

CASE 966

DD

MC140XXB

AWLYWW

ced to V for Control Inputs

SS

and V for Switch I/O)

EE

I

in

Input Current (DC or Transient)

per Control Pin

±10

mA

XX

A

= Specific Device Code

= Assembly Location

I

Switch Through Current

±25

mA

SW

P

D

Power Dissipation,

per Package (Note 2.)

500

mW

WL or L = Wafer Lot

YY or Y = Year

WW or W = Work Week

T

Ambient Temperature Range

Storage Temperature Range

–55 to +125

–65 to +150

260

°C

A

T

stg

T

Lead Temperature

L

ORDERING INFORMATION

(8–Second Soldering)

Seedetailedorderingandshippinginformationinthepackage

dimensions section on page 12 of this data sheet.

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high–impedancecircuit. For proper operation, V and V should be constrained

in

out

to the range V

(V or V

)

V

DD

.

SS

in

out

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either V , V or V ). Unused outputs must be left open.

SS

EE

DD

Semiconductor Components Industries, LLC, 2000

1

Publication Order Number:

March, 2000 – Rev. 3

MC14051B/D

MC14051B, MC14052B, MC14053B

MC14051B

MC14052B

MC14053B

8–Channel Analog

Multiplexer/Demultiplexer

Dual 4–Channel Analog

Multiplexer/Demultiplexer

Triple 2–Channel Analog

Multiplexer/Demultiplexer

6

11

10

9

13

14

15

12

1

INHIBIT

A

B

6

INHIBIT

A

B

X0

X1

X2

X3

Y0

Y1

Y2

Y3

6

11

10

9

12

13

2

1

5

3

INHIBIT

A

B

C

X0

X1

14

15

X

Y

CONTROLS 10

CONTROLS

X

Y

13

3

9

12

14

15

11

1

5

2

4

C

COMMONS

OUT/IN

X0

X1

X2

X3

X4

X5

X6

X7

COMMONS

OUT/IN

X

3

SWITCHES

IN/OUT

SWITCHES

IN/OUT

Y0

Y1

Z0

Z1

COMMON

OUT/IN

SWITCHES

IN/OUT

Z

4

5

2

4

V

= PIN 16

= PIN 8

= PIN 7

V

= PIN 16

= PIN 8

= PIN 7

V

DD

V

SS

V

EE

= PIN 16

= PIN 8

= PIN 7

DD

SS

EE

Note: Control Inputs referenced to V , Analog Inputs and Outputs reference to V . V must be ≤ V .

SS

EE

PIN ASSIGMENT

MC14052B

MC14051B

MC14053B

X4

X6

X

1

2

3

4

5

6

7

8

16

V

DD

Y0

Y2

Y

1

2

3

4

5

6

7

8

16

V

DD

Y1

Y0

Z1

1

2

3

4

5

6

7

8

16

15

14

V

DD

15 X2

14 X1

13 X0

12 X3

15 X2

14 X1

Y

X

X7

X5

INH

Y3

Y1

INH

13

X

Z

13 X1

12 X0

11 X3

Z0

11

10

9

A

B

C

INH

11

10

9

A

B

C

V

EE

V

EE

10

9

A

B

V

EE

V

SS

V

SS

V

SS

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2

MC14051B, MC14052B, MC14053B

ELECTRICAL CHARACTERISTICS

– 55 C

25 C

125 C

(3.)

Characteristic

Symbol

V

DD

Test Conditions

Unit

Min

Max

Min

Typ

Max

Min Max

SUPPLY REQUIREMENTS (Voltages Referenced to V

)

EE

Power Supply Voltage

Range

V

DD

—

3.0

18

3.0

—

18

3.0

18

V

DD

– 3.0 ≥ V_SS≥ V

EE

Quiescent Current Per

Package

I

5.0 Control Inputs:

—

5.0

10

20

—

0.005

0.010

0.015

5.0

10

20

—

150

300

600

µA

DD

10

15

V

= V or V

,

DD

in

SS

Switch I/O: V

V

EE

I/O

switch

V

, and ∆V

DD

(4.)

500 mV

Total Supply Current

(Dynamic Plus

Quiescent, Per Package

I

5.0 T = 25 C only (The

µA

D(AV)

A

(0.07 µA/kHz) f + I

(0.20 µA/kHz) f + I

(0.36 µA/kHz) f + I

DD

10

15

channel component,

(V – V )/R , is

Typical

in

out

on

not included.)

CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to V

)

SS

Low–Level Input Voltage

High–Level Input Voltage

V

5.0

10

15

R

= per spec,

on

= per spec

—

1.5

3.0

4.0

—

2.25

4.50

6.75

1.5

3.0

4.0

—

1.5

3.0

4.0

V

IL

IH

in

I

off

V

5.0

10

15

R

= per spec,

3.5

7.0

11

—

3.5

7.0

11

2.75

5.50

8.25

—

3.5

7.0

11

—

on

I

off

= per spec

Input Leakage Current

Input Capacitance

I

15

—

V

in

= 0 or V

—

± 0.1

—

±0.00001 ± 0.1

—

1.0

—

µA

DD

C

—

5.0

7.5

pF

in

SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to V

)

EE

Recommended

Peak–to–Peak Voltage

Into or Out of the Switch

V

—

Channel On or Off

0

V

0

—

V

0

V

PP

I/O

DD

Recommended Static or

∆V

Channel On

0

600

—

600

300

—

mV

switch

Dynamic Voltage Across

(4.)

the Switch

(Figure 5)

Output Offset Voltage

ON Resistance

V

OO

V

in

= 0 V, No Load

—

10

—

µV

(4.)

R

5.0 ∆V

10

15

500 mV

V = V or V

in

—

800

400

220

—

250

120

80

1050

500

280

—

1200

520

300

Ω

on

switch

IL

IH

(Control), and V

=

in

0 to V (Switch)

DD

∆ON Resistance Between

Any Two Channels in the

Same Package

∆R

5.0

10

15

—

70

50

45

—

25

10

70

50

45

—

135

95

65

Ω

on

Off–Channel Leakage

Current (Figure 10)

I

off

15

V

= V or V

IH

—

± 100

—

± 0.05

± 100

—

±1000 nA

in

IL

(Control) Channel to

Channel or Any One

Channel

Capacitance, Switch I/O

C

—

Inhibit = V

—

10

—

pF

I/O

O/I

DD

Capacitance, Common O/I

Inhibit = V

DD

(MC14051B)

(MC14052B)

(MC14053B)

—

60

32

17

—

Capacitance, Feedthrough

(Channel Off)

C

—

Pins Not Adjacent

Pins Adjacent

—

0.15

0.47

—

pF

I/O

3. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.

4. For voltage drops across the switch (∆V ) > 600 mV ( > 300 mV at high temperature), excessive V current may be drawn, i.e. the

switch

DD

current out of the switch may contain both V

and switch input components. The reliability of the device will be unaffected unless the

DD

Maximum Ratings are exceeded. (See first page of this data sheet.)

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3

MC14051B, MC14052B, MC14053B

ELECTRICAL CHARACTERISTICS ^(5.)(C = 50 pF, T = 25 C) (V

V

SS

unless otherwise indicated)

L

A

EE

(6.)

V

DD

– V

Typ

EE

Vdc

All Types

Characteristic

Symbol

, t

Max

Unit

Propagation Delay Times (Figure 6)

t

ns

PLH PHL

Switch Input to Switch Output (R = 10 kΩ)

L

MC14051

t

, t

= (0.17 ns/pF) C + 26.5 ns

5.0

10

15

35

15

12

90

40

30

PLH PHL

L

, t

= (0.08 ns/pF) C + 11 ns

PLH PHL

L

, t

= (0.06 ns/pF) C + 9.0 ns

L

PLH PHL

MC14052

ns

t

, t

= (0.17 ns/pF) C + 21.5 ns

5.0

10

15

30

12

10

75

30

25

PLH PHL

L

, t

= (0.08 ns/pF) C + 8.0 ns

PLH PHL

L

, t

= (0.06 ns/pF) C + 7.0 ns

L

PLH PHL

MC14053

t

, t

= (0.17 ns/pF) C + 16.5 ns

5.0

10

15

25

8.0

6.0

65

20

15

PLH PHL

L

, t

= (0.08 ns/pF) C + 4.0 ns

PLH PHL

L

, t

= (0.06 ns/pF) C + 3.0 ns

L

PLH PHL

Inhibit to Output (R = 10 kΩ, V = V

)

t

, t

,

L

EE

SS

PHZ PLZ

Output “1” or “0” to High Impedance, or

High Impedance to “1” or “0” Level

MC14051B

t

, t

PZH PZL

5.0

10

15

350

170

140

700

340

280

MC14052B

MC14053B

5.0

10

15

300

155

125

600

310

250

ns

5.0

10

15

275

140

110

550

280

220

Control Input to Output (R = 10 kΩ, V = V

)

t

, t

L

EE

SS

PLH PHL

MC14051B

5.0

10

15

360

160

120

720

320

240

MC14052B

5.0

10

15

325

130

90

650

260

180

ns

MC14053B

5.0

10

15

300

120

80

600

240

160

Second Harmonic Distortion

—

10

0.07

—

%

(R = 10KΩ, f = 1 kHz) V = 5 V

L

in

PP

Bandwidth (Figure 7)

BW

10

17

—

MHz

(R = 1 kΩ, V = 1/2 (V –V ) p–p, C = 50pF

L

in

DD

EE

L

20 Log (V /V ) = – 3 dB)

out in

Off Channel Feedthrough Attenuation (Figure 7)

R = 1KΩ, V = 1/2 (V – V ) p–p

—

10

– 50

—

dB

L

in

DD

EE

f

= 4.5 MHz — MC14051B

= 30 MHz — MC14052B

= 55 MHz — MC14053B

in

Channel Separation (Figure 8)

(R = 1 kΩ, V = 1/2 (V –V ) p–p,

—

10

– 50

75

—

dB

L

in

DD

EE

f

in

= 3.0 MHz

Crosstalk, Control Input to Common O/I (Figure 9)

mV

(R = 1 kΩ, R = 10 kΩ

1

L

Control t

= t

= 20 ns, Inhibit = V

)

TLH

THL

SS

5. The formulas given are for the typical characteristics only at 25 C.

6. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.

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4

MC14051B, MC14052B, MC14053B

V

DD

V

DD

V

DD

IN/OUT

OUT/IN

V

EE

V

DD

LEVEL

CONVERTED

CONTROL

IN/OUT

OUT/IN

CONTROL

V

EE

Figure 1. Switch Circuit Schematic

16

V

DD

TRUTH TABLE

Control Inputs

Select

INH

A 11

B 10

6

BINARY TO 1–OF–8

DECODER WITH

INHIBIT

ON Switches

LEVEL

CONVERTER

Inhibit

C*

B

A

MC14051B MC14052B

MC14053B

C

9

0

1

0

1

0

1

X0

X1

X2

X3

Y0

Y1

Y2

Y3

X0

X1

X2

X3

Z0 Y0 X0

Z0 Y0 X1

Z0 Y1 X0

Z0 Y1 X1

8

V

SS

7

V

EE

X0 13

X1 14

X2 15

X3 12

0

1

0

1

0

1

0

1

X4

X5

X6

X7

Z1 Y0 X0

Z1 Y0 X1

Z1 Y1 X0

Z1 Y1 X1

3 X

X4

X5

X6

X7

1

5

2

4

1

x

None

*Not applicable for MC14052

x = Don’t Care

Figure 2. MC14051B Functional Diagram

16

V

DD

16

V

DD

INH

6

BINARY TO 1–OF–4

DECODER WITH

INHIBIT

LEVEL

CONVERTER

INH

A 11

B 10

6

A 10

BINARY TO 1–OF–2

DECODER WITH

INHIBIT

LEVEL

CONVERTER

B

9

C

9

8

V

SS

7

V

EE

X0 12

X1 14

X2 15

X3 11

8

V

SS

7

V

EE

13 X

X0 12

X1 13

14 X

Y0

Y1

Y2

Y3

1

5

2

4

Y0

Y1

Z0

Z1

2

1

5

3

15 Y

3

Y

4

Z

Figure 3. MC14052B Functional Diagram

Figure 4. MC14053B Functional Diagram

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5

MC14051B, MC14052B, MC14053B

TEST CIRCUITS

ON SWITCH

LOAD

CONTROL

SECTION

OF IC

A

B

C

PULSE

GENERATOR

V

out

V

C

L

INH

R

L

SOURCE

V

DD

V

EE

V

EE DD

Figure 5. ∆V Across Switch

Figure 6. Propagation Delay Times,

Control and Inhibit to Output

A, B, and C inputs used to turn ON

or OFF

the switch under test.

R

L

A

B

A

C

B

C

ON

V

out

INH

C = 50 pF

L

R

L

V

SS

OFF

INH

V

out

V

in

R

L

C = 50 pF

L

V

DD

– V

EE

V

DD

– V

EE

2

V

in

2

Figure 7. Bandwidth and Off–Channel

Feedthrough Attenuation

Figure 8. Channel Separation

(Adjacent Channels Used For Setup)

OFF CHANNEL UNDER TEST

V

DD

V

EE

A

B

C

CONTROL

SECTION

OF IC

OTHER

CHANNEL(S)

V

EE

V

out

V

DD

R

L

INH

C = 50 pF

L

R1

V

EE

COMMON

V

DD

Figure 9. Crosstalk, Control Input to

Common O/I

Figure 10. Off Channel Leakage

NOTE: See also Figures 7 and 8 in the MC14016B

data sheet.

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6

MC14051B, MC14052B, MC14053B

V

DD

KEITHLEY 160

DIGITAL

MULTIMETER

10 k

1 kΩ

RANGE

X–Y

V

DD

PLOTTER

V

EE

= V

SS

Figure 11. Channel Resistance (R_ON) Test Circuit

TYPICAL RESISTANCE CHARACTERISTICS

350

300

350

300

250

200

150

250

200

150

100

T = 125°C

A

T = 125°C

A

100

25°C

–55°C

50

0

50

0

–10 –8.0 –6.0 –4.0 –2.0

0

0.2 4.0 6.0 8.0

10

–10 –8.0 –6.0 –4.0 –2.0

0

0.2 4.0 6.0 8.0 10

V , INPUT VOLTAGE (VOLTS)

in

V , INPUT VOLTAGE (VOLTS)

in

Figure 12. V_DD= 7.5 V, V_EE= – 7.5 V

Figure 13. V_DD= 5.0 V, V_EE= – 5.0 V

350

300

700

600

T = 25°C

A

250

200

150

100

500

400

300

200

V

DD

= 2.5 V

T = 125°C

5.0 V

A

7.5 V

25°C

50

0

100

0

–55°C

–10 –8.0 –6.0 –4.0 –2.0

0

0.2 4.0 6.0 8.0 10

–10 –8.0 –6.0 –4.0 –2.0

0

0.2 4.0 6.0 8.0

10

V , INPUT VOLTAGE (VOLTS)

in

V , INPUT VOLTAGE (VOLTS)

in

Figure 15. Comparison at 25°C, V_DD= –V_EE

Figure 14. V_DD= 2.5 V, V_EE= – 2.5 V

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7

MC14051B, MC14052B, MC14053B

APPLICATIONS INFORMATION

Figure A illustrates use of the on–chip level converter

detailed in Figures 2, 3, and 4. The 0–to–5 V Digital Control

signal is used to directly control a 9 V analog signal.

peak. If voltage transients above V and/or below V are

DD EE

anticipated on the analog channels, external diodes (Dx) are

recommendedas shown in Figure B. These diodes should be

small signal types able to absorb the maximum anticipated

current surges during clipping.

p–p

The digital control logic levels are determined by V

DD

and V . The V voltage is the logic high voltage; the V

SS

DD

SS

voltage is logic low. For the example, V = + 5 V = logic

The absolute maximum potential difference between

DD

high at the control inputs; V = GND = 0 V = logic low.

V

and V is 18.0 V. Most parameters are specified up to

DD EE

SS

The maximum analog signal level is determined by V

15 V which is the recommended maximum difference

between V and V

DD

and V . The V

voltage determines the maximum

.

EE

DD

recommended peak above

V

.

SS

The

V

voltage

Balanced supplies are not required. However, V must

EE

SS

determines the maximum swing below V . For the

be greater than or equal to V . For example, V = + 10

SS

EE

DD

example, V

– V = 5 V maximum swing above V

;

V, V = + 5 V, and V – 3 V is acceptable. See the Table

DD

SS

SS EE

V

– V = 5 V maximum swing below V . The example

below.

SS

EE

SS

showsa±4.5Vsignalwhichallowsa1/2voltmarginateach

+5 V

–5 V

V

DD

V

SS

V

EE

+4.5 V

9 V

SWITCH

I/O

p–p

+5 V

9 V

ANALOG SIGNAL

COMMON

O/I

p–p

GND

MC14051B

MC14052B

MC14053B

ANALOG SIGNAL

EXTERNAL

CMOS

–4.5 V

DIGITAL

CIRCUITRY

0–TO–5 V DIGITAL

CONTROL SIGNALS

INHIBIT,

A, B, C

Figure A. Application Example

V

DD

V

DD

D

X

D

X

ANALOG

I/O

COMMON

O/I

D

X

D

X

V

EE

V

EE

Figure B. External Germanium or Schottky Clipping Diodes

POSSIBLE SUPPLY CONNECTIONS

Control Inputs

Logic High/Logic Low

In Volts

V

EE

In Volts

Maximum Analog Signal Range

In Volts

DD

SS

In Volts

+ 8

0

– 8

+ 8/0

+ 5/0

+ 8 to – 8 = 16 V

p–p

+ 5

– 12

0

+ 5 to – 12 = 17 V

p–p

+ 5

0

+ 5/0

+ 5 to 0 = 5 V

p–p

+ 5

0

– 5

+ 5/0

+ 5 to – 5 = 10 V

p–p

+ 10

+ 5

– 5

+ 10/ + 5

+ 10 to – 5 = 15 V

p–p

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8

MC14051B, MC14052B, MC14053B

PACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

NOTES:

CASE 648–08

ISSUE R

–A–

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

16

1

9

8

B

S

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

INCHES

DIM MIN MAX

0.740 0.770 18.80 19.55

MILLIMETERS

MIN MAX

F

A

B

C

D

F

C

L

0.250 0.270

0.145 0.175

0.015 0.021

6.35

3.69

0.39

1.02

6.85

4.44

0.53

1.77

0.040

0.70

SEATING

–T–

G

H

J

K

L

M

S

0.100 BSC

0.050 BSC

0.008 0.015

2.54 BSC

1.27 BSC

PLANE

K

M

0.21

0.38

3.30

7.74

10

H

J

0.110

0.295 0.305

10

0.020 0.040

0.130

2.80

7.50

0

G

D 16 PL

0

0.51

1.01

M

0.25 (0.010)

T A

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

–A–

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

16

1

9

–B–

P 8 PL

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

M

S

0.25 (0.010)

B

8

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

G

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MAX

0.393

0.157

0.068

0.019

0.049

F

A

B

C

D

F

9.80

3.80

1.35

0.35

0.40

10.00 0.386

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

R X 45

K

C

G

J

K

M

P

1.27 BSC

0.050 BSC

–T–

SEATING

PLANE

0.19

0.10

0

0.25 0.008

0.25 0.004

0.009

7

J

M

D

16 PL

7

0

5.80

0.25

6.20 0.229

0.50 0.010

0.244

0.019

M

S

0.25 (0.010)

T B

A

R

http://onsemi.com

9

MC14051B, MC14052B, MC14053B

PACKAGE DIMENSIONS

TSSOP–16

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

16X KREF

M

S

0.10 (0.004)

T U

V

S

0.15 (0.006) T U

K

K1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

16

9

2X L/2

Y14.5M, 1982.

J1

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS. MOLD

FLASH OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

B

–U–

SECTION N–N

L

J

PIN 1

IDENT.

8

1

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

N

0.25 (0.010)

S

0.15 (0.006) T U

A

M

–V–

N

F

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

A

B

C

4.90

4.30

–––

5.10 0.193 0.200

4.50 0.169 0.177

DETAIL E

1.20

––– 0.047

D

F

G

H

J

J1

K

K1

L

0.05

0.50

0.65 BSC

0.18

0.09

0.19

0.15 0.002 0.006

0.75 0.020 0.030

0.026 BSC

0.28 0.007 0.011

0.20 0.004 0.008

0.16 0.004 0.006

0.30 0.007 0.012

0.25 0.007 0.010

–W–

C

0.10 (0.004)

DETAIL E

H

SEATING

PLANE

–T–

D

G

6.40 BSC

0.252 BSC

M

0

8

0

8

http://onsemi.com

10

MC14051B, MC14052B, MC14053B

PACKAGE DIMENSIONS

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

NOTES:

ISSUE O

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

L

E

16

9

8

Q

1

H

E

M

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

E

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

1

L

DETAIL P

Z

D

VIEW P

e

MILLIMETERS

INCHES

A

DIM MIN

MAX

MIN

–––

MAX

0.081

0.008

0.020

0.011

0.413

0.215

c

A

1

–––

0.05

0.35

0.18

9.90

5.10

2.05

A

0.20 0.002

0.50 0.014

0.27 0.007

10.50 0.390

5.45 0.201

b

c

D

E

A

1

b

0.13 (0.005)

e

1.27 BSC

0.050 BSC

0.10 (0.004)

M

H

7.40

0.50

1.10

0

0.70

–––

8.20 0.291

0.85 0.020

1.50 0.043

10

0.90 0.028

0.78 –––

0.323

0.033

0.059

10

0.035

0.031

E

L

E

M

Q

0

1

Z

http://onsemi.com

11

MC14051B, MC14052B, MC14053B

ORDERING & SHIPPING INFORMATION:

Device

Package

PDIP–16

Shipping

2000 Units per Box

48 Units per Rail

MC14053BCP

MC14053BD

PDIP–16

SOIC–16

2000 Units per Box

48 Units per Rail

MC14051BCP

MC14051BD

SOIC–16

MC14053BDR2

MC14053BDT

MC14053BDTEL

MC14053BDTR2

MC14053BF

SOIC–16

2500 Units / Tape & Reel

96 Units per Rail

MC14051BDR2

MC14051BDT

MC14051BDTEL

MC14051BDTR2

MC14051BF

SOIC–16

2500 Units / Tape & Reel

96 Units per Rail

TSSOP–16

SOEIAJ–16

TSSOP–16

SOEIAJ–16

2000 Units / Tape & Reel

2500 Units / Tape & Reel

See Note 7.

2000 Units / Tape & Reel

2500 Units / Tape & Reel

See Note 7.

MC14053BFEL

See Note 7.

MC14051BFEL

See Note 7.

7. For ordering information on the EIAJ version of the SOIC

packages, please contact your local ON Semiconductor rep-

resentative.

MC14052BCP

MC14052BD

PDIP–16

SOIC–16

2000 Units per Box

48 Units per Rail

MC14052BDR2

MC14052BDT

MC14052BDTR2

MC14052BF

SOIC–16

2500 Units / Tape & Reel

96 Units per Rail

TSSOP–16

SOEIAJ–16

2500 Units / Tape & Reel

See Note 7.

MC14052BFEL

See Note 7.

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold

SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment:

CENTRAL/SOUTH AMERICA:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–spanish@hibbertco.com

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada

Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support

Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

Toll Free from Hong Kong & Singapore:

Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada

001–800–4422–3781

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

Email: ONlit–asia@hibbertco.com

EUROPE: LDC for ON Semiconductor – European Support

German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)

Email: ONlit–german@hibbertco.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549

Phone: 81–3–5740–2745

French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)

Email: ONlit–french@hibbertco.com

English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)

Email: ONlit@hibbertco.com

Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

For additional information, please contact your local

Sales Representative.

*Available from Germany, France, Italy, England, Ireland

MC14051B/D

http://onsemi.com

12


型号：	MC14052B
厂家：	ONSEMI
描述：	Analog Multiplexers/Demultiplexers 模拟多路复用器/多路解复用器解复用器
文件：	总12页 (文件大小：345K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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