MC14175BDG [ONSEMI]
Quad Type D Flip−Flop; 四路D型触发器
| 型号： | MC14175BDG |
| 厂家： | 
ONSEMI |
| 描述： | Quad Type D Flip−Flop |
| 文件： | 总6页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14175B
Quad Type D Flip−Flop
The MC14175B quad type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each of the four flip−flops is positive−edge
triggered by a common clock input (C). An active−low reset input (R)
asynchronously resets all flip−flops. Each flip−flop has independent
Data (D) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flip−flops for
counter and toggle applications.
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MARKING
DIAGRAMS
Features
16
PDIP−16
P SUFFIX
CASE 648
• Complementary Outputs
MC14175BCP
AWLYYWWG
• Static Operation
1
• All Inputs and Outputs Buffered
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
1
16
SOIC−16
D SUFFIX
CASE 751B
14175BG
AWLYWW
• Output Compatible with Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load
1
1
• Functional Equivalent to TTL 74175
• Pb−Free Packages are Available*
16
SOEIAJ−16
MC14175B
ALYWG
MAXIMUM RATINGS (Voltages Referenced to V
)
F SUFFIX
CASE 966
1
SS
Parameter
Symbol
Value
Unit
V
1
DC Supply Voltage Range
V
DD
−0.5 to +18.0
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
Input or Output Voltage Range
(DC or Transient)
V , V
in out
−0.5 to V
+ 0.5
V
DD
Input or Output Current (DC or Transient)
per Pin
I , I
in out
10
mA
G
= Pb−Free Package
Power Dissipation per Package (Note 1)
Ambient Temperature Range
P
500
mW
°C
D
ORDERING INFORMATION
T
A
−55 to +125
−65 to +150
260
†
Device
Package
Shipping
Storage Temperature Range
°C
MC14175BCP
PDIP−16
25 Units/Rail
25 Units/Rail
Lead Temperature (8−Second Soldering)
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
MC14175BCPG
PDIP−16
(Pb−Free)
MC14175BD
SOIC−16
48 Units/Rail
48 Units/Rail
Packages: – 7.0 mW/_C From 65_C To 125_C
MC14175BDG
SOIC−16
(Pb−Free)
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14175BDR2
SOIC−16
2500/Tape & Reel
2500/Tape & Reel
high−impedance circuit. For proper operation, V and V should be constrained
in
out
MC14175BDR2G SOIC−16
(Pb−Free)
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
MC14175BFEL
SOEIAJ−16
SS
DD
2000/Tape & Reel
2000/Tape & Reel
MC14175BFELG SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 6
MC14175B/D
MC14175B
R
Q0
Q0
D0
D1
Q1
Q1
1
2
3
4
5
6
7
8
16
V
DD
2
9
1
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
CLOCK
RESET
D0
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
3
7
4
6
10
11
15
14
5
D1
12
13
D2
V
SS
9
C
D3
Figure 1. Pin Assignment
V
DD
V
SS
= PIN 16
= PIN 8
TRUTH TABLE
Figure 2. Block Diagram
Inputs
Outputs
Clock
Data
Reset
Q
Q
0
1
X
X
1
1
1
0
0
1
Q
0
1
0
Q
1
No
Change
X
X = Don’t Care
Figure 3. Timing Diagram
Figure 4. Functional Block Diagram
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2
MC14175B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
Typ
125_C
V
DD
(Note 2)
Min
Max
Min
Max
Min
Max
Vdc
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
V
OL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
“0” Level
“1” Level
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
O
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
OL
I
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
−
−
−
0.1
−
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mAdc
in
C
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
mAdc
DD
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package)
I
T
5.0
10
15
I = (1.7 mA/kHz) f + I
T
DD
DD
DD
I = (3.4 mA/kHz) f + I
T
I = (5.0 mA/kHz) f + I
T
(C = 50 pF on all outputs, all
L
buffers switching)
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: I (C ) = I (50 pF) + (C – 50) Vfk where: I is in mA (per package), C in pF,
T
L
T
L
T
L
V = (V – V ) in volts, f in kHz is input frequency, and k = 0.004.
DD
SS
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3
MC14175B
SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25_C)
L
A
All Types
Typ
V
DD
(Note 6)
Vdc
Min
Max
Characteristic
Output Rise and Fall Time
Symbol
, t
Unit
t
ns
TLH THL
t
t
t
, t
= (1.35 ns/pF) C + 32 ns
5.0
10
15
−
−
−
100
50
40
200
100
80
TLH THL
L
, t
= (0.6 ns/pF) C + 20 ns
TLH THL
L
, t
= (0.4 ns/pF) C + 20 ns
TLH THL
L
Propagation Delay Time — Clock to Q, Q
t
t
, t
ns
ns
PLH PHL
t
t
t
, t
= (0.9 ns/pF) C + 175 ns
5.0
10
15
−
−
−
220
90
70
400
160
120
PLH PHL
L
, t
= (0.36 ns/pF) C + 72 ns
PLH PHL
L
, t
= (0.26 ns/pF) C + 57 ns
PLH PHL
L
Propagation Delay Time — Reset to Q, Q
, t
PHL PLH
t
t
t
= (0.9 ns/pF) C + 280 ns
5.0
10
15
−
−
−
325
130
100
500
200
150
PHL
PHL
PHL
L
= (0.36 ns/pF) C + 112 ns
L
= (0.26 ns/pF) C + 87 ns
L
Clock Pulse Width
t
5.0
10
15
250
100
75
110
45
35
−
−
−
ns
ns
WH
Reset Pulse Width
t
5.0
10
15
200
80
60
100
40
30
−
−
−
WL
Clock Pulse Frequency
Clock Pulse Rise and Fall Time
Data Setup Time
f
5.0
10
15
−
−
−
4.5
11
14
2.0
5.0
6.5
mHz
ms
cl
t
, t
5.0
10
15
−
−
−
−
−
−
15
5.0
4.0
TLH THL
t
su
5.0
10
15
120
50
40
60
25
20
−
−
−
ns
Data Hold Time
t
h
5.0
10
15
80
40
30
40
20
15
−
−
−
ns
Reset Removal Time
t
5.0
10
15
250
100
80
125
50
40
−
−
−
ns
rem
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14175B
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
J
0.21
0.38
3.30
7.74
10
G
2.80
7.50
0
D 16 PL
M
M
0.25 (0.010)
T
A
M
S
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
_
_
_
_
M
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
0.25 (0.010)
T
B
A
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5
MC14175B
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
E
16
9
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
Q
1
H
E
M
_
E
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN
−−−
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
−−−
0.05
0.35
0.10
9.90
5.10
2.05
A
A
1
0.20 0.002
0.50 0.014
0.20 0.007
1
b
0.13 (0.005)
b
c
0.10 (0.004)
M
D
E
10.50
5.45 0.201
0.390
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
0
10
0.90 0.028
10
_
0.035
0.031
M
Q
0
_
_
_
0.70
−−−
1
Z
0.78
−−−
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC14175B/D
相关型号：
MC14175BFL1
4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, EIAJ, PLASTIC, SOIC-16
ONSEMI
MC14175BFR2
4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, EIAJ, SO-16
ONSEMI
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