MC14512BCP [ONSEMI]
8-Channel Data Selector; 8通道数据选择器
| 型号： | MC14512BCP |
| 厂家： | 
ONSEMI |
| 描述： | 8-Channel Data Selector |
| 文件： | 总8页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC14512B is an 8–channel data selector constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. This data selector finds primary
application in signal multiplexing functions. It may also be used for
data routing, digital signal switching, signal gating, and number
sequence generation.
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• Diode Protection on All Inputs
• Single Supply Operation
• 3–State Output (Logic “1”, Logic “0”, High Impedance)
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC14512BCP
AWLYYWW
1
16
SOIC–16
D SUFFIX
CASE 751B
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
14512B
AWLYWW
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage Range
–0.5 to +18.0
1
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
16
I , I
Input or Output Current
(DC or Transient) per Pin
±10
mA
SOEIAJ–16
F SUFFIX
CASE 966
in out
MC14512B
AWLYWW
P
D
Power Dissipation,
500
mW
per Package (Note NO TAG)
1
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
A
= Assembly Location
T
stg
WL or L = Wafer Lot
YY or Y = Year
T
Lead Temperature
L
WW or W = Work Week
(8–Second Soldering)
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
ORDERING INFORMATION
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Device
Package
PDIP–16
SOIC–16
Shipping
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14512BCP
MC14512BD
2000/Box
48/Rail
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
MC14512BDR2
SOIC–16 2500/Tape & Reel
SS
DD
MC14512BF
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
MC14512BFL1
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14512B/D
MC14512B
TRUTH TABLE
Inhibit
C
B
A
Disable
Z
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
X0
X1
X2
X3
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
X4
X5
X6
X7
X
X
X
X
X
X
1
X
0
1
0
High
Impedance
X = Don’t Care
PIN ASSIGNMENT
X0
X1
X2
X3
X4
X5
X6
1
2
3
4
5
6
7
8
16
15
14
13
12
11
V
DD
DIS
Z
C
B
A
10 INH
X7
V
SS
9
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2
MC14512B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(4.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (0.8 µA/kHz) f + I
T
I = (1.6 µA/kHz) f + I
T
I = (2.4 µA/kHz) f + I
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
Three–State Leakage Current
I
TL
15
—
± 0.1
—
± 0.0001
± 0.1
—
± 3.0
µAdc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.001.
T
L
DD
SS
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3
MC14512B
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C, See Figure 1)
L
A
All Types
(8.)
Characteristic
Output Rise and Fall Time
Symbol
V
DD
Typ
Max
Unit
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
t
5.0
10
15
100
50
40
200
100
80
TLH THL
L
THL
, t
= (0.75 ns/pF) C + 12.5 ns
TLH THL
L
, t
= (0.55 ns/pF) C + 9.5 ns
L
TLH THL
Propagation Delay Time (Figure 2)
Inhibit, Control, or Data to Z
t
ns
ns
ns
PLH
5.0
10
15
330
125
85
650
250
170
Propagation Delay Time (Figure 2)
Inhibit, Control, or Data to Z
t
PHL
5.0
10
15
330
125
85
650
250
170
3–State Output Delay Times (Figure 3)
“1” or “0” to High Z, and
t
t
, t
, t
,
5.0
10
15
60
35
30
150
100
75
PHZ PLZ
PZH PZL
High Z to “1” or “0”
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
I
D
V
DD
DISABLE
INHIBIT
A
B
Z
C
L
C
X0
X1
X2
X3
X4
X5
X6
X7
PULSE
GENERATOR
V
in
50%
50%
DUTY
CYCLE
V
SS
Figure 1. Power Dissipation Test Circuit and Waveform
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4
MC14512B
V
DD
20 ns
t
20 ns
DATA
V
DD
90%
DISABLE
INHIBIT
A
B
C
50%
10%
V
SS
Z
t
PLH
PHL
90%
50%
V
OH
C
L
Z
10%
V
OL
X0
X1
X2
X3
X4
X5
X6
X7
t
t
THL
TLH
PULSE
GENERATOR
TEST CONDITIONS:
INHIBIT = V
SS
A, B, C = V
SS
20 ns
INHIBIT,
A, B, OR C
20 ns
V
DD
90%
50%
10%
V
SS
t
t
PLH
PHL
V
SS
V
OH
90%
50%
10%
Parameter
Inhibit to Z
A, B, C to Z
Test Conditions
A, B, C = V , X = V
DD
Z
SS
O
V
OL
Inh = V , X = V
t
t
TLH
SS
O
DD
THL
Figure 2. AC Test Circuit and Waveforms
V
DD
20 ns
PULSE
GENERATOR
20 ns
V
DD
V
DD
90%
50%
10%
DISABLE
INHIBIT
A
V
DD
Z
DISABLE
INPUT
V
SS
C
L
S1
S2
V
B
C
X0
X1
X2
X3
t
1 k
PZL
V
t
PLZ
S3
S4
OH
90%
≈ 2.5 V @ V = 5 V,
10 V, AND 15 V
DD
10%
OUTPUT
OUTPUT
V
OL
t
t
PZH
PHZ
≈ 2 V @ V = 5 V
DD
V
SS
≈ 6 V @ V = 10 V
OH
DD
90%
X4
X5
X6
X7
10%
≈ 10 V @ V = 15 V
DD
V
SS
V
OL
Switch Positions for 3–State Test
Test
S1
S2
S3
S4
t
Open
Closed
Closed
Open
Closed Closed
Open
Closed
Closed
Open
PHZ
V
SS
t
t
Open
Open
Open
Open
PLZ
PZL
PZH
t
Closed Closed
Figure 3. 3–State AC Test Circuit and Waveform
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5
MC14512B
LOGIC DIAGRAM
13
12
C
B
15
11
1
DISABLE
10
A
DATA
BUS
X0
SELECTED
DEVICE
INHIBIT
2
3
4
5
6
7
9
V
I
DD
OD
X1
X2
MC14512B
MC14512B
MC14512B
I
L
LOAD
14
Z
I
TL
X3
X4
X5
X6
I
TL
V
SS
X7
1
1
OUT
IN
IN
OUT
2
2
TRANSMISSION
GATE
3–STATE MODE OF OPERATION
Output terminals of several MC14512B 8–Bit Data
Selectors can be connected to a single date bus as shown.
One MC14512B is selected by the 3–state control, and the
remaining devices are disabled into a high–impedance “off”
state. The number of 8–bit data selectors, N, that may be
connected to a bus line is determined from the output drive
(including fanout to other device inputs), and can be
calculated by:
IOD – IL
N =
+ 1
ITL
N must be calculated for both high and low logic state of the
bus line.
current, I , 3–state or disable output leakage current, I
,
TL
OD
and the load current, I , required to drive the bus line
L
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6
MC14512B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
G
H
J
K
L
M
S
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
PLANE
–T–
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
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7
MC14512B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE O
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
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MC14512B/D
相关型号：
MC14512BCPD
Multiplexer, 4000/14000/40000 Series, 1-Func, 8 Line Input, 1 Line Output, True Output, CMOS, PDIP16, 648-08
MOTOROLA
MC14512BCPDS
4000/14000/40000 SERIES, 8 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16, 648-06
MOTOROLA
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