MC14515BDWR2G [ONSEMI]
4−Bit Transparent Latch / 4−to−16 Line Decoder; 4位透明锁存器/ 4至16线译码器
| 型号： | MC14515BDWR2G |
| 厂家： | 
ONSEMI |
| 描述： | 4−Bit Transparent Latch / 4−to−16 Line Decoder |
| 文件： | 总8页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14514B, MC14515B
4−Bit Transparent Latch /
4−to−16 Line Decoder
The MC14514B and MC14515B are two output options of a 4 to 16
line decoder with latched inputs. The MC14514B (output active high
option) presents a logical “1” at the selected output, whereas the
MC14515B (output active low option) presents a logical “0” at the
selected output. The latches are R−S type flip−flops which hold the
last input data presented prior to the strobe transition from “1” to “0”.
These high and low options of a 4−bit latch / 4 to 16 line decoder are
constructed with N−channel and P−channel enhancement mode
devices in a single monolithic structure. The latches are R−S type
flip−flops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
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MARKING
DIAGRAMS
24
1
PDIP−24
P SUFFIX
CASE 709
1
MC145xxBCP
AWLYYWWG
These complementary circuits find primary use in decoding
applications where low power dissipation and/or high noise immunity
is desired.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
24
1
SOIC−24
DW SUFFIX
CASE 751E
MC145xxB
AWLYYWWG
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load the Rated Temperature Range
• Pb−Free Packages are Available*
1
xx
A
= 14 or 15
= Assembly Location
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
WL = Wafer Lot
YY = Year
WW = Work Week
= Pb−Free Package
Parameter
Symbol
Value
Unit
V
DC Supply Voltage Range
V
DD
−0.5 to +18.0
G
Input or Output Voltage Range
(DC or Transient)
V , V
in out
−0.5 to V
+0.5
V
DD
Input or Output Current (DC or Transient) I , I
per Pin
10
mA
in out
PIN ASSIGNMENT
Power Dissipation per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature (8−Second Soldering)
P
500
mW
°C
D
ST
D1
D2
S7
S6
S5
1
2
3
4
5
6
24
V
DD
T
A
−55 to +125
−65 to +150
260
23 INH
22 D4
21 D3
20 S10
19 S11
T
stg
°C
T
°C
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
S4
S3
S1
7
8
9
18 S8
17 S9
16 S14
15 S15
14 S12
13 S13
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
S2 10
S0 11
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
V
SS
12
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
ORDERING INFORMATION
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 6
MC14514B/D
MC14514B, MC14515B
BLOCK DIAGRAM
DECODE TRUTH TABLE (Strobe = 1)*
Selected Output
Data Inputs
11
S0
S1
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
MC14514 = Logic “1”
MC14515 = Logic “0”
9
Inhibit
D
C
B
A
10
8
V
V
= PIN 24
S2
DD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
S0
S1
S2
S3
= PIN 12
SS
S3
7
S4
6
2
3
A
B
C
D
S5
DATA 1
DATA 2
DATA 3
DATA 4
5
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
S4
S5
S6
S7
S6
4
S7
TRANSPARENT
LATCH
4 TO 16
18
17
20
19
14
13
16
15
21
22
S8
DECODER
S9
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
S8
S9
S10
S11
S10
S11
S12
S13
S14
S15
1
STROBE
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
S12
S13
S14
S15
1
X
X
X
X
All Outputs = 0, MC14514
All Outputs = 1, MC14515
23
INHIBIT
X = Don’t Care
*Strobe = 0, Data is latched
ORDERING INFORMATION
†
Device
MC14514BCP
Package
Shipping
PDIP−24
15 Units / Rail
30 Units / Rail
MC14514BCPG
PDIP−24
(Pb−Free)
MC14514BDW
SOIC−24
SOIC−24
MC14514BDWR2
MC14514BDWR2G
1000 / Tape & Reel
SOIC−24
(Pb−Free)
MC14515BCP
PDIP−24
15 Units / Rail
30 Units / Rail
MC14515BCPG
PDIP−24
(Pb−Free)
MC14515BDW
SOIC−24
SOIC−24
MC14515BDWR2
MC14515BDWR2G
1000 / Tape & Reel
SOIC−24
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
MC14514B, MC14515B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
Typ
125_C
V
Vdc
DD
(Note 2)
Min
Max
Min
Max
Min
Max
Characteristic
Output Voltage
Symbol
Unit
“0” Level
V
OL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
“1” Level
V
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
OH
V
= 0 or V
in
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
“0” Level
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
O
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 1.2
– 0.25
– 0.62
– 1.8
−
−
−
−
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
−
−
−
−
– 0.7
– 0.14
– 0.35
– 1.1
−
−
−
−
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
OL
I
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance (V = 0)
I
15
−
−
−
0.1
−
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mAdc
pF
in
C
in
in
Quiescent Current (Per Package)
I
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
DD
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package)
I
TL
5.0
10
15
I = (1.35 mA/kHz) f + I
mAdc
T
DD
DD
DD
I = (2.70 mA/kHz) f + I
T
I = (4.05 mA/kHz) f + I
T
(C = 50 pF on all outputs, all
L
buffers switching)
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: I (C ) = I (50 pF) + (C – 50) Vfk where: I is in mA (per package), C in pF,
T
L
T
L
T
L
V = (V – V ) in volts, f in kHz is input frequency, and k = 0.002.
DD
SS
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3
MC14514B, MC14515B
SWITCHING CHARACTERISTICS (Note 5) (C = 50 pF, T = 25_C)
L
A
All Types
Typ
(Note 6)
Min
Max
Characteristic
= (3.0 ns/pF) C + 30 ns
Symbol
V
Unit
DD
Output Rise Time
t
ns
TLH
t
t
t
5.0
10
15
−
−
−
180
90
65
360
180
130
TLH
TLH
TLH
L
= (1.5 ns/pF) C + 15 ns
L
= (1.1 ns/pF) C + 10 ns
L
Output Fall Time
t
ns
ns
ns
ns
THL
t
t
t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
= (0.55 ns/pF) C + 9.5 ns
5.0
10
15
−
−
−
100
50
40
200
100
80
THL
THL
THL
L
L
L
Propagation Delay Time; Data, Strobe to S
t ,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 465 ns
= (0.86 ns/pF) C + 192 ns
= (0.5 ns/pF) C + 125 ns
L
t
5.0
10
15
−
−
−
550
225
150
1100
450
300
PLH PHL
L
PHL
, t
PLH PHL
L
, t
PLH PHL
Inhibit Propagation Delay Times
t
,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 315 ns
= (0.66 ns/pF) C + 117 ns
= (0.5 ns/pF) C + 75 ns
L
t
5.0
10
15
−
−
−
400
150
100
800
300
200
PLH PHL
L
PHL
, t
PLH PHL
L
, t
PLH PHL
Setup Time Data to Strobe
t
su
5.0
10
15
250
100
75
125
50
38
−
−
−
Hold Time Strobe to Data
Strobe Pulse Width
t
5.0
10
15
– 20
0
10
– 100
– 40
– 30
−
−
−
ns
ns
h
t
WH
5.0
10
15
350
100
75
175
50
38
−
−
−
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
DD
V
DS
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
STROBE
INHIBIT
D1
For MC14515B
1. For P−channel: Inhibit = V
2. For N−channel: Inhibit = V
2. and D1−D4 constitute binary
2. code for “output under test.”
DD
SS
For MC14514B
1. For P−channel: Inhibit = V
1. and D1−D4 constitute
1. binary code for “output
1. under test.”
SS
D2
I
D
2. For N−channel: Inhibit = V
DD
D3
EXTERNAL
POWER SUPPLY
D4
V
SS
Figure 1. Drain Characteristics Test Circuit
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4
MC14514B, MC14515B
V
DD
0.01 mF
I
D
CERAMIC
500
mF
V
DD
24
20 ns
20 ns
PULSE
GENERATOR
V
D1
D2
DD
S0
90%
10%
V
in
C
C
L
V
SS
D3
D4
STROBE
INHIBIT
S15
L
12
V
SS
Figure 2. Dynamic Power Dissipation Test Circuit and Waveform
V
DD
STROBE
OUTPUT S0
OUTPUT S1
S0
S1
t
t
THL
TLH
INHIBIT
D1
20 ns
C
L
C
L
V
V
DD
90%
50%
INPUT
PROGRAMMABLE
PULSE
GENERATOR
10%
SS
t
t
PHL
PLH
D2
D3
V
DD
90%
50%
10%
OUTPUT
V
SS
OUTPUT S15
S15
t
t
THL
D4
TLH
V
SS
C
L
Figure 3. Switching Time Test Circuit and Waveforms
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5
MC14514B, MC14515B
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6
MC14514B, MC14515B
COMPLEX DATA ROUTING
Two MC14512 eight−channel data selectors are used here
times faster then the shift frequency of the input registers,
the most significant bit (MSB) from each register could be
selected for transfer to the data bus. Therefore, all of the
most significant bits from all of the registers can be
transferred to the data bus before the next most significant
bit is presented for transfer by the input registers.
Information from the 3−state bus is redistributed by the
MC14514B four−bit latch/decoder. Using the four−bit
address, D1 thru D4, the information on the inhibit line can
be transferred to the addressed output line to the desired
output registers, A thru P. This distribution of data bits to the
output registers can be made in many complex patterns. For
example, all of the most significant bits from the input
registers can be routed into output register A, all of the next
most significant bits into register B, etc. In this way
horizontal, vertical, or other methods of data slicing can be
implemented.
with the MC14514B four−bit latch/decoder to effect a
complex data routing system. A total of 16 inputs from data
registers are selected and transferred via a 3−state data bus
to a data distributor for rearrangement and entry into 16
output registers. In this way sequential data can be re−routed
or intermixed according to patterns determined by data
select and distribution inputs.
Data is placed into the routing scheme via the eight inputs
on both MC14512 data selectors. One register is assigned to
each input. The signals on A0, A1, and A2 choose one of
eight inputs for transfer out to the 3−state data bus. A fourth
signal, labelled Dis, disables one of the MC14512 selectors,
assuring transfer of data from only one register.
In addition to a choice of input registers, 1 thru 16, the rate
of transfer of the sequential information can also be varied.
That is, if the MC14512 were addressed at a rate that is eight
DATA ROUTING SYSTEM
INPUT
REGISTERS
DATA
TRANSFER
3−STATE
DATA BUS
DATA
DISTRIBUTION
OUTPUT
REGISTERS
DIS
D0
D1
D2
Q
REGISTER 1
D1 D2 D3 D4
S0
D3
D4
REGISTER A
STROBE
S1
S2
D5
D6
S3
REGISTER 8
D7
A0 A1 A2
S4
S5
S6
DATA
S7
SELECT
S8
S9
S10
S11
S12
S13
S14
S15
A0 A1 A2
D0
D1
D2
D3
D4
D5
D6
D7
Q
REGISTER 9
INHIBIT
REGISTER P
REGISTER 16
DIS
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7
MC14514B, MC14515B
PACKAGE DIMENSIONS
PDIP−24
CASE 709−02
ISSUE D
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
J
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. CONTROLLING DIMENSION: INCH.
24
13
12
L
B
1
INCHES
DIM MIN MAX
MILLIMETERS
A
M
MIN
MAX
32.13
14.22
5.08
A
B
C
D
F
1.235
0.540
0.155
0.014
0.040
1.265 31.37
0.560 13.72
N
C
0.200
0.022
0.060
3.94
0.36
1.02
0.56
1.52
K
G
H
J
0.100 BSC
2.54 BSC
0.065
0.008
0.115
0.080
0.015
0.135
1.65
0.20
2.92
2.03
0.38
3.43
H
F
SEATING
PLANE
K
L
G
D
0.600 BSC
15.24 BSC
M
N
0
0.020
15
_
0.040
0
_
0.51
15
_
1.02
_
SOIC−24
CASE 751E−04
ISSUE E
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
24
13
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B− 12X P
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
M
B
0.010 (0.25)
1
12
MILLIMETERS
INCHES
MIN
0.601
DIM MIN
MAX
MAX
0.612
0.299
0.104
0.019
0.035
24X D
J
A
B
C
D
F
15.25
7.40
2.35
0.35
0.41
15.54
7.60 0.292
2.65 0.093
0.49 0.014
0.90 0.016
M
S
S
0.010 (0.25)
T
A
B
F
G
J
1.27 BSC
0.050 BSC
0.23
0.13
0
0.32 0.009
0.29 0.005
0.013
0.011
8
R X 45
_
K
M
P
R
8
10.55
0
0.395
_
_
_
_
C
K
10.05
0.25
0.415
0.029
0.75 0.010
−T−
SEATING
PLANE
M
22X G
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC14514B/D
相关型号：
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