MC14516B [ONSEMI]
Binary Up/Down Counter; 二进制加/减计数器
| 型号： | MC14516B |
| 厂家： | 
ONSEMI |
| 描述： | Binary Up/Down Counter |
| 文件： | 总12页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC14516B synchronous up/down binary counter is
constructed with MOS P–channel and N–channel enhancement mode
devices in a monolithic structure.
This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
UP/DOWN input. The state of the counter changes on the positive
transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high
to the reset (R) pin.
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC14516BCP
AWLYYWW
1
This CMOS counter finds primary use in up/down and difference
counting. Other applications include: (1) Frequency synthesizer
applications where low power dissipation and/or high noise immunity
is desired, (2) Analog–to–digital and digital–to–analog conversions,
and (3) Magnitude and sign generation.
16
SOIC–16
D SUFFIX
CASE 751B
14516B
AWLYWW
1
• Diode Protection on All Inputs
16
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Internally Synchronous for High Speed
• Logic Edge–Clocked Design — Count Occurs on Positive Going
Edge of Clock
SOEIAJ–16
F SUFFIX
CASE 966
MC14516B
AWLYWW
1
• Single Pin Reset
• Asynchronous Preset Enable Operation
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky Load Over the Rated Temperature Range
ORDERING INFORMATION
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
Device
Package
PDIP–16
SOIC–16
Shipping
Symbol
Parameter
Value
Unit
V
MC14516BCP
MC14516BD
2000/Box
48/Rail
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
MC14516BDR2
SOIC–16 2500/Tape & Reel
I , I
Input or Output Current
(DC or Transient) per Pin
±10
mA
in out
MC14516BF
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
MC14516BFEL
P
D
Power Dissipation,
500
mW
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
per Package (Note 3.)
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
T
stg
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this high–impedance circuit. For proper
T
Lead Temperature
(8–Second Soldering)
L
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
operation, V and V should be constrained to the
in
out
range V
(V or V
)
V
DD
.
SS
in
out
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Unused inputs must always be tied to an appropriate
logicvoltagelevel(e.g., eitherV orV ). Unusedout-
SS
DD
puts must be left open.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14516B/D
MC14516B
PIN ASSIGNMENT
PE
1
2
3
4
5
6
7
8
16
15
V
DD
Q3
P3
C
14 Q2
13 P2
12 P1
11 Q1
10 U/D
P0
CARRY IN
Q0
CARRY OUT
V
SS
9
R
BLOCK DIAGRAM
PE
Q0
1
5
6
CARRY IN
RESET
UP/DOWN
CLOCK
P0
Q1
Q2
Q3
9
11
14
2
10
15
4
P1
12
13
3
P2
CARRY
OUT
P3
7
V
V
= PIN 16
= PIN 8
DD
SS
TRUTH TABLE
Preset
Enable
Carry In
Up/Down
Reset
Clock
Action
No Count
Count Up
Count Down
Preset
1
X
1
0
0
0
1
X
0
0
0
0
1
X
0
0
0
X
X
X
X
X
X
Reset
X = Don’t Care
NOTE: Whencounting up, the Carry Out signal is normally high and is low only
whenQ0throughQ3arehighandCarryIn islow.Whencountingdown,
Carry Out is low only when Q0 through Q3 and Carry In are low.
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2
MC14516B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(4.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (0.58 µA/kHz) f + I
T
I = (1.20 µA/kHz) f + I
T
I = (1.70 µA/kHz) f + I
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.001.
T
L
DD
SS
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3
MC14516B
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C)
L
A
All Types
(8.)
Characteristic
Output Rise and Fall Time
Symbol
V
DD
Unit
Min
Typ
Max
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
t
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
THL
, t
= (0.75 ns/pF) C + 12.5 ns
TLH THL
L
, t
= (0.55 ns/pF) C + 9.5 ns
TLH THL
L
Propagation Delay Time
Clock to Q
t
t
,
ns
PLH
PHL
t
t
t
, t
= (1.7 ns/pF) C + 230 ns
= (0.66 ns/pF) C + 97 ns
= (0.5 ns/pF) C + 75 ns
5.0
10
15
—
—
—
315
130
100
630
260
200
PLH PHL
L
, t
PLH PHL
L
, t
PLH PHL
L
Clock to Carry Out
t
t
t
t
,
ns
ns
ns
ns
PLH
t
t
t
t
, t
= (1.7 ns/pF) C + 230 ns
= (0.66 ns/pF) C + 97 ns
= (0.5 ns/pF) C + 75 ns
5.0
10
15
—
—
—
315
130
100
630
260
200
PLH PHL
L
PHL
, t
PLH PHL
L
, t
PLH PHL
L
Carry In to Carry Out
,
PLH
t
t
t
t
, t
= (1.7 ns/pF) C + 230 ns
= (0.66 ns/pF) C + 97 ns
= (0.5 ns/pF) C + 75 ns
5.0
10
15
—
—
—
180
80
60
360
160
120
PLH PHL
L
PHL
, t
PLH PHL
L
, t
PLH PHL
L
,
Preset or Reset to Q
PLH
t
5.0
10
15
—
—
—
315
130
100
630
360
200
t
t
t
, t
= (1.7 ns/pF) C + 230 ns
= (0.66 ns/pF) C + 97 ns
L
= (0.5 ns/pF) C + 75 ns
PHL
PLH PHL L
, t
PLH PHL
, t
PLH PHL
L
,
Preset or Reset to Carry Out
PLH
t
5.0
10
15
—
—
—
550
225
150
1100
450
300
t
t
t
, t
= (1.7 ns/pF) C + 465 ns
= (0.66 ns/pF) C + 192 ns
L
= (0.5 ns/pF) C + 125 ns
PHL
PLH PHL L
, t
PLH PHL
, t
PLH PHL
L
Reset Pulse Width
Clock Pulse Width
Clock Pulse Frequency
t
5.0
10
15
380
200
160
190
100
80
—
—
—
ns
ns
w
t
5.0
10
15
350
170
140
200
100
75
—
—
—
WH
f
cl
5.0
10
15
—
—
—
3.0
6.0
8.0
1.5
3.0
4.0
MHz
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.
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4
MC14516B
SWITCHING CHARACTERISTICS (9.) (C = 50 pF, T = 25 C) (continued)
L
A
All Types
(10.)
Characteristic
Preset or Reset Removal Time
Symbol
V
Unit
Min
Typ
Max
DD
t
5.0
10
15
650
230
180
325
115
90
—
ns
rem
The Preset or Reset signal must be low prior to a
positive–going transition of the clock.
—
Clock Rise and Fall Time
t
t
,
5.0
10
15
—
—
—
—
—
—
15
5
4
µs
ns
ns
ns
ns
ns
ns
ns
TLH
THL
Setup Time
t
t
t
5.0
10
15
260
120
100
130
60
50
—
—
—
su
Carry In to Clock
Hold Time
t
h
5.0
10
15
0
20
20
– 60
– 20
0
—
—
—
Clock to Carry In
Setup Time
5.0
10
15
500
200
150
250
100
75
—
—
—
su
Up/Down to Clock
Hold Time
t
h
5.0
10
15
– 70
– 10
0
– 160
– 60
– 40
—
—
—
Clock to Up/Down
Setup Time
Pn to PE
5.0
10
15
– 40
– 30
– 25
– 120
– 70
– 50
—
—
—
su
Hold Time
PE to Pn
t
h
5.0
10
15
480
420
420
240
210
210
—
—
—
Preset Enable Pulse Width
t
5.0
10
15
200
100
80
100
50
40
—
—
—
WH
9. The formulas given are for the typical characteristics only at 25 C.
10.Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.
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5
MC14516B
V
DD
500 pF
I
D
0.01 µF
CERAMIC
PE
Q0
CARRY IN
20 ns
20 ns
CLOCK
R
Q1
Q2
Q3
V
DD
90%
UP/DOWN
CLOCK
P0
C
L
50%
PULSE
GENERATOR
10%
V
SS
VARIABLE
WIDTH
C
L
P1
C
L
P2
CARRY
OUT
P3
C
L
C
L
Figure 1. Power Dissipation Test Circuit and Waveform
LOGIC DIAGRAM
P0
4
Q0
6
P1 Q1
12 11
P2
13
Q2
14
P3
3
Q3
2
RESET
9
1
PRESET
ENABLE
CLOCK 15
P
P
P
P
PE
C
Q
PE
C
Q
Q
PE
C
Q
PE
Q
C
T
CARRY OUT
7
T
Q
T
T
Q
Q
CARRY IN
5
UP/DOWN 10
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6
MC14516B
TOGGLE FLIP–FLOP
FLIP–FLOP FUNCTIONAL TRUTH TABLE
Preset
PARALLEL IN
Enable
Clock
T
X
0
Q
n+1
P
PE
C
Q
Q
1
X
Parallel In
0
Q
Q
Q
n
n
n
T
0
1
0
X
X = Don’t Care
t
su
t
rem
1
f
cl
t
h
CARRY IN OR
UP/DOWN
V
DD
50%
V
SS
V
DD
50%
CLOCK
V
SS
t
w(H)
t
w(H)
V
DD
PRESET ENABLE
V
SS
t
TLH
CARRY OUT ONLY
Q OR CARRY OUT
0
V
OH
90%
10%
90%
10%
V
OL
t
PHL
t
t
t
THL
PLH
PLH
t
rem
V
DD
50%
RESET
V
SS
t
w
Figure 2. Switching Time Waveforms
PIN DESCRIPTIONS
CONTROLS
INPUTS
P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) — Data
on these inputs is loaded into the counter when PE is taken
high.
PE, Preset Enable, (Pin 1)— Asynchronouslyloadsdata
on the Preset Inputs. This pin is active high and inhibits the
clock when high.
Carry In, (Pin 5) — This active–low input is used when
Cascadingstages. CarryInisusuallyconnectedtoCarryOut
of the previous stage. While high, Clock is inhibited.
Clock, (Pin 15) — Binary data is incremented or
decremented, depending on the direction of count, on the
positive transition of this input.
R, Reset, (Pin 9) — Asynchronously resets the Q out–
puts to a low state. This pin is active high and inhibits the
clock when high.
Up/Down, (Pin 10) — Controls the direction of count,
high for up count, low for down count.
SUPPLY PINS
OUTPUTS
V , Negative Supply Voltage, (Pin 8) — This pin is
SS
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) —
Binary data is present on these outputs with Q0
corresponding to the least significant bit.
CarryOut, (Pin7)—Usedwhencascadingstages,Carry
Out is usually connected to Carry In of the next stage. This
synchronous output is active low and may also be used to
indicate terminal count.
usually connected to ground.
V
DD
, Positive Supply Voltage, (Pin 16) — This pin is
connected to a positive supply voltage ranging from 3.0
volts to 18.0 volts.
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7
MC14516B
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q4
Q5
Q1
Q6
Q2
Q7
Q3
PRESET
ENABLE
0 = COUNT
Q3
Q0
PE
PE
1 = PRESET
TERMINAL COUNT
INDICATOR
C
out
C
out
C
in
C
in
L.S.D.
MC14516B
M.S.D.
MC14516B
CLOCK
U/D
CLOCK
U/D
1 = UP
0 = DOWN
R
R
P0
P1
P2
P3
P0
P1
P2
P3
P7
P0
P1
P2
P3
P4
P5
P6
+V
DD
+V
DD
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
CLOCK
RESET
RESISTORS = 10 k
+V
DD
OPEN = COUNT
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit(M.S.D.)isdisabledwhileC ishigh. WhenthecountoftheL.S.D. reaches0(countdownmode)orreaches15(count
in
up mode), C goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
out
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
Figure 3. Presettable Cascaded 8–Bit Up/Down Counter
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8
MC14516B
TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8–BIT UP/DOWN COUNTER
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9
MC14516B
f
out
BUFFER
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q5
Q1
Q6
Q2
Q7
Q3
Q0
PE
PE
C
out
C
out
C
in
C
in
L.S.D.
MC14516B
M.S.D.
MC14516B
CLOCK
U/D
CLOCK
U/D
R
R
P0
P1
P2
P3
P3
P0
P1
P2
P3
P7
P0
P1
P2
P4
P5
P6
+V
DD
+V
DD
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
CLOCK (f )
RESISTORS = 10 k
in
f
n
in
RESET
f
out
=
+V
DD
OPEN = COUNT
NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,
the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.
Figure 4. Programmable Cascaded Frequency Divider
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10
MC14516B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
G
H
J
K
L
M
S
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
PLANE
–T–
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
http://onsemi.com
11
MC14516B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE O
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
ON Semiconductor and
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