MC14528BFR1 [ONSEMI]
4000/14000/40000 SERIES, DUAL MONOSTABLE MULTIVIBRATOR, PDSO16, EIAJ, SO-16;
| 型号： | MC14528BFR1 |
| 厂家： | 
ONSEMI |
| 描述： | 4000/14000/40000 SERIES, DUAL MONOSTABLE MULTIVIBRATOR, PDSO16, EIAJ, SO-16 时钟 光电二极管 逻辑集成电路 |
| 文件： | 总12页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC14528B is a dual, retriggerable, resettable monostable
multivibrator. It may be triggered from either edge of an input pulse,
and produces an output pulse over a wide range of widths, the duration
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of which is determined by the external timing components, C and
X
R .
X
MARKING
DIAGRAMS
16
• Separate Reset Available
• Diode Protection on All Inputs
• Triggerable from Leading or Trailing Edge Pulse
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement with the MC14538B
PDIP–16
P SUFFIX
CASE 648
MC14528BCP
AWLYYWW
1
16
SOIC–16
D SUFFIX
CASE 751B
14528B
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
16
Symbol
Parameter
Value
Unit
V
SOEIAJ–16
F SUFFIX
CASE 966
V
DD
DC Supply Voltage Range
–0.5 to +18.0
MC14528B
AWLYWW
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
1
I , I
Input or Output Current
(DC or Transient) per Pin
±10
mA
in out
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
P
D
Power Dissipation,
500
mW
per Package (Note 3.)
WW or W = Work Week
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
T
stg
ORDERING INFORMATION
T
Lead Temperature
L
Device
Package
PDIP–16
SOIC–16
Shipping
(8–Second Soldering)
MC14528BCP
MC14528BD
2000/Box
48/Rail
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
MC14528BDR2
SOIC–16 2500/Tape & Reel
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14528BF
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
MC14528BFEL
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
to the range V
(V or V
)
V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14528B/D
MC14528B
PIN ASSIGNMENT
V
1
2
3
4
5
6
7
8
16
15
V
DD
SS
C 1/R 1
V
SS
X
X
RESET 1
A1
14 C 2/R 2
X X
13 RESET 2
12 A2
B1
Q1
11 B2
Q1
10 Q2
V
SS
9
Q2
BLOCK DIAGRAM
C 1
X
R 1
X
V
DD
1
2
6
7
4
5
Q1
Q1
A1
B1
3
RESET 1
C 2
X
R 2
X
V
DD
15
14
10
9
12
11
Q2
Q2
A2
B2
13
RESET 2
V
DD
= PIN 16
V
SS
= PIN 1, PIN 8, PIN 15
R AND C ARE EXTERNAL COMPONENTS
X
X
ONE–SHOT SELECTION GUIDE
100 ns 1 s
10 s 100 s 1 ms 10 ms 100 ms 1 s
10 s
MC14528B
MC14536B
MC14538B
MC14541B
MC4538A*
23 HR
5 MIN.
*LIMITED OPERATING VOLTAGE (2–6 V)
TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
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2
MC14528B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
DD
(4.)
Vdc
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
mAdc
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 1.2
– 0.64
– 1.6
– 4.2
—
—
—
—
– 1.0
– 0.51
– 1.3
– 3.4
– 1.7
– 0.88
– 2.25
– 8.8
—
—
—
—
– 0.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
I
OH
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
I
OL
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
–8
Total Supply Current at an
external load Capacitance (C )
and at external timing
I
T
—
I (C , C ) = [(C + 0.36C )V f + 2x10
T
L
X
L
X
DD
–3
–2 2
R C (V
) f] x 10
where: I in µA (per circuit), C and C in pF, R in megohms,
L
X
X
DD
T
L
X
X
capacitance (C ), use the
formula —
V
DD
in Vdc, f in kHz is input frequency.
X
(5.)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
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3
MC14528B
SWITCHING CHARACTERISTICS (8.) (C = 50 pF, T = 25 C)
L
A
C
pF
R
kΩ
V
DD
Vdc
X
X
(9.)
Characteristic
Output Rise and Fall Time
Symbol
Min
Typ
Max
Unit
t
,
—
—
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
= (0.75 ns/pF) C + 12.5 ns
TLH THL
L
, t
= (0.55 ns/pF) C + 9.5 ns
L
TLH THL
Turn–Off, Turn–On Delay Time — A or B to Q or Q
t
t
,
15
5.0
10
ns
ns
PLH
t
t
t
, t
= (1.7 ns/pF) C + 240 ns
= (0.66 ns/pF) C + 87 ns
L
= (0.5 ns/pF) C + 65 ns
L
5.0
10
15
—
—
—
325
120
90
650
240
180
PLH PHL
L
PHL
, t
PLH PHL
, t
PLH PHL
Turn–Off, Turn–On Delay Time — A or B to Q or Q
t
,
1000
PLH
t
t
t
, t
= (1.7 ns/pF) C + 620 ns
= (0.66 ns/pF) C + 257 ns
L
= (0.5 ns/pF) C + 185 ns
L
t
PHL
5.0
10
15
—
—
—
705
290
210
—
—
—
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Input Pulse Width — A or B
t
15
1000
15
5.0
10
5.0
10
15
150
75
55
70
30
30
—
—
—
ns
ns
ns
µs
%
WH
t
5.0
10
15
—
—
—
70
30
30
—
—
—
WL
Output Pulse Width — Q or Q
(For C < 0.01 µF use graph for
t
t
5.0
10
5.0
10
15
—
—
—
550
350
300
—
—
—
W
X
appropriate V level.)
DD
Output Pulse Width — Q or Q
10,000
10,000
15
5.0
10
15
15
10
15
30
50
55
45
90
95
W
(For C > 0.01 µF use formula:
X
(6.)
t
W
= 0.2 R C Ln [V – V ])
X X DD SS
Pulse Width Match between Circuits in the same
package
t1 – t2
10
5.0
10
15
—
—
—
6.0
8.0
8.0
25
35
35
Reset Propagation Delay — Reset to Q or Q
t
,
5.0
10
5.0
10
15
—
—
—
325
90
60
600
225
170
ns
ns
ns
ns
PLH
t
PHL
1000
15
5.0
10
15
—
—
—
1000
300
250
—
—
—
Retrigger Time
t
rr
5.0
10
5.0
10
15
0
0
0
—
—
—
—
—
—
1000
5.0
10
15
0
0
0
—
—
—
—
—
—
External Timing Resistance
External Timing Capacitance
R
C
—
—
—
—
—
—
5.0
—
1000
kΩ
µF
X
X
(7.)
No Limits
6.
R is in Ohms, C is in farads, V and V in volts, PW in seconds.
X X DD SS out
7. If C > 15 µF, Use Discharge Protection Diode D , per Fig. 9.
X
X
8. The formulas given are for the typical characteristics only at 25 C.
9. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14528B
FUNCTION TABLE
Inputs
Outputs
Reset
A
B
Q
Q
H
H
H
L
H
H
L
Not Triggered
Not Triggered
H
H
H
L, H,
L
H
L, H,
Not Triggered
Not Triggered
L
X
X
X
X
L
H
Not Triggered
V
DD
V
DD
16
16
I
OL
A
B
A
B
Q
Q
OPEN
Q
Q
V
OL
V
OH
RESET
8
OPEN
RESET
8
I
OH
V
V
SS
SS
Figure 1. Output Source Current Test Circuit
Figure 2. Output Sink Current Test Circuit
V
DD
0.1 F
CERAMIC
500 pF
I
D
R
X
R ′
X
C
X
C ′
X
20 ns
20 ns
V
DD
V
in
90%
10%
DUTY CYCLE = 50%
A
Q
Q
V
in
0 V
B
C
L
RESET
A′
C
L
Q′
Q′
C
L
B′
C
L
RESET′
V
SS
Figure 3. Power Dissipation Test Circuit and Waveforms
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5
MC14528B
V
DD
INPUT CONNECTIONS
*C = 15 pF
X
Characteristics
Reset
A
B
*C = 15 pF
R = 5.0 k
X
R ′
R
L
X
X
t
t
, t
, t
, t
V
PG1
V
DD
PLH PHL TLH THL
W
DD
DD
C
C ′
X
X
t
t
, t
, t
, t
V
V
SS
PG2
PLH PHL TLH THL
W
A
B
PULSE
GENERATOR
t
, t
, t
PG3
PG1
PG2
PLH(R) PHL(R)
W
Q
Q
C
L
RESET
A′
PULSE
GENERATOR
C
L
PG1 =
Q′
Q′
* Includes capacitance of probes,
wiring, and fixture parasitic.
C
L
B′
PG2 =
PG3 =
PULSE
GENERATOR
NOTE: AC test waveforms for
PG1, PG2, and PG3 on
next page.
C
L
RESET′
V
SS
Figure 4. AC Test Circuit
V
DD
90%
10%
50%
50%
V
SS
A
B
t
t
THL
TLH
t
WH
t
t
TLH
THL
V
DD
90%
10%
50%
V
SS
t
WL
t
t
THL
TLH
V
RESET
DD
90%
10%
50%
V
SS
t
t
THL
WL
PHL
t
W
t
rr
t
t
t
PLH
TLH
V
OH
90%
10%
50%
50%
50%
50%
Q
Q
V
OL
t
t
THL
TLH
t
t
t
PHL
PHL
PHL
V
OH
90%
10%
50%
50%
50%
50%
V
OL
Figure 5. AC Test Waveforms
1000
V
DD
= 15 V
15 V
10 V
5.0 V
10 V
5.0 V
100
10
R = 100 k
X
15 V
10 V
5.0 V
R = 10 k
X
R = 5.0 k
X
1.0
0.1
15 V
10 V
5.0 V
10
100
1000
10,000
100,000
C , EXTERNAL CAPACITANCE (pF)
X
Figure 6. Pulse Width versus CX
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6
MC14528B
TYPICAL APPLICATIONS
C
x
C
x
R
x
R
x
V
DD
V
DD
RISING EDGE
TRIGGER
RISING EDGE
TRIGGER
Q
Q
Q
Q
A
B
A
B
RESET
RESET
V
DD
V
DD
V
DD
C
x
R
x
C
x
R
x
V
DD
V
DD
Q
Q
A
B
Q
Q
A
B
FALLING EDGE
TRIGGER
FALLING EDGE
TRIGGER
RESET
RESET
V
DD
V
DD
Figure 7. Retriggerable
Monostables Circuitry
Figure 8. Non–Retriggerable
Monostables Circuitry
D
X
C
x
V
DD
NC
1, 15
2, 14
R
x
V
DD
NC
NC
Q
A
B
Q
Q
Q
RESET
RESET
V
DD
V
DD
V
DD
V
DD
Figure 9. Use of a Diode to Limit
Power Down Current Surge
Figure 10. Connection of Unused Sections
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7
MC14528B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
G
H
J
K
L
M
S
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
PLANE
–T–
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
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8
MC14528B
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
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9
MC14528B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE O
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
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10
MC14528B
Notes
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11
MC14528B
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
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attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment:
CENTRAL/SOUTH AMERICA:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
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001–800–4422–3781
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Email: ONlit–asia@hibbertco.com
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German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)
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Phone: 81–3–5740–2745
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Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)
Email: ONlit@hibbertco.com
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
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