MC14538BDWR2G [ONSEMI]
Dual Precision Retriggerable/Resettable Monostable Multivibrator; 双路精密可重触发/复式单稳态多谐振荡器
| 型号： | MC14538BDWR2G |
| 厂家： | 
ONSEMI |
| 描述： | Dual Precision Retriggerable/Resettable Monostable Multivibrator |
| 文件： | 总12页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14538B
Dual Precision
Retriggerable/Resettable
Monostable Multivibrator
The MC14538B is a dual, retriggerable, resettable monostable
multivibrator. It may be triggered from either edge of an input pulse,
and produces an accurate output pulse over a wide range of widths, the
duration and accuracy of which are determined by the external timing
components, C and R . Output Pulse Width T = R @ C (secs)
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MARKING
DIAGRAMS
X
X
X
X
R = W
X
16
1
PDIP−16
P SUFFIX
CASE 648
C = Farads
X
MC14538BCP
AWLYYWWG
Features
• Unlimited Rise and Fall Time Allowed on the A Trigger Input
• Pulse Width Range = 10 ms to 10 s
• Latched Trigger Inputs
• Separate Latched Reset Inputs
• 3.0 Vdc to 18 Vdc Operational Limits
• Triggerable from Positive (A Input) or Negative−Going Edge (B−Input)
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
16
SOIC−16
D SUFFIX
CASE 751B
14538BG
AWLYWW
1
16
SOIC−16
DW SUFFIX
CASE 751G
• Pin−for−pin Compatible with MC14528B and CD4528B (CD4098)
14538BG
AWLYYWW
• Use the MC54/74HC4538A for Pulse Widths Less Than 10 ms with
Supplies Up to 6 V
1
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
16
1
Symbol
Parameter
Value
−0.5 to +18.0
Unit
V
14
538B
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
V
DC Supply Voltage Range
DD
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
I , I
in out
Input or Output Current
(DC or Transient) per Pin
10
mA
16
P
T
Power Dissipation, per Package
(Note 1)
500
mW
D
SOEIAJ−16
F SUFFIX
CASE 966
MC14538B
ALYWG
Operating Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
A
1
T
stg
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
T
Lead Temperature
(8−Second Soldering)
L
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
WW, W = Work Week
G
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
to the range V v (V or V ) v V
.
DD
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
August, 2005 − Rev. 7
MC14538B/D
MC14538B
PIN ASSIGNMENT
BLOCK DIAGRAM
C
X
R
X
V
1
2
3
4
5
6
7
8
16
15
V
SS
DD
SS
V
DD
C /R A
X
V
X
1
2
RESET A
14 C /R B
X X
A
B
4
5
A
13 RESET B
A
Q1
Q1
RESET
6
7
B
12
11
10
9
A
B
A
B
B
Q
A
3
Q
Q
Q
A
B
B
V
SS
C
X
R
X
V
DD
15
14
A
B
12
11
Q2
Q2
10
9
ONE−SHOT SELECTION GUIDE
RESET
100 ns 1 ms 10 ms 100 ms 1 ms 10 ms 100 ms 1 s
MC14528B
10 s
13
MC14536B
MC14538B
MC14541B
MC4538A*
23 HR
5 MIN.
R AND C ARE EXTERNAL COMPONENTS.
X
X
ꢀꢀV = PIN 16
DD
ꢀꢀV = PIN 8, PIN 1, PIN 15
SS
*LIMITED OPERATING VOLTAGE (2 − 6 V)
TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
ORDERING INFORMATION
Device
†
Package
PDIP−16
PDIP−16
Shipping
MC14538BCP
500 Units / Rail
500 Units / Rail
MC14538BCPG
(Pb−Free)
MC14538BD
SOIC−16
48 Units / Rail
48 Units / Rail
MC14538BDG
SOIC−16
(Pb−Free)
MC14538BDR2
SOIC−16
2500 Units / Tape & Reel
2500 Units / Tape & Reel
MC14538BDR2G
SOIC−16
(Pb−Free)
MC14538BDW
SOIC−16 WB
SOIC−16 WB
47 Units / Rail
MC14538BDWR2
MC14538BDWR2G
1000 Units / Tape & Reel
1000 Units / Tape & Reel
SOIC−16 WB
(Pb−Free)
MC14538BDTR2
MC14538BF
TSSOP−16*
SOEIAJ−16
2500 Units / Tape & Reel
50 Units / Rail
MC14538BFG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC14538BFEL
SOEIAJ−16
2000 Units / Tape & Reel
2000 Units / Tape & Reel
MC14538BFELG
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC14538B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
125_C
V
DD
Characteristic
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
Vdc
(Note 2)
Output Voltage
“0” Level
“1” Level
“0” Level
V
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
OL
V
in
= V or 0
DD
V
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
OH
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
Vdc
IH
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
OH
OH
OH
OH
15
(V = 0.4 Vdc)
(V = 0.5 Vdc)
(V = 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
OL
OL
OL
Input Current, Pin 2 or 14
Input Current, Other Inputs
I
I
15
15
−
−
−
−
−
0.05
0.1
−
−
−
−
−
0.00001
0.00001
25
0.05
0.1
−
−
−
−
−
0.5
1.0
−
mAdc
mAdc
pF
in
in
Input Capacitance, Pin 2 or 14
C
in
in
Input Capacitance, Other Inputs
C
−
−
5.0
7.5
−
pF
(V = 0)
in
Quiescent Current
(Per Package)
I
I
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
mAdc
mAdc
DD
DD
Q = Low, Q = High
Quiescent Current, Active State
(Both) (Per Package)
5.0
10
15
−
−
−
2.0
2.0
2.0
−
−
−
0.04
0.08
0.13
0.20
0.45
0.70
−
−
−
2.0
2.0
2.0
Q = High, Q = Low
–2
–5
Total Supply Current at an external
load capacitance (C ) and at
external timing network (R , C )
I
5.0
10
I
I
I
= (3.5 x 10 ) R C f + 4C f + 1 x 10 C f
X X X L
= (8.0 x 10 ) R C f + 9C f + 2 x 10 C f
X X X L
= (1.25 x 10 ) R C f + 12C f + 3 x 10 C f
X X X L
T
T
T
T
–2
–5
L
–1
–5
X
X
(Note 3)
where: I in mA (one monostable switching only),
T
where: C in mF, C in pF, R in k ohms, and
X
L
X
where: f in Hz is the input frequency.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
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3
MC14538B
SWITCHING CHARACTERISTICS (Note 4) (C = 50 pF, T = 25_C)
L
A
All Types
V
Vdc
DD
Characteristic
Symbol
Unit
Min
Typ
(Note 5)
Max
Output Rise Time
t
t
ns
TLH
THL
t
t
t
= (1.35 ns/pF) C + 33 ns
= (0.60 ns/pF) C + 20 ns
= (0.40 ns/pF) C + 20 ns
5.0
10
15
−
−
−
100
50
40
200
100
80
TLH
TLH
TLH
L
L
L
Output Fall Time
ns
ns
t
t
t
= (1.35 ns/pF) C + 33 ns
= (0.60 ns/pF) C + 20 ns
= (0.40 ns/pF) C + 20 ns
5.0
10
15
−
−
−
100
50
40
200
100
80
THL
THL
THL
L
L
L
t
,
Propagation Delay Time
A or B to Q or Q
PLH
t
PHL
t
t
t
, t
= (0.90 ns/pF) C + 255 ns
= (0.36 ns/pF) C + 132 ns
L
= (0.26 ns/pF) C + 87 ns
L
5.0
10
15
−
−
−
300
150
100
600
300
220
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Reset to Q or Q
ns
t
t
t
, t
= (0.90 ns/pF) C + 205 ns
= (0.36 ns/pF) C + 107 ns
L
= (0.26 ns/pF) C + 82 ns
L
5.0
10
15
−
−
−
250
125
95
500
250
190
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
t , t
r
Input Rise and Fall Times
Reset
5
10
15
−
−
−
−
−
−
15
5
4
ms
ms
−
f
B Input
A Input
5
10
15
−
−
−
300
1.2
0.4
1.0
0.1
0.05
5
10
15
No Limit
Input Pulse Width
A, B, or Reset
t
t
,
5.0
10
15
170
90
80
85
45
40
−
−
−
ns
ns
ms
WH
WL
Retrigger Time
t
5.0
10
15
0
0
0
−
−
−
−
−
−
rr
T
Output Pulse Width — Q or Q
Refer to Figures 8 and 9
C
X
C
X
C
X
= 0.002 mF, R = 100 kW
5.0
10
15
198
200
202
210
212
214
230
232
234
X
= 0.1 mF, R = 100 kW
5.0
10
15
9.3
9.4
9.5
9.86
10
10.14
10.5
10.6
10.7
ms
s
X
= 10 mF, R = 100 kW
5.0
10
15
0.91
0.92
0.93
0.965
0.98
0.99
1.03
1.04
1.06
X
Pulse Width Match between circuits in
the same package.
100
[(T – T )/T ]
5.0
10
15
−
−
−
1.0
1.0
1.0
5.0
5.0
5.0
%
1
2
1
C
X
= 0.1 mF, R = 100 kW
X
4. The formulas given are for the typical characteristics only at 25_C.
5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
OPERATING CONDITIONS
External Timing Resistance
External Timing Capacitance
R
C
−
−
5.0
0
−
−
(Note 6)
kW
mF
X
No Limit
(Note 7)
X
6. The maximum usable resistance R is a function of the leakage of the capacitor C , leakage of the MC14538B, and leakage due to board
X
X
layout and surface resistance. Susceptibility to externally induced noise signals may occur for R > 1 MW..
X
7. If C > 15 mF, use discharge protection diode per Fig. 11.
X
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4
MC14538B
V
V
DD
DD
P1
R
X
2 (14)
ENABLE
+
+
C1
C2
−
V
ref1
−
R
Q
6ꢁ(10)
7ꢁꢁ(9)
V
ref2
C
X
ENABLE
OUTPUT
LATCH
(15)
1
S
Q
N1
V
SS
CONTROL
4 (12)
5 (11)
A
B
NOTE: Pins 1, 8 and 15 must
be externally grounded
Q
Q
R
R
3 (13)
RESET LATCH
RESET
S
R
Figure 1. Logic Diagram
(1/2 of DevIce Shown)
V
DD
0.1 mF
CERAMIC
500 pF
I
D
R
R ′
X
X
V
C
C ′
X
SS
X
V
SS
V
in
C /R
X
X
A
B
Q
20 ns
20 ns
C
L
RESET
A′
Q
V
DD
90%
10%
C
L
Q′
Q′
C
L
V
in
0 V
B′
C
L
RESET′
V
SS
Figure 2. Power Dissipation Test Circuit and Waveforms
V
DD
INPUT CONNECTIONS
R
R ′
X
Characteristics
Reset
A
B
X
*C = 50 pF
L
C
C ′
X
t
, t , t , t
,
,
V
PG1
V
DD
X
PLH PHL TLH THL
DD
V
V
SS
SS
T, t , t
WH WL
C /R
X
t
, t
, t
, t
V
V
PG2
X
PLH PHL TLH THL
DD
SS
A
B
PULSE
GENERATOR
T, t , t
WH WL
Q
Q
t
t
, t
,
PG3
PG1
PG2
PLH(R) PHL(R)
C
L
, t
WH WL
RESET
PULSE
GENERATOR
C
L
A′
Q′
*Includes capacitance of probes,
wiring, and fixture parasitic.
PG1 =
C
L
B′
Q′
PULSE
GENERATOR
NOTE: Switching test waveforms
PG2 =
PG3 =
C
L
for PG1, PG2, PG3 are shown
In Figure 4.
RESET′
V
SS
Figure 3. Switching Test Circuit
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5
MC14538B
90%
10%
50%
50%
V
V
V
DD
DD
DD
A
B
t
t
t
THL
TLH
WH
t
t
TLH
THL
90%
10%
50%
t
WL
t
t
PHL
THL
RESET
90%
10%
50%
t
WL
t
t
THL
t
PLH
TLH
T
t
t
t
t
rr
PLH
PHL
90%
10%
50%
50%
50%
50%
Q
Q
t
t
THL
TLH
t
t
PHL
PLH
PHL
90%
10%
50%
50%
50%
50%
Figure 4. Switching Test Waveforms
T = 25°C
R = 100 kW
X
A
0% POINT PULSE WIDTH
R = 100 kW
X
V
V
V
= 5.0 V, T = 9.8 ms
= 10 V, T = 10 ms
C = 0.1 mF
X
DD
DD
DD
C = 0.1 mF
X
1.0
0.8
0.6
0.4
0.2
0
2
= 15 V, T = 10.2 ms
1
0
1
2
−ꢂ4
−ꢂ2
0
2
4
5
6
7
8
9
10
11
12
13
14
15
T, OUTPUT PULSE WIDTH (%)
V
, SUPPLY VOLTAGE (VOLTS)
DD
Figure 5. Typical Normalized Distribution
of Units for Output Pulse Width
Figure 6. Typical Pulse Width Variation as
a Function of Supply Voltage VDD
1000
FUNCTION TABLE
Inputs
A
Outputs
R = 100 kW, C = 50 pF
X
L
ONE MONOSTABLE SWITCHING ONLY
Reset
B
Q
Q
100
10
H
H
H
L
V
= 15 V
DD
H
H
L
Not Triggered
Not Triggered
5.0 V
H
10 V
H
H
L, H,
L
H
L, H,
Not Triggered
Not Triggered
1.0
0.1
L
X
X
X
X
L
H
Not Triggered
0.001
0.1
1.0
OUTPUT DUTY CYCLE (%)
10
100
Figure 7. Typical Total Supply Current
versus Output Duty Cycle
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6
−
−
60
40 −ꢂ20
0
20
40
60
80 100 120 140
−ꢂ60 −ꢂ40 −ꢂ20
0
20
40
60
80 100 120 140
−
−
−ꢂ1.0
−ꢂ2.0
−ꢂ3.0
MC14538B
R = 100 kW
X
C = .002 mF
X
R = 100 kW
X
3.0
C = 0.1 mF
X
V
V
= 15 V
DD
DD
2
1
0
1
2
2.0
1.0
V
V
= 15 V
= 10 V
DD
DD
= 10 V
= 5 V
0
V
DD
V
= 5.0 V
DD
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 8. Typical Error of Pulse Width
Equation versus Temperature
Figure 9. Typical Error of Pulse Width
Equation versus Temperature
THEORY OF OPERATION
1
3
4
A
2
B
5
RESET
V
refꢃ2
V
refꢃ2
V
refꢃ2
V
refꢃ2
C /R
X
X
V
refꢃ1
V
refꢃ1
V
refꢃ1
V
refꢃ1
Q
T
T
T
1
4
5
Positive edge trigger
Positive edge re−trigger (pulse lengthening)
Positive edge re−trigger (pulse lengthening)
2
3
Negative edge trigger
Positive edge trigger
Figure 10. Timing Operation
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7
MC14538B
TRIGGER OPERATION
The block diagram of the MC14538B is shown in
Figure 1, with circuit operation following.
on Reset sets the reset latch and causes the capacitor to be
fast charged to V by turning on transistor P1 ➀. When the
DD
voltage on the capacitor reaches V , the reset latch will
ref 2
As shown in Figure 1 and 10, before an input trigger
occurs, the monostable is in the quiescent state with the Q
clear, and will then be ready to accept another pulse. It the
Reset input is held low, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will not
change. Since the Q output is reset when an input low level
is detected on the Reset input, the output pulse T can be made
significantly shorter than the minimum pulse width
specification.
output low, and the timing capacitor C completely charged
X
to V . When the trigger input A goes from V to V
DD
SS
DD
(while inputs B and Reset are held to V ) a valid trigger is
DD
recognized, which turns on comparator C1 and N−channel
transistor N1➀. At the same time the output latch is set. With
transistor N1 on, the capacitor C rapidly discharges toward
X
POWER−DOWN CONSIDERATIONS
V
until V
is reached. At this point the output of
SS
ref1
Large capacitance values can cause problems due to the
large amount of energy stored. When a system containing
the MC14538B is powered down, the capacitor voltage may
comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time
comparator C2 turns on. With transistor N1 off, the capacitor
discharge from V through the standard protection diodes
DD
C begins to charge through the timing resistor, R , toward
X
X
at pin 2 or 14. Current through the protection diodes should
be limited to 10 mA and therefore the discharge time of the
V
. When the voltage across C equals V , comparator
DD
X ref 2
C2 changes state, causing the output latch to reset (Q goes
low) while at the same time disabling comparator C2 ➀. This
ends at the timing cycle with the monostable in the quiescent
state, waiting for the next trigger.
V
supply must not be faster than (V ). (C)/(10 mA).
DD
DD
For example, if V = 10 V and C = 10 mF, the V supply
DD
X
DD
should discharge no faster than (10 V) x (10 mF)/(10 mA)
= 10 ms. This is normally not a problem since power
supplies are heavily filtered and cannot discharge at this rate.
In the quiescent state, C is fully charged to V causing
X
DD
the current through resistor R to be zero. Both comparators
X
When a more rapid decrease of V to zero volts occurs,
DD
are “off” with total device current due only to reverse
junction leakages. An added feature of the MC14538B is
that the output latch is set via the input trigger without regard
to the capacitor voltage. Thus, propagation delay from
the MC14538B can sustain damage. To avoid this possibility
use an external clamping diode, D , connected as shown in
X
Fig. 11.
trigger to Q is independent of the value of C , R , or the duty
cycle of the input waveform.
X
X
D
x
C
V
V
x
RETRIGGER OPERATION
DD
DD
R
x
V
SS
The MC14538B is retriggered if a valid trigger occurs ➀
followed by another valid trigger ➀ before the Q output has
returned to the quiescent (zero) state. Any retrigger, after the
timing node voltage at pin 2 or 14 has begun to rise from
Q
Q
V
ref 1
, but has not yet reached V
, will cause an increase
ref 2
in output pulse width T. When a valid retrigger is initiated
➀, the voltage at C /R will again drop to V before
RESET
X
X
ref 1
progressing along the RC charging curve toward V . The
DD
Q output will remain high until time T, after the last valid
retrigger.
Figure 11. Use of a Diode to Limit
Power Down Current Surge
RESET OPERATION
The MC14538B may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
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8
MC14538B
TYPICAL APPLICATIONS
C
X
R
C
X
X
R
X
RISING−EDGE
TRIGGER
V
DD
V
DD
Q
RISING−EDGE
TRIGGER
A
B
Q
A
B
Q
Q
B = V
DD
RESET = V
DD
RESET = V
DD
C
X
C
R
X
X
R
X
V
A = V
V
DD
DD
SS
Q
Q
Q
A
B
B
Q
FALLING−EDGE
TRIGGER
FALLING−EDGE
TRIGGER
RESET = V
RESET = V
DD
DD
Figure 12. Retriggerable
Monostables Circuitry
Figure 13. Non−Retriggerable
Monostables Circuitry
NC
Q
Q
NC
NC
A
B
C
D
V
DD
V
DD
Figure 14. Connection of Unused Sections
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9
MC14538B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
J
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
G
0.21
0.38
3.30
7.74
10
D 16 PL
2.80
7.50
0
M
M
0.25 (0.010)
T A
M
S
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
_
_
_
_
M
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
0.25 (0.010)
T B
A
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10
MC14538B
PACKAGE DIMENSIONS
SOIC−16 WB
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G−03
ISSUE C
NOTES:
A
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
q
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
16
9
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
2.35
A1 0.10
MAX
2.65
0.25
0.49
0.32
1
8
A
B
C
D
E
e
H
h
L
q
0.35
0.23
10.15 10.45
7.40 7.60
1.27 BSC
10.05 10.55
B
16X B
M
S
S
B
0.25
T A
0.25
0.50
0
0.75
0.90
7
_
_
SEATING
PLANE
14X
e
C
T
TSSOP−16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F−01
ISSUE A
NOTES:
16X KREF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
M
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
D
F
0.15 0.002 0.006
0.75 0.020 0.030
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
D
G
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11
MC14538B
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966−01
ISSUE O
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
16
9
E
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
Q
1
H
E
E
M
_
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
2.05
0.20
0.50
0.27
10.50
5.45
A
−−−
0.05
0.35
0.18
9.90
5.10
A
A
1
0.002
0.008
0.020
0.011
0.413
0.215
1
b
0.13 (0.005)
b
c
0.014
0.007
0.390
0.201
0.10 (0.004)
M
D
E
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
0
10
10
0.035
M
Q
0
0.028
_
_
_
_
0.70
−−−
0.90
0.78
1
Z
−−− 0.031
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