MC14538BFEL_技术文档

The MC14538B is a dual, retriggerable, resettable monostable

multivibrator. It may be triggered from either edge of an input pulse,

and produces an accurate output pulse over a wide range of widths, the

duration and accuracy of which are determined by the external timing

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MARKING

DIAGRAMS

components, C and R .

X

16

PDIP–16

P SUFFIX

CASE 648

Output Pulse Width = (Cx) (Rx) where:

Rx is in k

Cx is in F

MC14538BCP

AWLYYWW

1

16

• Unlimited Rise and Fall Time Allowed on the A Trigger Input

• Pulse Width Range = 10 µs to 10 s

• Latched Trigger Inputs

SOIC–16

D SUFFIX

CASE 751B

14538B

AWLYWW

1

16

• Separate Latched Reset Inputs

• 3.0 Vdc to 18 Vdc Operational Limits

• Triggerable from Positive (A Input) or Negative–Going Edge

(B–Input)

TSSOP–16

DT SUFFIX

CASE 948F

14

538B

ALYW

1

16

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Pin–for–pin Compatible with MC14528B and CD4528B (CD4098)

14538B

SOIC–16

DW SUFFIX

CASE 751G

AWLYYWW

• Use the MC54/74HC4538A for Pulse Widths Less Than 10 µs with

1

Supplies Up to 6 V.

16

SOEIAJ–16

F SUFFIX

CASE 966

MC14538B

AWLYWW

MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)

SS

Symbol

Parameter

Value

Unit

V

1

A

= Assembly Location

V

DD

DC Supply Voltage Range

–0.5 to +18.0

WL or L = Wafer Lot

YY or Y = Year

WW or W = Work Week

V , V

in out

Input or Output Voltage Range

(DC or Transient)

–0.5 to V + 0.5

V

DD

I , I

in out

Input or Output Current

(DC or Transient) per Pin

±10

mA

ORDERING INFORMATION

Device

Package

PDIP–16

SOIC–16

Shipping

P

Power Dissipation,

per Package (Note 3.)

500

mW

D

MC14538BCP

MC14538BD

2000/Box

48/Rail

T

A

Operating Temperature Range

Storage Temperature Range

–55 to +125

–65 to +150

260

°C

T

stg

MC14538BDR2

MC14538BDT

SOIC–16 2500/Tape & Reel

TSSOP–16 96/Rail

T

Lead Temperature

(8–Second Soldering)

L

2. Maximum Ratings are those values beyond which damage to the device

may occur.

MC14538BDTR2 TSSOP–16 2500/Tape & Reel

3. Temperature Derating:

MC14538BDW

SOIC–16

47/Rail

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

MC14538BDWR2

MC14538BF

SOIC–16 1000/Tape & Reel

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

SOEIAJ–16

See Note 1.

MC14538BFEL

high–impedancecircuit. For proper operation, V and V should be constrained

in

out

to the range V

(V or V

)

V

.

SS

in

out

DD

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local

ON Semiconductor representative.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either V or V ). Unused outputs must be left open.

SS

DD

Semiconductor Components Industries, LLC, 2000

1

Publication Order Number:

March, 2000 – Rev. 3

MC14538B/D

MC14538B

PIN ASSIGNMENT

V

1

2

3

4

5

6

7

8

16

15

V

DD

SS

C /R A

V

SS

X

RESET A

14 C /R B

X X

A

13 RESET B

A

B

12

11

10

9

A

B

A

Q

B

A

Q

B

A

V

SS

Q

B

BLOCK DIAGRAM

C

X

R

X

V

DD

1

2

A

B

4

5

Q1

RESET

6

7

3

C

X

R

X

V

DD

15

14

A

B

12

11

Q2

10

9

RESET

13

R AND C ARE EXTERNAL COMPONENTS.

X

V

DD

= PIN 16

V

SS

= PIN 8, PIN 1, PIN 15

ONE–SHOT SELECTION GUIDE

100 ns 1 µs 10 µs 100 µs 1 ms 10 ms 100 ms 1 s

MC14528B

10 s

MC14536B

MC14538B

MC14541B

MC4538A*

23 HR

5 MIN.

*LIMITED OPERATING VOLTAGE (2 – 6 V)

TOTAL OUTPUT PULSE WIDTH RANGE

RECOMMENDED PULSE WIDTH RANGE

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2

MC14538B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

SS

– 55 C

25 C

125 C

V

DD

(4.)

Vdc

Characteristic

Output Voltage

Symbol

Unit

Min

Max

Min

Typ

Max

Min

Max

“0” Level

“1” Level

“0” Level

V

OL

5.0

10

15

—

0.05

—

0

0.05

—

0.05

Vdc

V

in

= V or 0

DD

V

OH

5.0

10

15

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

10

15

—

4.95

9.95

14.95

—

Vdc

V

in

= 0 or V

DD

Input Voltage

(V = 4.5 or 0.5 Vdc)

V

IL

5.0

10

15

—

1.5

3.0

4.0

—

2.25

4.50

6.75

1.5

3.0

4.0

—

1.5

3.0

4.0

O

(V = 9.0 or 1.0 Vdc)

O

(V = 13.5 or 1.5 Vdc)

O

“1” Level

V

IH

Vdc

(V = 0.5 or 4.5 Vdc)

5.0

10

15

3.5

7.0

11

—

3.5

7.0

11

2.75

5.50

8.25

—

3.5

7.0

11

—

O

(V = 1.0 or 9.0 Vdc)

O

(V = 1.5 or 13.5 Vdc)

O

Output Drive Current

I

mAdc

OH

(V = 2.5 Vdc)

Source

Sink

5.0

10

– 3.0

– 0.64

– 1.6

– 4.2

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

– 1.7

– 0.36

– 0.9

– 2.4

—

OH

(V = 4.6 Vdc)

OH

(V = 9.5 Vdc)

OH

(V = 13.5 Vdc)

OH

15

(V = 0.4 Vdc)

I

OL

5.0

10

15

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

OL

(V = 0.5 Vdc)

OL

(V = 1.5 Vdc)

OL

Input Current, Pin 2 or 14

Input Current, Other Inputs

I

15

—

±0.05

±0.1

—

±0.00001 ±0.05

—

±0.5

±1.0

—

µAdc

pF

in

±0.00001

25

±0.1

—

in

Input Capacitance, Pin 2 or 14

Input Capacitance, Other Inputs

C

in

—

5.0

7.5

—

pF

(V = 0)

in

Quiescent Current

(Per Package)

I

5.0

10

15

—

5.0

10

20

—

0.005

0.010

0.015

5.0

10

20

—

150

300

600

µAdc

mAdc

µAdc

DD

Q = Low, Q = High

Quiescent Current, Active State

(Both) (Per Package)

I

5.0

10

15

—

2.0

—

0.04

0.08

0.13

0.20

0.45

0.70

—

2.0

Q = High, Q = Low

–2

–5

Total Supply Current at an external

load capacitance (C ) and at

external timing network (R , C )

I

T

5.0

10

I = (3.5 x 10 ) R C f + 4C f + 1 x 10 C f

T X X X L

I = (8.0 x 10 ) R C f + 9C f + 2 x 10 C f

T X X X L

I = (1.25 x 10 ) R C f + 12C f + 3 x 10 C f

T X X X L

–2

–5

L

(5.)

–1

–5

X

where: I in µA (one monostable switching only),

T

where: C in µF, C in pF, R in k ohms, and

X

L

X

where: f in Hz is the input frequency.

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25 C.

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3

MC14538B

SWITCHING CHARACTERISTICS ^(6.)(C = 50 pF, T = 25 C)

L

A

All Types

V

Vdc

DD

(7.)

Characteristic

Symbol

Unit

Min

Typ

Max

Output Rise Time

t

ns

TLH

THL

t

= (1.35 ns/pF) C + 33 ns

= (0.60 ns/pF) C + 20 ns

= (0.40 ns/pF) C + 20 ns

5.0

10

15

—

100

50

40

200

100

80

TLH

L

Output Fall Time

t

ns

t

= (1.35 ns/pF) C + 33 ns

= (0.60 ns/pF) C + 20 ns

= (0.40 ns/pF) C + 20 ns

5.0

10

15

—

100

50

40

200

100

80

THL

L

Propagation Delay Time

A or B to Q or Q

t

,

PLH

t

PHL

t

, t

= (0.90 ns/pF) C + 255 ns

= (0.36 ns/pF) C + 132 ns

L

= (0.26 ns/pF) C + 87 ns

L

5.0

10

15

—

300

150

100

600

300

220

PLH PHL

L

, t

PLH PHL

, t

PLH PHL

Reset to Q or Q

ns

t

, t

= (0.90 ns/pF) C + 205 ns

= (0.36 ns/pF) C + 107 ns

L

= (0.26 ns/pF) C + 82 ns

L

5.0

10

15

—

250

125

95

500

250

190

PLH PHL

L

, t

PLH PHL

, t

PLH PHL

Input Rise and Fall Times

Reset

t , t

r

5

10

15

—

15

5

4

µs

ms

—

f

B Input

A Input

5

10

15

—

300

1.2

0.4

1.0

0.1

0.05

5

10

15

No Limit

Input Pulse Width

A, B, or Reset

t

,

5.0

10

15

170

90

80

85

45

40

—

ns

µs

WH

WL

Retrigger Time

t

rr

5.0

10

15

0

—

Output Pulse Width — Q or Q

Refer to Figures 8 and 9

T

C

= 0.002 µF, R = 100 kΩ

5.0

10

15

198

200

202

210

212

214

230

232

234

X

= 0.1 µF, R = 100 kΩ

5.0

10

15

9.3

9.4

9.5

9.86

10

10.14

10.5

10.6

10.7

ms

s

X

= 10 µF, R = 100 kΩ

5.0

10

15

0.91

0.92

0.93

0.965

0.98

0.99

1.03

1.04

1.06

X

Pulse Width Match between circuits in

the same package.

100

[(T – T )/T ]

5.0

10

15

—

± 1.0

± 5.0

%

1

2

1

C

= 0.1 µF, R = 100 kΩ

X

6. The formulas given are for the typical characteristics only at 25 C.

7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

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4

MC14538B

OPERATING CONDITIONS

External Timing Resistance

External Timing Capacitance

(8.)

R

C

—

5.0

0

—

kΩ

µF

X

No

(9.)

Limit

8. The maximum usable resistance R is a function of the leakage of the capacitor C , leakage of the MC14538B, and leakage due to board

X

layout and surface resistance. Susceptibility to externally induced noise signals may occur for R > 1 MΩ..

X

9. If C > 15 µF, use discharge protection diode per Fig. 11.

X

V

DD

V

DD

P1

R

X

2 (14)

ENABLE

C2

+

C1

–

V

ref1

–

R

Q

6 (10)

(9)

V

ref2

C

X

ENABLE

OUTPUT

LATCH

(15)

1

S

Q

7

N1

V

SS

CONTROL

4 (12)

5 (11)

A

B

NOTE: Pins 1, 8 and 15 must

be externally grounded

Q

R

3 (13)

RESET LATCH

RESET

S

R

Figure 1. Logic Diagram

(1/2 of DevIce Shown)

V

DD

0.1 µF

CERAMIC

500 pF

I

D

R

X

R ′

X

V

SS

C

X

C ′

X

V

SS

V

in

C /R

X

A

B

Q

20 ns

C

L

RESET

A′

Q

V

DD

90%

10%

C

L

Q′

C

L

V

in

0 V

B′

C

L

RESET′

V

SS

Figure 2. Power Dissipation Test Circuit and Waveforms

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5

MC14538B

V

DD

INPUT CONNECTIONS

R

X

R ′

X

Characteristics

Reset

A

B

* C = 50 pF

L

C

X

C ′

X

t

, t

,

V

DD

PG1

V

DD

PLH PHL TLH THL

V

SS

V

SS

T, t , t

WH WL

C /R

t

, t

,

V

PG2

X

PLH PHL TLH THL

DD

SS

A

B

PULSE

GENERATOR

T, t , t

WH WL

Q

t

, t

,

PG3

PG1

PG2

PLH(R) PHL(R)

C

L

, t

WH WL

RESET

PULSE

GENERATOR

C

L

A′

Q′

* Includes capacitance of probes,

wiring, and fixture parasitic.

PG1 =

C

L

B′

Q′

PULSE

GENERATOR

PG2 =

PG3 =

NOTE: Switching test waveforms

C

L

RESET′

for PG1, PG2, PG3 are shown

In Figure 4.

V

SS

Figure 3. Switching Test Circuit

90%

10%

50%

V

DD

A

B

t

THL

TLH

WH

t

TLH

THL

90%

10%

V

DD

50%

t

WL

t

THL

PHL

RESET

90%

10%

V

DD

50%

t

WL

t

THL

t

PLH

TLH

T

t

rr

t

PLH

PHL

90%

10%

50%

t

50%

Q

t

THL

TLH

t

PLH

PHL

90%

10%

50%

Figure 4. Switching Test Waveforms

T = 25°C

R = 100 kΩ

X

A

0% POINT PULSE WIDTH

R = 100 kΩ

C = 0.1 µF

X

V

= 5.0 V, T = 9.8 ms

= 10 V, T = 10 ms

= 15 V, T = 10.2 ms

C = 0.1 µF

X

DD

V

1.0

0.8

0.6

0.4

0.2

0

DD

2

1

0

1

2

V

DD

–4 –2

0

2

4

5

6

7

8

9

10

V , SUPPLY VOLTAGE (VOLTS)

DD

11

12

13

14

15

T, OUTPUT PULSE WIDTH (%)

Figure 5. Typical Normalized Distribution

of Units for Output Pulse Width

Figure 6. Typical Pulse Width Variation as

a Function of Supply Voltage V_DD

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6

MC14538B

1000

100

10

FUNCTION TABLE

Inputs

Outputs

R = 100 kΩ, C = 50 pF

ONE MONOSTABLE SWITCHING ONLY

X

L

Reset

A

B

Q

H

L

V

DD

= 15 V

H

L

Not Triggered

5.0 V

H

10 V

H

L, H,

L

H

L, H,

Not Triggered

1.0

0.1

L

X

L

H

Not Triggered

0.001

0.1

1.0

OUTPUT DUTY CYCLE (%)

10

100

Figure 7. Typical Total Supply Current

versus Output Duty Cycle

R = 100 kΩ

X

C = .002 µF

X

R = 100 kΩ

C = 0.1 µF

X

3.0

V

= 15 V

= 10 V

DD

2

1

2.0

1.0

V

= 15 V

= 10 V

DD

V

DD

0

V

DD

V

= 5 V

DD

–1

–2

–1.0

–2.0

–3.0

V

DD

= 5.0 V

–60 –40 –20

0

20

40

60

80 100 120 140

–60 –40 –20

0

20

40

60

80 100 120 140

T , AMBIENT TEMPERATURE (°C)

A

T , AMBIENT TEMPERATURE (°C)

A

Figure 8. Typical Error of Pulse Width

Equation versus Temperature

Figure 9. Typical Error of Pulse Width

Equation versus Temperature

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7

MC14538B

THEORY OF OPERATION

1

3

4

A

B

2

5

RESET

V

ref 2

V

ref 2

V

ref 2

V

ref 2

C /R

X

V

ref 1

V

ref 1

V

ref 1

V

ref 1

Q

T

1

4

5

Positive edge trigger

Positive edge re–trigger (pulse lengthening)

2

3

Negative edge trigger

Positive edge trigger

Figure 10. Timing Operation

TRIGGER OPERATION

RETRIGGER OPERATION

The block diagram of the MC14538B is shown in

Figure 1, with circuit operation following.

As shown in Figure 1 and 10, before an input trigger

occurs, the monostable is in the quiescent state with the Q

The MC14538B is retriggered if a valid trigger occurs

followed by another valid trigger before the Q output has

returned to the quiescent (zero) state. Any retrigger, after the

timing node voltage at pin 2 or 14 has begun to rise from

output low, and the timing capacitor C completely charged

V

ref 1

, but has not yet reached V

, will cause an increase

X

ref 2

to V . When the trigger input A goes from V to V

in output pulse width T. When a valid retrigger is initiated

, the voltage at C /R will again drop to V before

DD

SS

DD

(while inputs B and Reset are held to V ) a valid trigger is

DD

X

ref 1

recognized, which turns on comparator C1 and N–channel

transistorN1 . Atthesametimetheoutputlatchisset. With

progressing along the RC charging curve toward V . The

Q output will remain high until time T, after the last valid

retrigger.

DD

transistor N1 on, the capacitor C rapidly discharges toward

X

V

until V

is reached. At this point the output of

SS

ref1

RESET OPERATION

comparator C1 changes state and transistor N1 turns off.

Comparator C1 then turns off while at the same time

comparatorC2turnson. WithtransistorN1off, thecapacitor

C begins to charge through the timing resistor, R , toward

X

V

The MC14538B may be reset during the generation of the

output pulse. In the reset mode of operation, an input pulse

on Reset sets the reset latch and causes the capacitor to be

X

. When the voltage across C equals V , comparator

DD

X ref 2

fast charged to V by turning on transistor P1 . When the

DD

C2 changes state, causing the output latch to reset (Q goes

low)whileatthesametimedisablingcomparatorC2 . This

ends at the timing cycle with the monostable in the quiescent

state, waiting for the next trigger.

voltage on the capacitor reaches V , the reset latch will

ref 2

clear, and will then be ready to accept another pulse. It the

Reset input is held low, any trigger inputs that occur will be

inhibited and the Q and Q outputs of the output latch will not

change. Since the Q output is reset when an input low level

isdetectedontheResetinput, theoutputpulseTcanbemade

significantly shorter than the minimum pulse width

specification.

In the quiescent state, C is fully charged to V causing

X

DD

the current through resistor R to be zero. Both comparators

X

are “off” with total device current due only to reverse

junction leakages. An added feature of the MC14538B is

that the output latch is set via the input trigger without regard

to the capacitor voltage. Thus, propagation delay from

triggertoQisindependentofthevalueofC , R , ortheduty

X

cycle of the input waveform.

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8

MC14538B

D

x

POWER–DOWN CONSIDERATIONS

Large capacitance values can cause problems due to the

large amount of energy stored. When a system containing

the MC14538B is powered down, the capacitor voltage may

C

x

V

DD

R

x

V

SS

V

DD

discharge from V through the standard protection diodes

DD

at pin 2 or 14. Current through the protection diodes should

be limited to 10 mA and therefore the discharge time of the

Q

V

supply must not be faster than (V ). (C)/(10 mA).

DD

For example, if V = 10 V and C = 10 µF, the V supply

DD

X

DD

RESET

should discharge no faster than (10 V) x (10 µF)/(10 mA)

= 10 ms. This is normally not a problem since power

suppliesareheavilyfilteredandcannotdischargeatthisrate.

Figure 11. Use of a Diode to Limit

Power Down Current Surge

When a more rapid decrease of V to zero volts occurs,

DD

theMC14538Bcansustaindamage. Toavoidthispossibility

use an external clamping diode, D , connected as shown in

X

Fig. 11.

TYPICAL APPLICATIONS

C

X

R

X

C

X

R

X

RISING–EDGE

TRIGGER

V

DD

V

DD

Q

RISING–EDGE

A

B

Q

TRIGGER

Q

B

Q

B = V

DD

RESET = V

DD

RESET = V

DD

C

X

C

X

R

X

R

X

V

DD

A = V

V

DD

SS

Q

A

B

Q

FALLING–EDGE

TRIGGER

FALLING–EDGE

TRIGGER

RESET = V

DD

Figure 12. Retriggerable

Monostables Circuitry

Figure 13. Non–Retriggerable

Monostables Circuitry

NC

Q

NC

A

B

C

D

V

DD

V

DD

Figure 14. Connection of Unused Sections

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9

MC14538B

PACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

–A–

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

16

1

9

8

B

S

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

INCHES

DIM MIN MAX

0.740 0.770 18.80 19.55

MILLIMETERS

MIN MAX

F

A

B

C

D

F

G

H

J

K

L

M

S

C

L

0.250 0.270

0.145 0.175

0.015 0.021

6.35

3.69

0.39

1.02

6.85

4.44

0.53

1.77

0.040

0.70

SEATING

PLANE

–T–

0.100 BSC

0.050 BSC

0.008 0.015

2.54 BSC

1.27 BSC

K

M

0.21

0.38

3.30

7.74

10

H

J

0.110

0.295 0.305

10

0.020 0.040

0.130

2.80

7.50

0

G

D 16 PL

0

0.51

1.01

M

0.25 (0.010)

T A

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

–A–

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

16

1

9

–B–

P 8 PL

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

M

S

0.25 (0.010)

B

8

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

G

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MAX

0.393

0.157

0.068

0.019

0.049

F

A

B

C

D

F

9.80

3.80

1.35

0.35

0.40

10.00 0.386

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

R X 45

K

C

G

J

K

M

P

1.27 BSC

0.050 BSC

–T–

SEATING

PLANE

0.19

0.10

0

0.25 0.008

0.25 0.004

0.009

7

J

M

D

16 PL

7

0

5.80

0.25

6.20 0.229

0.50 0.010

0.244

0.019

M

S

0.25 (0.010)

T B

A

R

http://onsemi.com

10

MC14538B

PACKAGE DIMENSIONS

SOIC–16

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751G–03

ISSUE B

A

D

16

9

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS

OF THE B DIMENSION AT MAXIMUM MATERIAL

CONDITION.

1

8

MILLIMETERS

B

16X B

DIM MIN

MAX

2.65

0.25

0.49

0.32

10.45

7.60

A

A1

B

C

D

E

2.35

0.10

0.35

0.23

10.15

7.40

M

S

0.25

T A

B

e

1.27 BSC

H

h

L

10.05

0.25

0.50

0

10.55

0.75

0.90

7

SEATING

PLANE

14X

e

C

T

TSSOP–16

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

16X KREF

M

S

0.10 (0.004)

T U

V

S

0.15 (0.006) T U

K

K1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

16

9

2X L/2

J1

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS. MOLD

FLASH OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

B

–U–

SECTION N–N

L

J

PIN 1

IDENT.

8

1

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

N

0.25 (0.010)

S

0.15 (0.006) T U

A

M

–V–

N

F

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

A

B

C

4.90

4.30

–––

5.10 0.193 0.200

4.50 0.169 0.177

DETAIL E

1.20

––– 0.047

D

F

G

H

J

J1

K

K1

L

0.05

0.50

0.65 BSC

0.18

0.09

0.19

0.15 0.002 0.006

0.75 0.020 0.030

0.026 BSC

0.28 0.007 0.011

0.20 0.004 0.008

0.16 0.004 0.006

0.30 0.007 0.012

0.25 0.007 0.010

–W–

C

0.10 (0.004)

DETAIL E

H

SEATING

PLANE

–T–

D

G

6.40 BSC

0.252 BSC

M

0

8

0

8

http://onsemi.com

11

MC14538B

PACKAGE DIMENSIONS

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

ISSUE O

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

L

E

16

9

8

Q

1

H

E

M

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

E

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

1

L

DETAIL P

Z

D

VIEW P

e

MILLIMETERS

INCHES

A

DIM MIN

MAX

MIN

–––

MAX

0.081

0.008

0.020

0.011

0.413

0.215

c

A

1

–––

0.05

0.35

0.18

9.90

5.10

2.05

A

0.20 0.002

0.50 0.014

0.27 0.007

10.50 0.390

5.45 0.201

b

c

D

E

A

1

b

0.13 (0.005)

e

1.27 BSC

0.050 BSC

0.10 (0.004)

M

H

7.40

0.50

1.10

0

0.70

–––

8.20 0.291

0.85 0.020

1.50 0.043

10

0.90 0.028

0.78 –––

0.323

0.033

0.059

10

0.035

0.031

E

L

E

M

Q

0

1

Z

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold

SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment:

CENTRAL/SOUTH AMERICA:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–spanish@hibbertco.com

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada

Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support

Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

Toll Free from Hong Kong & Singapore:

Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada

001–800–4422–3781

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

Email: ONlit–asia@hibbertco.com

EUROPE: LDC for ON Semiconductor – European Support

German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)

Email: ONlit–german@hibbertco.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549

Phone: 81–3–5740–2745

French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)

Email: ONlit–french@hibbertco.com

English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)

Email: ONlit@hibbertco.com

Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

For additional information, please contact your local

Sales Representative.

*Available from Germany, France, Italy, England, Ireland

MC14538B/D

http://onsemi.com

12


型号：	MC14538BFEL
厂家：	ONSEMI
描述：	Dual Precision Retiggerable/Resettable Monostable Multivibrator 双精度Retiggerable /复式单稳多谐振荡器振荡器逻辑集成电路光电二极管时钟
文件：	总12页 (文件大小：289K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC14538BFEL [ONSEMI]

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