MC14555 [ONSEMI]
Dual Binary to 1-of-4 Decoder/Demultiplexer; 到1 -的-4双二进制解码器/多路解复用器
| 型号： | MC14555 |
| 厂家： | 
ONSEMI |
| 描述： | Dual Binary to 1-of-4 Decoder/Demultiplexer |
| 文件： | 总8页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,
Q3). The MC14555B has the selected output go to the “high” state,
and the MC14556B has the selected output go to the “low” state.
Expanded decoding such as binary–to–hexadecimal (1–of–16), etc.,
can be achieved by using other MC14555B or MC14556B devices.
Applications include code conversion, address decoding, memory
selection control, and demultiplexing (using the Enable input as a data
input) in digital data transmission systems.
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC1455XBCP
AWLYYWW
1
• Diode Protection on All Inputs
16
• Active High or Active Low Outputs
• Expandable
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
SOIC–16
D SUFFIX
CASE 751B
1455XB
AWLYWW
1
16
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
SOEIAJ–16
F SUFFIX
CASE 966
MC1455XB
AWLYWW
1
X
A
= Specific Device Code
= Assembly Location
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
Symbol
Parameter
Value
Unit
V
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
ORDERING INFORMATION
I , I
Input or Output Current
(DC or Transient) per Pin
±10
mA
in out
Device
Package
PDIP–16
SOIC–16
Shipping
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
MC14555BCP
MC14555BD
2000/Box
48/Rail
T
A
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
T
stg
MC14555BDR2
SOIC–16 2500/Tape & Reel
T
L
Lead Temperature
(8–Second Soldering)
MC14555BF
SOEIAJ–16
SOEIAJ–16
PDIP–16
See Note 1.
See Note 1.
2000/Box
48/Rail
MC14555BFEL
MC14556BCP
MC14556BD
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
SOIC–16
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14556BDR2
SOIC–16 2500/Tape & Reel
MC14556BF
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
MC14556BFEL
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14555B/D
MC14555B, MC14556B
PIN ASSIGNMENTS
MC14555B
MC14556B
E
1
2
3
4
5
6
7
8
16
15
14
13
V
E
1
2
3
4
5
6
7
8
16
15
14
13
V
DD
A
DD
A
A
A
A
A
E
B
E
B
B
A
A
B
B
A
A
B
Q0
A
Q0
A
B
B
B
B
Q1
A
12 Q0
Q1
A
12 Q0
B
B
Q2
A
Q2
A
11 Q1
11 Q1
B
B
Q3
A
10 Q2
Q3
A
10 Q2
B
B
V
SS
9
Q3
V
SS
9
Q3
B
B
TRUTH TABLE
Inputs
Outputs
Enable Select
MC14555B
MC14556B
E
B
A
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
X
X
0
0
0
0
1
1
1
1
X = Don’t Care
BLOCK DIAGRAM
MC14555B
MC14556B
Q0
A
4
5
6
Q0
4
5
6
7
2
3
1
2
3
1
A
B
E
Q1
Q1
Q2
Q3
B
Q2
E
Q3
7
Q0
A
12
14
12
11
10
9
Q0
Q1
Q2
Q3
14
13
15
A
B
E
Q1
11
B
13
15
Q2
10
E
Q3
9
V
V
= PIN 16
= PIN 8
DD
SS
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2
MC14555B, MC14556B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(4.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
±0.1
—
—
±0.00001
±0.1
—
—
±1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (0.85 µA/kHz) f + I
T
I = (1.70 µA/kHz) f + I
T
I = (2.60 µA/kHz) f + I
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.002.
T
L
DD
SS
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3
MC14555B, MC14556B
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C)
L
A
(8.)
Characteristic
Symbol
V
DD
Min
Typ
Max
Unit
Output Rise and Fall Time
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
= (0.75 ns/pF) C + 12.5 ns
TLH THL
L
, t
= (0.55 ns/pF) C + 9.5 ns
L
TLH THL
Propagation Delay Time — A, B to Output
t
t
,
ns
ns
PLH
t
t
t
, t
= (1.7 ns/pF) C + 135 ns
= (0.66 ns/pF) C + 62 ns
L
5.0
10
15
—
—
—
220
95
70
440
190
140
PLH PHL
L
PHL
, t
PLH PHL
, t
= (0.5 ns/pF) C + 45 ns
PLH PHL
L
Propagation Delay Time — E to Output
t
,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 115 ns
= (0.66 ns/pF) C + 52 ns
L
t
PHL
5.0
10
15
—
—
—
200
85
65
400
170
130
PLH PHL
L
, t
PLH PHL
, t
= (0.5 ns/pF) C + 40 ns
PLH PHL
L
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
INPUT E LOW
INPUT A HIGH, INPUT E LOW
20 ns
20 ns
20 ns
20 ns
V
DD
90%
50%
10%
V
DD
90%
50%
10%
INPUT B
V
SS
A INPUTS
(50% DUTY CYCLE)
1
2f
V
SS
V
DD
t
t
PLH
PHL
V
OH
90%
50%
10%
OUTPUT Q3
MC14556B
V
SS
B INPUTS
V
OL
(50% DUTY CYCLE)
t
t
V
OH
THL
TLH
t
t
PLH
PHL
V
OH
90%
OUTPUT Q1
V
OL
OUTPUT Q3
MC14555B
50%
10%
V
OL
All 8 outputs connect to respective C loads.
f in respect to a system clock.
L
t
t
TLH
THL
Figure 1. Dynamic Power Dissipation Signal Waveforms
Figure 2. Dynamic Signal Waveforms
LOGIC DIAGRAM
(1/2 of Dual)
*
Q0
A
B
*
Q1
*
Q2
E
*
Q3
* Eliminated for MC14555B
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4
MC14555B, MC14556B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
G
H
J
K
L
M
S
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
PLANE
–T–
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
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5
MC14555B, MC14556B
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
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6
MC14555B, MC14556B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE O
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
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7
MC14555B, MC14556B
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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MC14555B/D
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