MC33151DR2G [ONSEMI]
High Speed Dual MOSFET Drivers; 高速双MOSFET驱动器
| 型号： | MC33151DR2G |
| 厂家： | 
ONSEMI |
| 描述： | High Speed Dual MOSFET Drivers |
| 文件： | 总12页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC34151, MC33151
High Speed Dual
MOSFET Drivers
The MC34151/MC33151 are dual inverting high speed drivers
specifically designed for applications that require low current digital
circuitry to drive large capacitive loads with high slew rates. These
devices feature low input current making them CMOS and LSTTL
logic compatible, input hysteresis for fast output switching that is
independent of input transition time, and two high current totem pole
outputs ideally suited for driving power MOSFETs. Also included is
an undervoltage lockout with hysteresis to prevent erratic system
operation at low supply voltages.
Typical applications include switching power supplies, dc to dc
converters, capacitor charge pump voltage doublers/inverters, and
motor controllers.
These devices are available in dual−in−line and surface mount
packages.
http://onsemi.com
MARKING
DIAGRAMS
8
PDIP−8
P SUFFIX
CASE 626
MC3x151P
AWL
YYWW
8
1
1
8
SOIC−8
D SUFFIX
CASE 751
3x151
ALYW
Features
8
• Pb−Free Packages are Available
1
1
• Two Independent Channels with 1.5 A Totem Pole Output
• Output Rise and Fall Times of 15 ns with 1000 pF Load
• CMOS/LSTTL Compatible Inputs with Hysteresis
• Undervoltage Lockout with Hysteresis
x
A
= 3 or 4
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
• Low Standby Current
• Efficient High Frequency Operation
• Enhanced System Performance with Common Switching Regulator
Control ICs
PIN CONNECTIONS
• Pin Out Equivalent to DS0026 and MMH0026
N.C.
1
2
3
4
8
7
6
5
N.C.
Drive Output A
V
CC
Logic Input A
GND
6
V
CC
+
−
+
+
+
Logic Input B
Drive Output B
5.7V
+
(Top View)
Drive Output A
7
Logic Input A
2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
+
dimensions section on page 9 of this data sheet.
+
Drive Output B
5
Logic Input B
4
3
GND
Figure 1. Representative Block Diagram
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
July, 2004 − Rev. 4
MC34151/D
MC34151, MC33151
MAXIMUM RATINGS
Rating
Symbol
Value
20
Unit
V
Power Supply Voltage
Logic Inputs (Note 1)
V
CC
V
in
−0.3 to V
V
CC
Drive Outputs (Note 2)
A
Totem Pole Sink or Source Current
Diode Clamp Current (Drive Output to V
I
1.5
1.0
O
)
I
O(clamp)
CC
Power Dissipation and Thermal Characteristics
D Suffix SOIC−8 Package Case 751
Maximum Power Dissipation @ T = 50°C
Thermal Resistance, Junction−to−Air
P Suffix 8−Pin Package Case 626
P
0.56
180
W
°C/W
A
D
R
q
JA
Maximum Power Dissipation @ T = 50°C
P
D
1.0
W
A
Thermal Resistance, Junction−to−Air
R
100
°C/W
q
JA
J
Operating Junction Temperature
T
+150
°C
°C
Operating Ambient Temperature
MC34151
MC33151
T
A
0 to +70
−40 to +85
−40 to +125
MC33151V
Storage Temperature Range
T
stg
−65 to +150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
ELECTRICAL CHARACTERISTICS (V = 12 V, for typical values T = 25°C, for min/max values T is the only operating
CC
A
A
ambient temperature range that applies [Note 3], unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
Input Threshold Voltage −
Input Current − High State (V = 2.6 V)
Output Transition High to Low State
Output Transition Low to High State
V
V
−
0.8
1.75
1.58
2.6
−
V
IH
IL
I
IH
−
−
200
20
500
100
mA
IH
Input Current − Low State (V = 0.8 V)
I
IL
IL
DRIVE OUTPUT
Output Voltage − Low State (I
Output Voltage − Low State (I
Output Voltage − Low State (I
Output Voltage − High State (I
Output Voltage − High State (I
Output Voltage − High State (I
= 10 mA)
= 50 mA)
= 400 mA)
V
−
−
−
10.5
10.4
9.5
0.8
1.1
1.7
11.2
11.1
10.9
1.2
1.5
2.5
−
−
−
V
Sink
OL
Sink
Sink
= 10 mA)
= 50 mA)
= 400 mA)
V
OH
Source
Source
Source
Output Pulldown Resistor
R
−
100
−
kW
PD
SWITCHING CHARACTERISTICS (T = 25°C)
A
Propagation Delay (10% Input to 10% Output, C = 1.0 nF)
ns
L
Logic Input to Drive Output Rise
Logic Input to Drive Output Fall
t
t
−
−
35
36
100
100
PLH(in/out)
PHL(in/out)
Drive Output Rise Time (10% to 90%) C = 1.0 nF
t
−
−
14
31
30
−
ns
ns
L
r
Drive Output Rise Time (10% to 90%) C = 2.5 nF
L
Drive Output Fall Time (90% to 10%) C = 1.0 nF
t
−
−
16
32
30
−
L
f
Drive Output Fall Time (90% to 10%) C = 2.5 nF
L
TOTAL DEVICE
Power Supply Current
Standby (Logic Inputs Grounded)
I
mA
V
CC
−
−
6.0
10.5
10
15
Operating (C = 1.0 nF Drive Outputs 1 and 2, f = 100 kHz)
L
Operating Voltage
V
6.5
−
18
CC
1. For optimum switching speed, the maximum input voltage should be limited to 10 V or V , whichever is less.
CC
2. Maximum package power dissipation limits must be observed.
3. T
=
0°C for MC34151
−40°C for MC33151
T
high
=
+70°C for MC34151
+85°C for MC33151
low
http://onsemi.com
2
MC34151, MC33151
12
V
4.7 0.1
+
6
+
+
−
+
+
5.7V
Drive Output
7
+
2
Logic Input
50
C
L
5.0 V
Logic Input
t , t ≤ 10 ns
90%
+
r
f
10%
0 V
+
t
5
PLH
4
t
PHL
90%
10%
Drive Output
3
t
r
t
f
Figure 2. Switching Characteristics Test Circuit
Figure 3. Switching Waveform Definitions
2.4
2.2
V
CC
= 12 V
V
CC
= 12 V
2.0
1.8
1.6
1.4
1.2
1.0
T = 25°C
2.0
1.6
1.2
0.8
A
Upper Threshold
Low State Output
Lower Threshold
High State Output
0.4
0
0
2.0
4.0
6.0
8.0
10
12
−55
−25
0
25
50
75
100
125
V , INPUT VOLTAGE (V)
in
T , AMBIENT TEMPERATURE (°C)
A
Figure 4. Logic Input Current versus
Input Voltage
Figure 5. Logic Input Threshold Voltage
versus Temperature
200
160
200
160
Overdrive Voltage is with Respect
to the Logic Input Lower Threshold
V
= 12 V
C = 1.0 nF
Overdrive Voltage is with Respect
to the Logic Input Lower Threshold
V
= 12 V
C = 1.0 nF
CC
CC
L
L
T = 25°C
A
T = 25°C
A
120
80
40
0
120
80
40
0
V
V
th(upper)
th(lower)
−1.6
−1.2
−0.8
−0.4
0
0
1.0
2.0
3.0
4.0
V , INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V)
in
V , INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)
in
Figure 6. Drive Output Low−to−High Propagation
Delay versus Logic Overdrive Voltage
Figure 7. Drive Output High−to−Low Propagation
Delay versus Logic Input Overdrive Voltage
http://onsemi.com
3
MC34151, MC33151
3.0
High State Clamp
(Drive Output Driven Above V
)
CC
V
= 12 V
80 ms Pulsed Load
CC
2.0
1.0
0
90%
V
V
= 12 V
= 5 V to 0 V
CC
120 Hz Rate
T = 25°C
Logic Input
in
A
C = 1.0 nF
L
T = 25°C
A
V
CC
Low State Clamp
(Drive Output Driven Below Ground)
Drive Output
0
10%
GND
−1.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
50 ns/DIV
I , OUTPUT LOAD CURRENT (A)
O
Figure 8. Propagation Delay
Figure 9. Drive Output Clamp Voltage
versus Clamp Current
0
0
V
= 12 V
80 ms Pulsed Load
Source Saturation
(Load to Ground)
CC
V
CC
= 12 V
Source Saturation
(Load to Ground)
−0.5
−0.7
V
CC
I
I
= 10 mA
V
CC
source
−1.0
−2.0
−3.0
3.0
2.0
1.0
0
120 Hz Rate
T = 25°C
= 400 mA
−0.9
−1.1
A
source
1.9
1.7
I
= 400 mA
sink
1.5
1.0
0.8
I
= 10 mA
sink
Sink Saturation
)
GND
Sink Saturation
)
GND
1.0
0.6
(Load to V
CC
(Load to V
CC
0
−55
0
0.2
0.4
0.6
0.8
1.2
1.4
−25
0
25
50
75
100
125
I , OUTPUT LOAD CURRENT (A)
O
T , AMBIENT TEMPERATURE (°C)
A
Figure 10. Drive Output Saturation Voltage
versus Load Current
Figure 11. Drive Output Saturation Voltage
versus Temperature
V
V
= 12 V
= 5 V to 0 V
CC
90%
90%
in
C = 1.0 nF
L
T = 25°C
A
V
V
= 12 V
= 5 V to 0 V
CC
in
C = 1.0 nF
L
10%
T = 25°C
A
10%
10 ns/DIV
10 ns/DIV
Figure 12. Drive Output Rise Time
Figure 13. Drive Output Fall Time
http://onsemi.com
4
MC34151, MC33151
80
60
40
20
0
80
V
= 12 V
CC
V
V
= 12 V
= 0 V to 5.0 V
CC
Both Logic Inputs Driven
0 V to 5.0 V
50% Duty Cycle
IN
60
40
20
0
T = 25°C
A
Both Drive Outputs Loaded
T = 25°C
f = 200 kHz
A
f = 500 kHz
t
f
f = 50 kHz
t
r
0.1
1.0
C , OUTPUT LOAD CAPACITANCE (nF)
10
0.1
1.0
C , OUTPUT LOAD CAPACITANCE (nF)
10
L
L
Figure 14. Drive Output Rise and Fall Time
versus Load Capacitance
Figure 15. Supply Current versus Drive Output
Load Capacitance
80
60
8.0
T = 25°C
A
Both Logic Inputs Driven
0 V to 5.0 V,
50% Duty Cycle
Both Drive Outputs Loaded
1
Logic Inputs at V
CC
Low State Drive Outputs
6.0
4.0
2.0
2
T = 25°C
A
3
1 − V = 18 V, C = 2.5 nF
CC L
40 2 − V = 12 V, C = 2.5 nF
CC L
3 − V = 18 V, C = 1.0 nF
CC L
4 − V = 12 V, C = 1.0 nF
4
Logic Inputs Grounded
High State Drive Outputs
CC
L
20
0
0
100
1.0 M
10 k
0
4.0
8.0
V , SUPPLY VOLTAGE (V)
CC
12
16
f, INPUT FREQUENCY (Hz)
Figure 16. Supply Current versus Input Frequency
Figure 17. Supply Current versus Supply Voltage
APPLICATIONS INFORMATION
Description
Output Stage
The MC34151 is a dual inverting high speed driver
specifically designed to interface low current digital
circuitry with power MOSFETs. This device is constructed
with Schottky clamped Bipolar Analog technology which
offers a high degree of performance and ruggedness in
hostile industrial environments.
Each totem pole Drive Output is capable of sourcing and
sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 W at
1.0 A. The low ‘on’ resistance allows high output currents
to be attained at a lower V than with comparative CMOS
CC
drivers. Each output has a 100 kW pulldown resistor to keep
the MOSFET gate low when V is less than 1.4 V. No over
CC
current or thermal protection has been designed into the
Input Stage
device, so output shorting to V
avoided.
or ground must be
CC
The Logic Inputs have 170 mV of hysteresis with the input
threshold centered at 1.67 V. The input thresholds are
insensitive to V making this device directly compatible
with CMOS and LSTTL logic families over its entire
operating voltage range. Input hysteresis provides fast
output switching that is independent of the input signal
transition time, preventing output oscillations as the input
thresholds are crossed. The inputs are designed to accept a
Parasitic inductance in series with the load will cause the
driver outputs to ring above V during the turn−on
CC
CC
transition, and below ground during the turn−off transition.
With CMOS drivers, this mode of operation can cause a
destructive output latchup condition. The MC34151 is
immune to output latchup. The Drive Outputs contain an
internal diode to V
for clamping positive voltage
CC
signal amplitude ranging from ground to V . This allows
CC
transients. When operating with V at 18 V, proper power
CC
the output of one channel to directly drive the input of a
second channel for master−slave operation. Each input has
a 30 kW pulldown resistor so that an unconnected open input
will cause the associated Drive Output to be in a known high
state.
supply bypassing must be observed to prevent the output
ringing from exceeding the maximum 20 V device rating.
Negative output transients are clamped by the internal NPN
pullup transistor. Since full supply voltage is applied across
http://onsemi.com
5
MC34151, MC33151
the NPN pullup during the negative output transient, power
gate charge information on their data sheets. Figure 18
shows a curve of gate voltage versus gate charge for the ON
Semiconductor MTM15N50. Note that there are three
distinct slopes to the curve representing different input
capacitance values. To completely switch the MOSFET
‘on’, the gate must be brought to 10 V with respect to the
dissipation at high frequencies can become excessive.
Figures 20, 21, and 22 show a method of using external
Schottky diode clamps to reduce driver power dissipation.
Undervoltage Lockout
An undervoltage lockout with hysteresis prevents erratic
system operation at low supply voltages. The UVLO forces
source. The graph shows that a gate charge Q of 110 nC is
g
required when operating the MOSFET with a drain to source
the Drive Outputs into a low state as V rises from 1.4 V
CC
voltage V of 400 V.
DS
to the 5.8 V upper threshold. The lower UVLO threshold is
5.3 V, yielding about 500 mV of hysteresis.
16
MTM15N50
= 15 A
T = 25°C
A
I
D
Power Dissipation
Circuit performance and long term reliability are
enhanced with reduced die temperature. Die temperature
increase is directly related to the power that the integrated
circuit must dissipate and the total thermal resistance from
the junction to ambient. The formula for calculating the
junction temperature with the package in free air is:
12
V
DS
= 400 V
V
DS
= 100 V
8.0
4.0
8.9 nF
T = T + P (R )
qJA
T = Junction Temperature
J
2.0 nF
J
A
D
D Q
g
C
GS
=
where:
D V
GS
T = Ambient Temperature
A
0
0
40
80
Q , GATE CHARGE (nC)
120
160
P = Power Dissipation
D
g
R
Thermal Resistance Junction to Ambient
qJA =
There are three basic components that make up total
power to be dissipated when driving a capacitive load with
respect to ground. They are:
Figure 18. Gate−To−Source Voltage
versus Gate Charge
P
P + P + P
Q C T
D =
The capacitive load power dissipation is directly related to
the required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:
where:
P = Quiescent Power Dissipation
Q
P = Capacitive Load Power Dissipation
C
P = Transition Power Dissipation
T
PC(MOSFET) = VC Qg f
The quiescent power supply current depends on the
supply voltage and duty cycle as shown in Figure 17. The
device’s quiescent power dissipation is:
The flat region from 10 nC to 55 nC is caused by the
drain−to−gate Miller capacitance, occurring while the
MOSFET is in the linear region dissipating substantial
amounts of power. The high output current capability of the
MC34151 is able to quickly deliver the required gate charge
for fast power efficient MOSFET switching. By operating
PQ = VCC ICCL (1−D) + ICCH (D)
where:
I
= Supply Current with Low State Drive
CCL
the MC34151 at a higher V , additional charge can be
Outputs
CC
provided to bring the gate above 10 V. This will reduce the
‘on’ resistance of the MOSFET at the expense of higher
driver dissipation at a given operating frequency.
I
= Supply Current with High State Drive
Outputs
D = Output Duty Cycle
CCH
The transition power dissipation is due to extremely short
simultaneous conduction of internal circuit nodes when the
Drive Outputs change state. The transition power
dissipation per driver is approximately:
The capacitive load power dissipation is directly related
to the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:
PT = VCC (1.08 VCC CL f − 8 y 10−4
PT must be greater than zero.
)
P = V (V − V ) C f
C
CC
OH
OL
L
where:
V
V
= High State Drive Output Voltage
= Low State Drive Output Voltage
OH
Switching time characterization of the MC34151 is
performed with fixed capacitive loads. Figure 14 shows that
for small capacitance loads, the switching speed is limited
by transistor turn−on/off time and the slew rate of the
internal nodes. For large capacitance loads, the switching
speed is limited by the maximum output current capability
of the integrated circuit.
OL
C = Load Capacitance
L
f = frequency
When driving a MOSFET, the calculation of capacitive
load power P is somewhat complicated by the changing
C
gate to source capacitance C as the device switches. To aid
GS
in this calculation, power MOSFET manufacturers provide
http://onsemi.com
6
MC34151, MC33151
LAYOUT CONSIDERATIONS
High frequency printed circuit layout techniques are
optimum drive performance, it is recommended that the
initial circuit design contains dual power supply bypass
imperative to prevent excessive output ringing and overshoot.
Do not attempt to construct the driver circuit on
wire−wrap or plug−in prototype boards. When driving
large capacitive loads, the printed circuit board must contain
a low inductance ground plane to minimize the voltage spikes
induced by the high ground ripple currents. All high current
loops should be kept as short as possible using heavy copper
runs to provide a low impedance high frequency path. For
capacitors connected with short leads as close to the V pin
CC
and ground as the layout will permit. Suggested capacitors are
a low inductance 0.1 mF ceramic in parallel with a 4.7 mF
tantalum. Additional bypass capacitors may be required
depending upon Drive Output loading and circuit layout.
Proper printed circuit board layout is extremely
critical and cannot be over emphasized.
V
CC
V
in
0.1
47
6
+
−
V
in
+
+
+
+
+
5.7V
+
+
R
g
7
5
2
D
1
TL494
or
TL594
1N5819
4
Series gate resistor R may be needed to damp high frequency parasitic
g
oscillations caused by the MOSFET input capacitance and any series
3
wiring inductance in the gate−source circuit. R will decrease the
MOSFET switching speed. Schottky diode D can reduce the driver’s
g
1
power dissipation due to excessive ringing, by preventing the output pin
from being driven below ground.
The MC34151 greatly enhances the drive capabilities of common switching
regulators and CMOS/TTL logic devices.
Figure 19. Enhanced System Performance with
Common Switching Regulators
Figure 20. MOSFET Parasitic Oscillations
+
+
7
4 X
1N5819
+
Isolation
Boundary
+
+
5
1N
5819
3
3
Output Schottky diodes are recommended when driving inductive loads at
high frequencies. The diodes reduce the driver’s power dissipation by
preventing the output pins from being driven above V and below ground.
CC
Figure 21. Direct Transformer Drive
Figure 22. Isolated MOSFET Drive
http://onsemi.com
7
MC34151, MC33151
V
in
I
B
V
in
+
0
−
+
Base Charge
Removal
R
g(on)
+
C
1
R
g(off)
In noise sensitive applications, both conducted and radiated EMI can
be reduced significantly by controlling the MOSFET’s turn−on and
turn−off times.
The totem−pole outputs can furnish negative base current for enhanced
transistor turn−off, with the addition of capacitor C .
1
Figure 23. Controlled MOSFET Drive
Figure 24. Bipolar Transistor Drive
V
CC
= 15 V
4.7 0.1
+
6
+
−
+
+
+
5.7V
+
6.8 10
1N5819
7
+
2
+ V ≈ 2.0 V
O
CC
+
47
+
+
6.8 10
+
1N5819
47
5
4
− V ≈ − V
O
CC
+
330pF
3
10k
Output Load Regulation
I
O
(mA)
+V (V)
−V (V)
O
O
The capacitor’s equivalent series resistance limits the Drive Output Current
to 1.5 A. An additional series resistor may be required when using tantalum or
other low ESR capacitors.
0
27.7
27.4
26.4
25.5
24.6
22.6
−13.3
−12.9
−11.9
−11.2
−10.5
−9.4
1.0
10
20
30
50
Figure 25. Dual Charge Pump Converter
http://onsemi.com
8
MC34151, MC33151
ORDERING INFORMATION
Device
†
Package
SOIC−8
SOIC−8
Shipping
MC34151D
98 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
MC34151DR2
MC34151DR2G
SOIC−8
(Pb−Free)
MC34151P
PDIP−8
SOIC−8
SOIC−8
50 Units / Rail
98 Units / Rail
MC33151D
MC33151DR2
MC33151DR2G
2500 Tape & Reel
2500 Tape & Reel
SOIC−8
(Pb−Free)
MC33151P
PDIP−8
SOIC−8
50 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
MC33151VDR2
MC33151VDR2G
SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
9
MC34151, MC33151
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8
5
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
−B−
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1
4
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.16
6.60
4.45
0.51
1.78
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
0.370
0.240
0.155
0.015
0.040
F
−A−
NOTE 2
L
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27
0.30
3.43
0.030
0.008
0.115
0.050
0.012
0.135
K
L
C
7.62 BSC
0.300 BSC
M
N
−−−
0.76
10
_
1.01
−−−
0.030
10
_
0.040
J
−T−
SEATING
PLANE
N
M
D
K
G
H
M
M
M
0.13 (0.005)
T
A
B
http://onsemi.com
10
MC34151, MC33151
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AB
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
C
N X 45
_
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
SEATING
PLANE
−Z−
0.10 (0.004)
1.27 BSC
0.050 BSC
M
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
J
H
D
8
0
_
_
_
_
M
S
S
X
0.25 (0.010)
Z
Y
0.25
5.80
0.50 0.010
6.20 0.228
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
MC34151, MC33151
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
MC34151/D
相关型号：
©2020 ICPDF网 联系我们和版权申明