MC33157DW_技术文档

The MC33157 includes the oscillator circuit and two output

channels to control a half–bridge power stage.

One of the channels is ground–referenced. The second one is

floating to provide a bootstrap operation for the high side switch.

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Dedicated Driver for Industrial Linear Tubes

• Main oscillator is current controlled, making it easy to set up by a

single external resistor. On top of that, such a feature is useful to

implement a dimming function by frequency shift.

16

1

• Filament pre–heating time control built–in.

SO–16L

DW SUFFIX

CASE 751G

• The strike sequence is controllable by external passive components,

the resonnant frequency being independently adjustable. This

frequency can be made different from the pre–heating and the steady

state values. A frequency sweep between two defined values makes

this IC suitable for any series resonnant topologies.

PIN CONNECTIONS AND

MARKING DIAGRAM

• Dedicated internal comparator provides an easy lamp strike detection

implementation.

• Digital RESET pin provides a fast reset of the system (less than 10µs).

Both output MOSFET are set to “OFF” state when RESET is zero.

• Adjustable dead time makes the product suitable for any snubber

capacitor and size of MOSFET used as power switches.

• Designed to be used with standard setting capacitors ≤ 470nF.

• A voltage reference, derived from the internal bandgap, is provided

for external usage. This voltage is 100% trimmed at probe level

yielding a 2% tolerance over the temperature range.

1

2

3

4

5

6

7

8

16

15

14

V

HS

DD

+V

V

HO

ref

C

PH

V

OUT

R

PH

12

11

10

9

C

V

LO

SWEEP

C

OP

GND

RESET

SD

ICO

C

SWEEP

R

PH

C

R

DTA

PH

OP

6

OP

V

DD

AWL = Manufacturing Code

YYWW = Date Code

ICO

2

+Vref

1

4

5

3

7

+Vref

Iph

(Top View)

15 V

R

U

VLO

Iph

Ifstrike

PREHEAT

& STRIKE CONTROL

BAND GAP

REFERENCE

Iop

ORDERING INFORMATION

+Vref

Device

Package

Shipping

47 Units / Rail

+Vref

(+7 V)

R

+Vref

MC33157DW Plastic SO–16L

DT adjust

16

15

14

13

12

11

ENABLE

Dead Time

VHS

VHO

VOUT

NC

8

9

HIGH SIDE

BUFFER

LEVEL

SHIFTER

Latch

CONTROL LOGIC

Strike Detection

Strike

Detection

Q

Vth

C

LOW SIDE

BUFFER

VLO

GND

Clear

10

INHIBIT

RESET

Semiconductor Components Industries, LLC, 1999

1

Publication Order Number:

November, 1999 – Rev. 1

MC33157/D

MC33157

MAXIMUM RATINGS

Rating

Symbol

Value

600

16

Unit

V

High Side Max Voltage

V

HS

Differential Max Voltage V

– V

V

HS

V

HS

OUT

High Side Output Voltage Range

Low Side Output Voltage Range

V

–0.3 to V +0.3

V

HO

OUT HS

V

–0.3 to +16

±10

V

LO

Max V

Allowable Slew Rate

dV /dt

HS

V/ns

HS

/V

HO LO

Allowable Slew Rate

(Note 1)

dV /dt, dV /dt

HO LO

±10

Supply Voltage

V

P

16

600

140

V

DD

D

Maximum Power Dissipation @ T = 50°C

Thermal Resistance Junction–to–Air

Operating Junction Temperature

mW

°C/W

°C

A

R

T

θJA

–40 to +150

J

Storage Temperature Range

Electrostatic Discharge [HBMI]

T

–65 to +150

2.0

°C

stg

ESD

kV

ELECTRICAL CHARACTERISTICS (V

unless otherwise noted.)

= 14V. All parameters are specified for –20°C to 85°C ambient temperature

DD

Characteristic

Symbol

Min

Typ

Max

Unit

SUPPLY VOLTAGE

Input Threshold Voltage

Turn–On

Turn–Off

UV

11

8.0

12

8.5

12.8

9.0

V

ON

UV

OFF

Clamp Voltage @ I

CLAMP

= 10 mA

V

15

16

12

16.5

V

CLAMP

(Note 2)

Supply Current

I

S

mA

Standby Current at No Load @ V

< UV

I

STDBY

1.5

2.5

DD

OFF

Quiescent Current at No Load @ V

> UV

I

Q

DD

ON

OUTPUT DRIVERS (V , V

LO HO

)

High Side VDS

@ Source current = 250 mA

@ Sink current = 300 mA

V

(P)

(N)

–

880

40

1500

mV

ns

ON

DS

Low Side VDS

V

DS

High Side / Low Side rise time @ C

= 2 nF

t

r

OUT

High Side / Low Side fall time @ C

OSCILLATOR

t

f

35

ns

OUT

Output Max Frequency

f

250

–

kHz

%

OSC

Internal Master Clock Duty Cycle

DC

–

50

System operation programming recommended values

R

68

10

100

560

2200

250

560

k

OP

PH

R

ENDSWEEP

R

C

DTA

OP

pF

V

High threshold

Low threshold

–

4.2

2.8

400

2.0

–

V

COP

I

discharging current

µA

COP

over I

current ratio

COP

ROP

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2

MC33157

ELECTRICAL CHARACTERISTICS (continued) (V

unless otherwise noted.)

= 14V. All parameters are specified for –20°C to 85°C ambient temperature

DD

Characteristic

TIMING

Symbol

Min

Typ

Max

Unit

Preheat timing capacitor pulsed charging current

(Duty Cycle=1/16)

It

PH

14

16

17

µA

Filament preheat time with C

= 0.47 µF

t

–

2.0

125

1/16

10

–

s

PH

Strike sequence recycling time with C

= 0.47 µF

t

ms

PH

SK

C

charging current ratio

∂

–

PH

Strike sequence restart blanking time with C

Dead time: externally adjustable by Rdt

= 470nF

t

–

ms

µs

k

PH

bk

dt

0.3

10

–

2.5

220

Dead time adjust resistance (Recommended range)

Dead time tolerance

Rdt

–

dt

±10

%

Tol

VOLTAGE REFERENCE

Voltage reference @ I

= 500 µA, T = 25°C

V

–

7.0

10

–

V

LOAD

J

REF

Line regulation @ I

LOAD

= 500 µA, T = 25°C

V

mV

mA

V

J

REF

Load regulation @ I

= 500 µA to 5 mA

V

–

LOAD

REF

Maximum load current

I

–

25

7.15

REFMAX

Total V

variation over Line, Temperature, Load

V

REF

6.85

7.0

REF

INPUT

Strike detect high voltage threshold

Strike detect low voltage threshold

VTH HI

SD

–

4.0

3.75

–

V

VTH LO

SD

Maximum current on strike detect input @ Regulation level

Maximum voltage on strike detect @ Regulation level

Maximum current on strike detect input @ Low level

Maximum strike detect voltage negative input

Strike detect minimum pulse width

I

HI

–

10

7.0

10

–0.3

–

nA

V

SD

V

SD

HI

–

I

LO

–

nA

V

SD

V

SD

NEG

–

SDPW

RSTHI

RSTLO

50

–

100

1.8

–20

–

ns

V

RESET high voltage

2.2

–

RESET low voltage

1.6

–

V

RESET input current @ high voltage

RESET input current @ low voltage

RESET maximum voltage

–

µA

V

–

7.0

–0.3

RESET maximum negative voltage

–

V

NOTES:

(1) Since this device has a built–in zener, one cannot use a low impedance supply to drive this pin. Having a current limit mode by external

means is mandatory.

(2) Test Conditions: C

OUT

= 2.2 nF, f = 100 kHz, V = 15V.

DD

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MC33157

PIN FUNCTION DESCRIPTION

Symbol

Function

Description

1

V

DD

Supply voltage

input

This pin provides the DC supply to the circuit. The voltage is internally clamped by a zener

connected to the ground. It is NOT allowed to use a DC low impedance power supply to feed this

pin, but limiting the current by an external resistor is mandatory. It is recommended to damp this pin

to ground by an electrolytic capacitor connected close to pin 1.

2

3

+V

Voltage

reference

output

This pin provides a +7V voltage reference derived from the internal bandgap. The +Vref can supply

up to 25 mA and shall be decoupled to ground by a 220nF ceramic capacitor

ref

C

R

Preheat timing

capacitor

This capacitor sets two timings: filaments preheat time (t ) and strike sequence recycle time (t ).

PH SK

PH

It is charged with a constant current and cares must be observed to minimize the leakage current

at this pin to get the expected timing. Typically, a 0.47 µF capacitor will give a 2 seconds

pre–heating time and a 125 ms strike sequence recycle time. (See details given by figure 9)

4

Preheat and

Strike

frequencies

adjustment

resistors

The R

resistor together with R

and C

OP

defines the frequency used to preheat the

= f ). Duringthesweep

PH

filaments(f

ENDSWEEP

= f ). R

definesthestrikefrequency(f

PH

1

ENDSWEEP

2

timing, the frequency will sweep from the high pre–heating f to the low strike f values. Normally,

1

2

f

is far from the LC resonance but f is close enough to generate the high voltage across the

1

2

fluorescent tube. (See details given by figure 9)

5

6

7

C

Frequency

sweep timing

capacitor

This timing define the sweep time from f to f . Since the timing capacitor is charged with a low

constant current, cares must be observed to minimize the leakage current at this pin to get the

SWEEP

1

2

expected timing. Since this capacitor is charged through resistor R , the voltage rises according

PH

to an exponential and the frequency shifts with the same law.

C

Oscillator

capacitor

This pin defines the steady state operation frequency (f = f ) of the controller. Since this timing

OP

3

capacitor is charged with a low constant current, cares must be observed to minimize the leakage

current at this pin to get the expected frequency. Film type capacitor are recommended

(polycarbonate).

ICO

Steady state

operating

Since the circuit uses a Current Controlled Oscillator (ICO), the current forced into this pin will

control the operating frequency. The allowable current range is from 1 µA to 500 µA. The +Vref

frequency

adjustment

current input

output can be used to provide the voltage across R . An auxiliary voltage source can be used to

implement a dimming function.

OP

8

9

DTA

SD

Dead Time

Adjust

This pin provides an access to the internal timing system to adjust the dead time between the gate

drive of the High and Low power switches connected, respectively, to pin V

HO

and V

.

LO

Strike detection

input

This pin drives a comparator, with an internal fixed reference, and acknowledges the tube strike.

When a negative going slope (across the internal reference) is detected, the system considers the

lamp has struck and the oscillator jumps from the present frequency value, which is within the

window defined by R

and R

to the steady state value defined by R . If no negative

PH

ENDSWEEP

OP

going slope is detected on this pin, the system will repeat the sweep and strike sequence four

times, then stops. The circuit will re–start from either a RESET, or by pulling +V to ground. The

DD

input signal can be either a logic level or an analog voltage ramping up from zero to +Vref followed

by a negative going slope to zero. In any case, the positive pulse width must be 1 µs minimum. The

pcb layout must be designed to minimize the noise at this pin. (See details given by figures 8, 9, &

10)

10

RESET

Master reset

input

Forcing a logic zero to this pin (HCMOS low level) will reset the circuit, initializing a frequency sweep

and lamp strike sequence. The master reset does not include the pre–heating timing. The minimum

pulse width requested is 10µs to guarantee a reset state. However, this pin has no built in filtering

and a shorter pulse may initialize a reset sequence: it is the responsibility of the designer to make

sure that no noise or parasitic pulse are developed at the RESET input. A full re–start of the

sequence, including the pre–heating time, can be initialized by pulling the +V

case, +V

DD

pin to ground. In this

and RESET must be simultaneously released to a high state. When RESET is asserted

DD

low (active) both outputs MOS are biased in the off condition. An internal 20µA pull up current forces

the pin to logic one, allowing the designer to left this pin open if the RESET function is not used. In

order to avoid any uncontrolled state of the output drivers, it is recommended to set up a 10ms low

level at pin 10. The reset is activated in less than 10 microsecond, but releasing this pin while the Vcc

supply is high (above 300V) can generate a random operation, depending upon the dv/dt coming

from the power supply.

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4

MC33157

PIN FUNCTION DESCRIPTION (continued)

Description

Symbol

Function

11

GND

Ground

(zero voltage

reference)

Since high and fast currents circulate in the circuit, it is mandatory to build a single ground point in

the system.

12

V

LO

Low side driver

output

This pin provides the V to drive the Low side power MOSFET.

GS

13

14

NC

Not Connected

V

OUT

High side

common point /

Half bridge

output

This pin is connected to the output of the half bridge and is referenced for the High side switch.

15

16

V

High side driver

output

This pin provides the V to drive the High side power MOSFET.

GS

HO

V

High voltage

boost supply

The gate drive of the High side switch is derived from this voltage.

HS

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5

MC33157

+Vref

Internal

Circuits

6

2K

C

OP

External

10 V

ESD

10 V

ESD

Figure 1. PIN 6 C

INPUT

OP

+Vref

I

SWP

I

PH

(8 UA)

ph/swp Switch

2K

CAN’T READ

3

C

10 V

ESD

10 V

ESD

PH

I

blanking

(200 uA)

(external)

Figure 2. PIN 3 C

INPUT

PH

+Vref

Internal

Circuits

5V

10

2K

0V

10 V

ESD

10 V

ESD

Figure 3. PIN 10 RESET

+Vref

4 V

Internal

Circuits

0.0 V

9

2K

10 V

ESD

10 V

ESD

Hysteresis Switch

Figure 4. PIN 9 SD

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6

MC33157

+Vref

8

1

I

I/8

2K

Internal

Circuits

8

10 V

ESD

10 V

ESD

R

DTA

(external)

Figure 5. PIN 8 DTA

+Vref

10 V

ESD

2

R

I

OP

(external)

2K

6

7

10 V

ESD

2I

10 V

ESD

C

OP

(external)

1 k

(internal)

Figure 6. PIN ICO

+Vref

10 V

ESD

2

ph/swp switch

2K

C

SWP

(external)

5

R

ENDSWEEP

(external)

10 V

ESD

10 V

ESD

R

PH

I

(external)

10 V

ESD

10 V

ESD

6

4

2K

2I

C

OP

(external)

1 k

(internal)

Figure 7. PIN 2, 4 & 5 V , R

ref PH

& C

SWP

V

T

1 s

SD max

SDHIVth

4 V typ

SDLOVth

3.75 V typ

Internal Hysterisis

t

The Strike Detect is acknowledged as soon as the input

voltage drops below SDLOVth. It is not necessary to pull

the input voltage to zero volt or to a negative bias

SDNEG max

Figure 8. STRIKE DETECTION

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7

MC33157

Rise time lms

V

DD

U

VLO

RESET

U

VON

9.2 V typ

U

VLO

3.8 V typ

7.0 V typ

V

ref

tph

V

CPH

(PREHEAT)

Frequency

SWEEP

t

1 s

STRIKE

DETECTION

STRIKE

1

0

RESET

Output

Frequency

status

F1

F2

F3

F1

F2

F3

OFF STATE

time

f = f , preheating frequency adjusted by R and R

PH PH ENDSWEEP

1

f = f

, end of sweep frequency, adjusted by R

pin 2). In any case f

f

2

ENDSWEEP

ENDSWEEP (

1

f = f , operating frequency controlled by the I current (pin 7) and capacitor C

OP CO OP

3

t

= (C * 2/3 * Vref) / ( * I )

PH tPH

PH

“OFF” state: High side switch OFF, Low side switch ON

Figure 9. TIMING DIAGRAM (Normal startup sequence and U

reset)

VLO

10 s

1

0

RESET

V

repeats indefinitely

CSWP

No further logic action activated

+V

ref

V

CSWP

SD

LOW

HIGH

STRIKE

DETECTION

Output Frequency

status

F3

OFF STATE

FSweep

time

Previous On state

When RESET pin is released to a logic one, the system jumps to the preheat frequency as defined by RPH,

then executes a frequency sweep down to f , as defined by R , and waits until a strike

ENDSWEEP ENDSWEEP

detection signal is applied to pin 9. There is no preheating timing performed after a reset coming from pin 10.

RESET logic level is CMOS compatible.

Note: Strike detection lever can be either digital – CMOS or analog as depicted here above, as long as the

signal fulfills the SD

and SD

values and timing.

HIGH

LOW

OFF STATE: both output MOSFET are biased in the off condition.

Figure 10. TIMING DIAGRAM (External reset)

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8

MC33157

1

0

RESET

End of preheating sequence

Blanking 10 ms typ

Blanking

Last restrike valid cycle

@ C = 470 nF

PH

+V

ref

V

CSWP

t

F

t

FEND

t

SK

SD

HIGH

V

+V

ref

SD

LOW

STRIKE

DETECTION

Output

Frequency status

FSweep

F2 F1

F2

F3

time

t

: Sweep Frequency time. This time is given by the RC network built with C

: Sweep sequence recycle time. This time is derived by integrating a constant DC current in capacitor

and R .

PH

SF SWEEP

t

C

SK

There is a fixed ratio ( ) between the preheating time t and strike sequence recycle time t .

PH SK

PH.

t

: Time during which f = (f

). This time is equal to t – t .

fEND

ENDSWP SK SF

The controllerrepeats the f

andthe strike sequence untilthere is a STRIKEsignalcomingfromthe externalcircuit, oruntilFOURsequences have beencounted.

SWEEP

Following a non strike situation, the controller goes in a full STOP and can be reinitialized by either pulling the V pin 1 to ground or by forcing a low to the RESET

pin 9. The controller assumes the lamp has struck when a negative going transient is applied on the STRIKE detection pin 10. On the other hand, in order to avoid false

DD

strike information, the controller force a blank time between the end of t

SWEEP

and the start of the next sequence.

Figure 11. TIMING DIAGRAM (no strike conditions)

5

4.5

4

I = V/√ [(R²+ (L – 1/C )²]

Z @ RLCF

I = V/√ [(R²+ (L )²]

3.5

3

Z = Lw

2.5

2

1.5

1

0.5

0

Frequency (F)

Figure 12. OUTPUT = f (freq) @ Lc = 1.5 mH, Cs = 6.8 nF

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9

MC33157

+400 V

R3

R9

10 F/25 V

C3

C4

D1

MUR160

R4

7

2

1

16

Q1

MTP6N60E

I

0

+V

V

HS

C

REF DD

C2

C1

6

3

4

C

OP

15

14

V

HO

Ns

C

PH

T1

D3

R2

U1

MC33157

V

R

OUT

PH

Np

Q2

MTP6N60E

5

8

C6

12

V

C

1N4148

LO

SWP

R5

D

TA

RESET

10

GND

11

SD

9

Typical Values for F = 70 kHz, F = 45 kHz, t = 2 s, t = 125 ms

SWEEP

PH

OP

PH

T1 Np =

Ns =

R1 390 k

C1

C2

C3

C4

C5

C6

C7

C8

C9

470 nF/25 V/Polyester

470 pF/2%/50 ppm

10 F/25 V/Electrolytic

220 nF/Polyester

100 nF/63 V/Polyester

220 nF/25 V/Polyester

6.8 nF/5%/1000 V

100 nF/400 V/Polyester

R2 62 k

Lp = 150 mH

R3 100 k – 0.5 W

R4 100 k

R5 82 K

R6 1 M

R7 68 K

Q1 MTP6N60E

Q2 MTP6N60E

D1 MUR160RL

D2 MUR120RL

D3 1N4148

R8 68 k

R9 22

U1 MC33157

C10 22 F/450 V/Electrolytic

C11 100 nF/25 V/Polyester

C12 330 pF/500 V/Polyester

TO SEE: AN1682 (Using the MC33157 Electronic Ballast Controller)

Figure 13. Typical Application Schematic Diagram

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10

MC33157

PACKAGE DIMENSIONS

SO–16L

DW SUFFIX

PLASTIC PACKAGE

CASE 751G–03

ISSUE B

A

D

16

9

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS

OF THE B DIMENSION AT MAXIMUM MATERIAL

CONDITION.

1

8

MILLIMETERS

B

16X B

DIM MIN

MAX

2.65

0.25

0.49

0.32

10.45

7.60

A

A1

B

C

D

E

2.35

0.10

0.35

0.23

10.15

7.40

M

S

0.25

T A

B

e

1.27 BSC

H

h

L

10.05

0.25

0.50

0

10.55

0.75

0.90

7

SEATING

PLANE

14X

e

C

T

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11

MC33157

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular

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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

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MC33157/D

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12


型号：	MC33157DW
厂家：	ONSEMI
描述：	Half Bridge Controller and Driver for Industrial Linear Tubes 半桥控制器和驱动器，用于工业线性管驱动器控制器
文件：	总12页 (文件大小：271K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC33157DW [ONSEMI]

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