MC33364DR2_技术文档

MC33364

Critical Conduction

GreenLine SMPS

Controller

The MC33364 series are variable frequency SMPS controllers that

operate in the critical conduction mode. They are optimized for high

density power supplies requiring minimum board area, reduced

component count, and low power dissipation. Integration of the high

voltage startup saves approximately 0.7 W of power compared to the

value of the resistor bootstrapped circuits.

Each MC33364 features an on- board reference, UVLO function, a

watchdog timer to initiate output switching, a zero current detector to

ensure critical conduction operation, a current sensing comparator, leading

edge blanking, a CMOS driver and cycle- by- cycle current limiting.

The MC33364D1 has an internal 126 kHz frequency clamp. The

MC33364D2 is available without an internal frequency clamp. The

MC33364D has an internal 126 kHz frequency clamp which is pinned

out, so that the designer can adjust the clamp frequency by connecting

appropriate values of resistance.

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MARKING

DIAGRAMS

8

SO-8

D1, D2 SUFFIX

CASE 751

M64Dx

ALYW

8

1

16

SO-16

D SUFFIX

CASE 751K

MC33364D

AWLYWW

16

1

General Features

x

A

= 1 or 2

= Assembly Location

• Lossless Off-Line Startup

• Leading Edge Blanking for Noise Immunity

• Watchdog Timer to Initiate Switching

• Operating Temperature Range -25° to +125°C

• Shutdown Capability

• Over Temperature Protection

• Optional/Adjustable Frequency Clamp to Limit EMI

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

PIN CONNECTIONS

MC33364D1

MC33364D2

ORDERING INFORMATION

Line

1

2

3

4

8

7

6

5

Zero Current

Current Sense

Voltage FB

V

CC

Device

Package

SO-8

Shipping

Gate Drive

GND

MC33364D1

MC33364D1R2

MC33364D2

MC33364D2R2

MC33364D

98 Units / Rail

V

ref

SO-8 Tape & Reel

SO-8

2500 Units / Tape & Reel

98 Units / Rail

(Top View)

MC33364D

SO-8 Tape & Reel

SO-16

2500 Units / Tape & Reel

48 Units / Rail

Line

N/C

1

16

Zero Current

N/C

2

3

4

5

6

7

8

MC33364DR2

SO-16 Tape & Reel

2500 Units / Tape & Reel

Current Sense

Voltage FB

N/C

13

12

V

cc

V

ref

11 Gate Drive

10 P GND

N/C

Freq Clamp

9

A GND

(Top View)

Semiconductor Components Industries, LLC, 2003

1

Publication Order Number:

May, 2003 - Rev. 13

MC33364/D

MC33364

Vcc

Vref

Line

Startup

turn on

Vref regulator

UVLO

Vref

Vcc

turn on

+

-

UVLO

+

-

15V/ 8.1V

-

+

ZCD

15V/ 7.6V

Vref

UVLO

10V

1.2V/ 1.0V

+

-

Thermal

5k

Shutdown

Reset

15V/ var

45k

15k

Watchdog

Timer

FB

Vcc

R

Level

SNA

R

S

Q

Gate

-

+

LEB

CS

FC

P Gnd

A Gnd

0.1V

Frequency Clamp

Figure 1. Representative Block Diagram

Input

AC Voltage

Output

Voltage

MC33364D

ZCD

Line

CS

FB

Vcc

Drive

P Gnd

A Gnd

Vref

FC

Rsense

R1

R2

Figure 2. Typical Application Circuit

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2

MC33364

Startup circuit is

charging the VCC

capacitor

Startup circuit turns

off when VCC is 15V

15V

Supply Voltage, VCC

8.1V

5V

VT (3.5 to 6V)

Startup circuit turns

on when VCC reaches

the threshold VT

Reference Voltage, Vref

0V

Vref regulator turns on

when VCC reaches 15V

Vref falls faster than VCC

since Vref capacitor is much

smaller than VCC capacitor

Vref regulator turns

off when VCC falls

below 8.1 V

Maximum drain current is

limited to 1.15V / Rsense

Drain Current

0A

Switching stops when

Vref falls below 3.7V

Switching starts when

Vref reaches 5V

Figure 3. Timing Diagram in Fault Condition

Criticial Mode

Discontinous Conduction Mode

Output

No load

Current

Maximum drain current is limited to 1.15V/ Rsense

Drain

LEB

Current

toff(min)

Secondary

Side Diode

Current

Vin

Drain

Voltage

10V

Voltage

at ZCD

0.7V

ZCD is ignored during minimum off-time limit

Figure 4. Timing Diagram in Normal Condition

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3

MC33364

PIN DESCRIPTION

Function

Description

1 (1)

Zero Current Detect

The ZCD Pin ensures critical conduction mode. ZCD monitors the voltage on the auxiliary winding,

during the demagnetization phase of the transformer, comparing it to an internal reference. The

ZCD sets the latch for the output driver.

3 (2)

4 (3)

Current Sense

The Current Sense Pin monitors the current in the power switch by measuring the voltage across

a resistor. Leading Edge Blanking is utilized to prevent false triggering. The voltage is compared to

a resistor divider connected to the Voltage Feedback Pin. A 110 mV voltage off-set is applied to

compensate the natural optocoupler saturation voltage.

Voltage Feedback

The Voltage Feedback Pin is typically connected to the collector of the optocoupler for feedback

from the isolated secondary output. The Feedback is connected to the V Pin via a 5 k resistor

ref

providing bias for the external optocoupler.

6 (4)

V

ref

The V Pin is a buffered internal 5.0 V reference with Undervoltage Lockout.

ref

8 (NA)

Frequency Clamp

The Frequency Clamp Pin ensures a minimum off-time value, typically 6.9 ms. It prevents the

MOSFET from restarting within a fixed (33364D1) or adjustable (33364D) delay. The minimum

off-time is disabled in the 33364D2. Therefore the maximum switching frequency cannot exceed

1/(T + T

).

ON

OFFmin

9 (5)

10 (5)

11 (6)

12 (7)

A GND

P GND

This pin is the ground for the internal circuitry excluding the gate drive stage.

This pin is the ground for the gate drive stage.

Gate Drive

The gate drive is the output to drive the gate of the power MOSFET.

V

CC

Provides the voltage for all internal circuitry including the gate drive stage and V . This pin has

ref

Undervoltage Lockout with hysteresis.

16 (8)

Line

The Line Pin provides the initial power to the V pins. Internally the line pin is a high voltage

CC

current source, eliminating the need for an external startup network.

For further information please refer to the following Application Notes;

AN1594: Critical Conduction Mode, Flyback Switching Power Supply Using the MC33364.

AN1681: How to keep a Flyback Switch-Mode Power Supply Stable with a Critical-Mode Controller.

MAXIMUM RATINGS (T = 25°C, unless otherwise noted.)

A

Rating

Power Supply Voltage (Operating)

Symbol

Value

16

Unit

V

CC

Line Voltage

V

Line

700

V

Current Sense, Compensation,

V

in1

-1.0 to +10

V

Voltage Feedback, Restart Delay and Zero Current Input Voltage

Zero Current Detect Input

Restart Diode Current

I

±5.0

mA

in

I

in

5.0

Power Dissipation and Thermal Characteristics

D1 and D2 Suffix, Plastic Package Case 751

Maximum Power Dissipation @ T = 70°C

Thermal Resistance, Junction-to-Air

P

450

178

mW

°C/W

A

D

R

q

JA

D Suffix, Plastic Package Case 751B-05

Maximum Power Dissipation @ T = 70°C

Thermal Resistance, Junction-to-Air

P

550

145

mW

°C/W

A

D

R

q

JA

Operating Junction Temperature

T

150

°C

J

Operating Ambient Temperature

T

A

-25 to +125

-55 to +150

Storage Temperature Range

T

stg

NOTE: ESD data available upon request.

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4

MC33364

ELECTRICAL CHARACTERISTICS (V = 15.5 V, for typical values T = 25°C, for min/max values T = -25 to 125°C)

CC

A

J

Characteristic

Symbol

Min

Typ

Max

Unit

VOLTAGE REFERENCE

Reference Output Voltage (I

= 0 mA, T = 25°C)

V

ref

4.90

5.05

2.0

0.3

5

5.20

50

-

V

Out

J

Line Regulation (V = 10 V to 20 V)

Reg

-

mV

mA

V

CC

line

Load Regulation (I

= 0 mA to 5.0 mA)

Reg

load

Out

Maximum V Output Current

I

O

ref

Reference Undervoltage Lockout Threshold

V

4.5

-

th

ZERO CURRENT DETECTOR

Input Threshold Voltage (V Decreasing)

V

0.9

-

1.0

1.1

-

V

mV

V

in

Hysteresis (V Decreasing)

V

H

200

in

Input Clamp Voltage - High State (I

Input Clamp Voltage - Low State (I

= 3.0 mA)

V

IH

9.0

-1.1

10.33

-0.75

12

0.5

DET

= -3.0 mA)

V

IL

DET

CURRENT SENSE COMPARATOR

Input Bias Current (V = 0 to 2.0 V)

I

-0.5

50

0.02

108

1.24

232

0.5

170

1.4

mA

mV

V

CS

IB

Built In Offset

V

IO

FB

Feedback Pin Input Range

Feedback Pin to Output Delay

DRIVE OUTPUT

V

1.1

100

t

400

ns

DLY

Source Resistance (Drive = 0 V, V

= V - 1.0 V)

= 1.0 V)

R

OH

R

OL

10

5

36

11

70

25

W

Gate

CC

Sink Resistance (Drive = V , V

CC

Gate

Output Voltage Rise Time (25% - 75%) (C = 1.0 nF)

t

-

67

28

150

50

ns

V

L

r

Output Voltage Fall Time (75% - 25%) (C = 1.0 nF)

t

f

L

Output Voltage in Undervoltage (V = 7.0 V, I

= 1.0 mA)

V

0.01

0.03

CC

Sink

O(UV)

LEADING EDGE BLANKING

Delay to Current Sense Comparator Input

t

-

250

-

ns

°C

ms

PHL(in/out)

(V = 2.0 V, V = 0 V to 4.0 V step, C = 1.0 nF)

FB

CS

L

THERMAL SHUTDOWN

Shutdown (Junction Temperature Increasing)

Hysteresis (Junction Temperature Decreasing)

T

-

180

50

-

sd

T

H

TIMER

Watchdog Timer

t

200

360

700

DLY

UNDERVOLTAGE LOCKOUT

Startup Threshold (V Increasing)

V

14

15

16

V

CC

th(on)

Minimum Operating Voltage After Turn-On (V Decreasing)

V

6.5

7.6

8.5

CC

Shutdown

FREQUENCY CLAMP

Internal FC Function (pin open)

Internal FC Function (pin grounded)

Frequency Clamp Input Threshold

Frequency Clamp Control Current Range (Sink)

Dead Time (FC pin = 1.7 V)

f

104

400

1.89

30

126

564

1.95

70

145

800

2.01

110

6.5

kHz

V

max

V

th(FC)

I

mA

ms

Control

T

d

3.5

5.0

TOTAL DEVICE

Line Startup Current (V

Restart Delay Time

= 50 V) (V = V

- 1.0 V)

I

Line

5.0

8.5

100

12

mA

ms

Line

CC

th(on)

t

DLY

Line

Line Pin Leakage (V

= 500 V)

I

0.5

6.0

1.5

300

32

10

70

12

mA

Line

Line Startup Current (V = 0 V, V

= 50 V)

CC

Line

V

Dynamic Operating Current (50 kHz, C = 1.0 nF)

I

CC

2.75

544

4.5

800

CC

L

V

Off State Consumption (V = 11 V)

I

CC Off

CC

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5

MC33364

30

500

V

= 14 V

C = 1000 pF

CC

25

20

L

T = 25°C

A

450

400

350

300

V

CC

= 15 V

15

10

5.0

0

−5.0

−55

−25

0

25

50

75

100

125

5.0 ms/DIV

T , AMBIENT TEMPERATURE (°C)

A

Figure 6. Watchdog Timer Delay

versus Temperature

Figure 5. Drive Output Waveform

6.0

4.0

2.0

0

1000

D Suffix

16 Pin SOIC

Circuit of Figure

12

T = 25°C

A

100

10

0.01

4.0

6.0

8.0

10

12

14

16

0.1

1.0

10

100

V

CC

, SUPPLY VOLTAGE (V)

t, TIME (s)

Figure 8. Transient Thermal Resistance

Figure 7. Supply Current

versus Supply Voltage

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

40

35

30

25

20

15

10

FC−to−Vref

D Suffix

16 Pin SOIC

T = 25°C

A

V

CC

= 15 V

FC−to−Gnd

5

0

−0.2

−0.4

10

100

1000

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

FEEDBACK VOLTAGE

RESISTOR (kW)

Figure 9. Minimum Off-time versus Timing Resistor

on the FC Pin

Figure 10. Feedback Voltage versus

Current Sense Voltage

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6

MC33364

OPERATING DESCRIPTION

Introduction

this case. Figure 3 shows the timing diagram in a fault

condition. There are three Under-Voltage Lock-Out

The MC33364 series represents a variable-frequency

current-mode critical-conduction solution with integrated

high voltage startup and protection circuitry to implement an

off-line flyback converter for modern consumer electronic

power supplies. Different frequency clamp options offer

different customized needs. This device series includes an

integrated 700 V Very High-Voltage (VHV) start-up

circuit. Thus, it is possible to design an application with

universal input voltage from 85 Vac to 265 Vac without any

additional startup circuits or components.

(UVLO) thresholds with respect to V . The upper

CC

threshold is 15 V. When this limit is reached, the startup

circuit block turns off and V

declines due to power

CC

consumption of the circuitry. The startup circuit block turns

on when V reaches 7.6 V and if V is higher than 3.7 V.

CC

ref

It is the second threshold of V . If V is smaller than 3.7 V,

CC

ref

the startup circuit will turn on when V

reaches a

CC

temperature dependent value V ranging between 3.5 V and

T

6 V. It is the last threshold of V . This temperature

CC

The critical conduction feature offers some advantages.

First, the MOSFET turns on at zero current and the diode

turns off at zero current. The zero current reduces these

turn-on and turn-off switching losses. It also reduces the

Electro-Magnetic Interface (EMI) of the SMPS and a less

expensive rectifier can be used. Second, by preventing the

SMPS from entering the discontinuous conduction mode

(DCM), the peak MOSFET drain current is limited to only

twice the average input current. It needs a smaller and less

expensive MOSFET. Third, by preventing the SMPS from

entering the Continuous Conduction Mode (CCM), the

flyback topology transfer function stays first-order and its

feedback compensation network is considerably simplified.

It also maximizes the power transfer by the flyback

dependent threshold is lower when temperature is higher so

that it takes a longer time to restore the V . It is a protection

CC

feature, which allows more dead time for cooling in high

temperature condition.

There is an UVLO in the V regulator block. When V

ref

CC

falls below typical 8.1 V in abnormal situation, the V

ref

regulator block stops. V and V collapses due to power

ref

CC

consumption of the circuitry. When V collapses to below

ref

3.7 V, the device cannot provide the Drive output and makes

a dead time. This dead time is designed for minimal power

transfer in the abnormal conditions. The dead time ends

when V reaches 15 V after reaching the UVLO limit V

CC

T

(3.5 to 6 V). Reaching V enables the startup circuit block,

T

charging up the V capacitor again. When V reaches

CC

2

transformer to its 1/2 L I limits.

15 V again, the V regulator block turns on and allows the

ref

A description of each of the functional blocks is given

below. The representative block diagram and typical

application circuit are in Figure 1 and Figure 2.

output to work again.

It is recommended to put a 0.1 uF capacitor on V pin for

stability of the voltage buffer. The V

ref

capacitor is

CC

relatively larger than this 0.1 uF capacitor, making a longer

charging time from V to 15 V and a longer dead time

in the abnormal or fault conditions.

Line, V_CC, Startup Circuit and Reference Voltage

V

CC

T

The Line pin is capable of a maximum 700 V so that it is

possible to connect this pin directly to the rectified

high-voltage Alternating Current (AC) input for

minimizing the number of external components. There is a

startup circuit block that regulates voltage from the Line pin

Zero Current Detect

To achieve critical conduction mode, MOSFET

conduction is always initiated by sensing a zero current

signal from the Zero Current Detect (ZCD) pin. The ZCD

pin indirectly monitors the inductor current by sensing the

auxiliary winding voltage. When the voltage falls below a

threshold of 1.0V, the comparator resets the RS latch to turn

the MOSFET on. There is 200 mV of hysteresis built into the

comparator for noise immunity and to prevent false tripping.

There are 10 V and 0.7 V clamps in the ZCD pin for

protection. An external resistor is recommended to limit the

input current to 2 mA to protect the clamps.

to the V

pin in an abnormal situation. In normal

CC

conditions, the auxiliary winding powers up the V and

CC

this startup circuit is opened and saves approximate 0.7 W

of power compared to the resistor bootstrapped circuits.

In normal operation, the auxiliary winding powers up the

V

CC

voltage. This voltage is a constant value between the

UVLO limits (7.6 V and 15 V). It is further regulated to a

constant 5 V reference voltage V for the internal circuitry

ref

usage. As long as the V voltage is between 7.6 V and

CC

15 V, it means the auxiliary winding can provide voltage as

in normal condition. The device recognizes that there is no

fault in the circuit and the device remains in the normal

operation status.

Watchdog Timer

A watchdog timer block is added to the device to start or

restart the Drive output when something goes wrong in the

ZCD. When the inductor current reaches zero for longer than

approximate 410 ms, the timer reset the RS latch and that

turns the MOSFET on.

However, when the auxiliary winding cannot power up

V

CC

, the V voltage will reach its UVLO limit. The device

CC

recognizes that it is an abnormal situation (such as startup or

output short-circuited). The V voltage is not constant in

CC

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7

MC33364

Current Sense and Feedback Regulation

Frequency Clamp Options

Current-mode control is implemented with the Current

Sense (CS) pin and Feedback (FB) pin. The FB pin is

internally pulled up with a 5 kOhm resistor from the 5 V

The drawback of critical conduction mode is variable

switching frequency. The switching frequency can increase

dramatically to hundreds of kHz when the output current is

too low or vanishes. It is a big problem when EMI above

150 kHz is concerned. Frequency Clamp (FC) is an optional

feature in the device to limit the upper switching frequency

to nominal 126 kHz by inserting a minimum off-time

V . There is a resistor divider circuit and a 0.1 V offset in

ref

this functional block. The following equation describes the

relation between the voltages of the FB and CS pins, V

FB

and V respectively.

CS

(t

). When a minimum off-time is inserted, the

off(min)

V

+ V ń4 * 0.1 V

FB

CS(max)

maximum frequency (f ) limit is set.

max

When the output is short circuited, there is no feedback

signal from the opto coupler and the FB pin is opened. It

gives V = 5 V and the maximum voltage of the CS pin is

1

) t

f

+

max

t

on(min)

off(min)

FB

The SMPS is forced to operate in DCM when the

maximum frequency is reached. The minimum off-time is

immediately counted after the driving signal goes low. If the

ZCD signal comes within this minimum off-time, the ZCD

information is ignored until the minimum off-time expires.

The next ZCD signal starts the MOSFET conduction.

There are three available FC options: MC33364D -

adjustable minimum off-time by external resistor,

MC33364D1 - 6.9 us fixed minimum off-time, and

MC33364D2 - no minimum off-time (FC disable).

The MC33364D has a FC pin, which can vary the

minimum off-time (or the maximum frequency) externally

in Figure 11. If the FC pin is opened, the minimum off-time

is fixed at 6.9 us. If the FC pin is grounded, the clamp is

disabled, and the SMPS will always operate in critical mode.

It is generally not recommended to sink or source more than

80 uA from the FC pin because high currents may cause

unstable operation.

1.15 V. When the voltage exceeds 1.15 V, the current sense

comparator turns on and terminates the MOSFET

conduction. It stops current flowing through the sense

resistor (R

) and hence the sense resistor limits the

Sense

maximum MOSFET drain current by the following

equation.

Maximum Drain Current + 1.15ńR

sense

When the output voltage is too high, the FB pin voltage is

pulled down by the opto coupler current and the duty ratio

is reduced. The output voltage is then regulated.

There is a Leading Edge Blanking (LEB) circuit with

250 ns propagation delay to prevent false triggering due to

parasitics in the CS pin. It makes a minimum on-time of the

MOSFET (t

).

on(min)

Thermal Shutdown

There is a thermal shutdown block to prevent overheating

condition and protect the device from overheating. When

temperature is over 180_C, the Drive output and startup

circuit block are disable. The device resumes operation

when temperature falls below 130_C.

Vref

FC

Gate Drive Output

FC

GND

The IC contains a CMOS output driver specifically

designed for direct drive of power MOSFET. The Drive

Output typical rise and fall times are 50 ns with a 1.0 nF

load. Unbalanced Source and Sink eliminates the need for an

external resistor between the device Drive output and the

Gate of the external MOSFET. Additional internal circuitry

has been added to keep the Drive Output in a sinking mode

whenever the UVLO is active. This characteristic eliminates

the need for an external gate pull-down resistor.

Increase toff

Decrease toff

FC

GND

toff = 6.9us

toff = 0us

(FC disable)

Figure 11. Frequency Clamp Setting

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8

MC33364

APPLICATION INFORMATION

Design Example

startup switch is turned off by the undervoltage and the

overvoltage control circuit. Because the power supply can

be shorted on the output, causing the auxiliary voltage to be

zero, the MC33364 will periodically start its startup block.

This mode is named “hiccup mode”. During this mode the

temperature of the chip rises but remains protected by the

thermal shutdown block. During the power supply’s normal

operation, the high voltage internal MOSFET is turned off,

preventing wasted power, and thereby, allowing greater

circuit efficiency.

Design an off-line Flyback converter according to the

following requirements:

Output Power:

Output:

12 W

6.0 V @ 2 Amperes

Input voltage range: 90 Vac - 270 Vac, 50/60 Hz

The operation for the circuit shown in Figure 12 is as

follows: the rectifier bridge D1-D4 and the capacitor C1

convert the ac line voltage to dc. This voltage supplies the

primary winding of the transformer T1 and the startup

circuit in U1 through the line pin. The primary current loop

is closed by the transformer’s primary winding, the TMOS

switch Q1 and the current sense resistor R7. The resistors

R5, R6, diode D6 and capacitor C4 create a snubber

clamping network that protects Q1 from spikes on the

primary winding. The network consisting of capacitor C3,

Since a bridge rectifier is used, the resulting minimum and

maximum dc input voltages can be calculated:

Ǹ

_{ac +}ǒ ₂Ǔ_{(90 Vac + 127 V}

)

V

dc + 2xV

in(min)

Ǹ

_{ac +}ǒ ₂Ǔ_{(270 Vac + 382 V}

)

V

dc + 2xV

in(max)

diode D5 and resistor R1 provides a V supply voltage for

U1 from the auxiliary winding of the transformer. The

CC

The maximum average input current is:

P

out

12 W

0.8 127 V

resistor R1 makes V more stable and resistant to noise.

CC

I

+

+ 0.118 A

in

(

)

nV

The resistor R2 reduces the current flow through the internal

clamping and protection zener diode of the Zero Crossing

Detector (ZCD) within U1. C3 is the decoupling capacitor

of the supply voltage. The resistor R3 can provide additional

bias current for the optoisolator’s transistor. The diode D8

and the capacitor C5 rectify and filter the output voltage. The

TL431, a programmable voltage reference, drives the

primary side of the optoisolator to provide isolated feedback

to the MC33364. The resistor divider consisting of R10 and

R11 program the voltage of the TL431. The resistor R9 and

the capacitors C7 and C8 provide frequency compensation

of the feedback loop. Resistor R8 provides a current limit for

the opto coupler and the TL431.

in(min)

where n = estimated circuit efficiency.

A TMOS switch with 600 V avalanche breakdown

voltage is used. The voltage on the switch’s drain consists of

the input voltage and the flyback voltage of the

transformer’s primary winding. There is a ringing on the

rising edge’s top of the flyback voltage due to the leakage

inductance of the transformer. This ringing is clamped by the

RCD network. Design this clamped wave for an amplitude

of 50 V below the avalanche breakdown of the TMOS

device. Add another 50 V to allow a safety margin for the

MOSFET. Then a suitable value of the flyback voltage may

be calculated:

Since the critical conduction mode converter is a variable

frequency system, the MC33364 has a built-in special block

to reduce switching frequency in the no load condition. This

block is named the ”frequency clamp” block. MC33364

used in the design example has an internal frequency clamp

set to 126 kHz. However, optional versions with a disabled

or variable frequency clamp are available. The frequency

clamp works as follows: the clamp controls the part of the

switching cycle when the MOSFET switch is turned off. If

this ”off-time” (determined by the reset time of the

transformer’s core) is too short, then the frequency clamp

does not allow the switch to turn-on again until the defined

frequency clamp time is reached (i.e., the frequency clamp

will insert a dead time).

V

+ V

* V

* 100 V +

flbk

TMOS

in(max)

600 V * 382 V * 100 V + 118 V

Since this value is very close to the V

, set:

in(min)

V

+ V

+ 127 V

flbk

in(min)

The V

value of the duty cycle is given by:

flbk

V

flbk

127 V

127 V ) 127 V

ēmax +

+

+ 0.5

[

]

V

) V

flbk

in(min)

The maximum input primary peak current:

2 I

(

)

2.0 0.118 A

in

I

+

+ 0.472 A

ppk

ēmax

0.5

There are several advantages of the MC33364’s startup

circuit. The startup circuit includes a special high voltage

switch that controls the path between the rectified line

Choose the desired minimum frequency f of operation

min

to be 70 kHz.

voltage and the V

supply capacitor to charge that

CC

After reviewing the core sizing information provided by

a core manufacturer, a EE core of size about 20 mm was

chosen. Siemens’ N67 magnetic material is used, which

corresponds to a Philips 3C85 or TDK PC40 material.

capacitor by a limited current when the power is applied to

the input. After a few switching cycles the IC is supplied

from the transformer’s auxiliary winding. After V

CC

reaches the undervoltage lockout threshold value, the

http://onsemi.com

9

MC33364

t

(I )

off in

The primary inductance value is given by:

(5 m sec)(0.118 A)

50 V

C1 +

+

+ 11.8 mF

V

ēmax V

(

)

ripple

in(min)

0.5 127 V

)(

L

+

+ 1.92 mH

p

(

)

0.472 A 70 kHz

ǒ

_minǓ

ǒ_IppkǓ _f

where the minimum ripple frequency is 2 times the 50 Hz

line frequency and t , the discharge time of C1 during the

off

The manufacturer recommends for that magnetic core a

maximum operating flux density of:

haversine cycle, is assumed to be half the cycle period.

Because we have a variable frequency system, all the

calculations for the value of the output filter capacitors will

be done at the lowest frequency, since the ripple voltage will

be greatest at this frequency. When selecting the output

capacitor select a capacitor with low ESR to minimize ripple

from the current ripple. The approximate equation for the

output capacitance value is given by:

B

+ 0.2 T

max

The cross-sectional area A of the EF20 core is:

c

2

A

+ 33.5 mm

c

The operating flux density is given by:

L I

p

ppk

B

+

I

max

out

2 A

N A

p c

C5 +

+

+ 286 mF

(f

)(V

)

(70 kHz)(0.1 V)

min rip

From this equation the number of turns of the primary

Determining the value of the current sense resistor (R7),

one uses the peak current in the predesign consideration.

Since within the IC there is a limitation of the voltage for the

current sensing, which is set to 1.2 V, the design of the

current sense resistor is simply given by:

winding can be derived:

L I

p

ppk

A

n

+

p

B

max c

The A factor is determined by:

L

2

V

cs

1.2 V

0.472 A

ǒ

Ǔ

A

L

B

R7 +

+

+ 2.54 W [ 2.2 W

L

p

max c

p

I

A

+

ppk

L

2

n p

_Lǒ_IǓ²

The error amplifier function is provided by a TL431 on the

secondary, connected to the primary side via an optoisolator,

the MOC8102.

ƪ _pƫ

ppk

2

ǒ

^Ǔǒ

Ǔ

0.2 T 33.5 E- 6 m

The voltage of the optoisolator collector node sets the

peak current flowing through the power switch during each

cycle. This pin will be connected to the feedback pin of the

MC33364, which will directly set the peak current.

Starting on the secondary side of the power supply, assign

the sense current through the voltage-sensing resistor

divider to be approximately 0.25 mA. One can immediately

calculate the value of the lower and upper resistor:

+

+ 105 nH

2

ǒ

Ǔ

(

)

.00192 H 0.472 A

From the manufacturer‘s catalogue recommendation the

core with an A of 100 nH is selected. The desired number

of turns of the primary winding is:

L

1ń2

L

(

)

p

0.00192 H

₊ƪ

ƫ

n

+

ǒ Ǔ

+ 139 turns

p

(

)

100 nH

A

L

V

(TL431)

ref

2.5 V

0.25 mA

R

+ R11 +

+ R10 +

+

+ 10 k

lower

upper

I

The number of turns needed by the 6.0 V secondary is

(assuming a Schottky rectifier is used):

div

V

* V (TL431)

out

ref

ǒ

Ǔ

p

ǒ_V_s_)VǓ _{1–ēmax n}

R

fwd

I

n +

div

s

6.0 V * 2.5V

0.25 mA

_ēmaxǒ

V

Ǔ

_in(min)ƫ

ƪ

+

+ 14 k

The value of the resistor that would provide the bias

ǒ

Ǔǒ

Ǔ

6.0 V) 0.3 V 1* 0.5 139

+

+ 7 turns

current through the optoisolator and the TL431 is set by the

minimum operating current requirements of the TL431.

This current is minimum 1.0 mA. Assign the maximum

current through the branch to be 5 mA. That makes the bias

resistor value equal to:

ƪ

ǒ

Ǔƫ

0.5 127 V

The auxiliary winding to power the control IC is 16 V and

its number of turns is given by:

(V

) V

)(1 * ēmax)n

aux

p

fwd

naux +

V

* [V (TL431) ) V

]

out

ref

LED

ƪ

_in(min))ƫ

(16 V ) 0.9 V)(1 * 0.5)139

ēmax(V

R

+ R

+

bias

S

I

LED

6.0 V * [2.5V ) 1.4V]

+

+ 19 turns

+ 420 W [ 430 W

[0.5(127 V)]

5.0 mA

The approximate value of rectifier capacitance needed is:

http://onsemi.com

10

MC33364

The MOC8102 has a typical current transfer ratio (CTR)

The gain exhibited by the open loop power supply at the

high input voltage will be:

of 100% with 25% tolerance. When the TL431 is full-on,

5 mA will be drawn from the transistor within the

MOC8102. The transistor should be in saturated state at that

time, so its collector resistor must be

ǒ_{Vin max}_outǓ²

2

* V

Ns

(

)

382 V * 6.0 V (7)

A +

_)(Np)Ǔ ⁺

(382 V)(1.2 V)(139)

ǒ

(V

)(V

error

V

* V

in max

sat

ref

I

5.0 V * 0.3 V

R

+

+ 940 W

collector

5.0 mA

+ 15.53 + 23.82 dB

LED

The

maximum

recommended

bandwidth

is

Since a resistor of 5.0 k is internally connected from the

reference voltage to the feedback pin of the MC33364, the

external resistor can have a higher value

approximately:

fs min

5

70 kHz

5

f

+

+ 14 kHz

c

(R )(R

)

(5.0 k)(940)

5.0 k * 940

int collector

The gain needed by the error amplifier to achieve this

bandwidth is calculated at the rated load because that yields

the bandwidth condition, which is:

R

+ R3 +

+

ext

(R ) * (R

int

)

collector

+ 1157 W [ 1200 W

f

This completes the design of the voltage feedback circuit.

In no load condition there is only a current flowing

through the optoisolator diode and the voltage sense divider

on the secondary side.

c

14 kHz

177

_{* A + 20 log}ǒ

Ǔ_{* 23.82 dB}

Gc + 20 log

ǒ Ǔ

f

ph

+ 14.14 dB

The gain in absolute terms is:

The load at that condition is given by:

(Gcń20)

(14.14ń20)

A

+ 10

+ 51

V

c

out

R

+

noload

(I

) I

)

Now the compensation circuit elements can be calculated.

The output resistance of the voltage sense divider is given by

the parallel combination of resistors in the divider:

LED

div

6.0 V

(5.0 mA ) 0.25 mA)

+

+ 1143 W

The output filter pole at no load is:

R

+ R

|| R

+ 10 k || 14 k + 5833 W

upper

in

lower

1

f

+

R9 + (Ac) (R ) + 29.75 k [ 30 k

pn

( 2p R

C

)

in

out

noload

1

+

+ 0.46 Hz

ƫ ^{+ 382 pF [ 390 pF}

C8 +

(2p)(1143)(300 mF)

ƪ

2p (A ) (R ) (f )

c

in

In heavy load condition the I

and I is negligible. The

div

LED

The compensation zero must be placed at or below the

light load filter pole:

heavy load resistance is given by:

V

out

6.0 V

2.0 A

R

+

+ 3.0 W

1

heavy

C7 +

₎ƫ ^{+ 11.63 mF [ 10 mF}

I

ƪ

2p (R9) (f

pn

The output filter pole at heavy load of this output is

1

f

+

+ 177 Hz

pn

(2p R

C

)

(2p)(3)(300 mF)

out

heavy

http://onsemi.com

11

MC33364

1N4006

D1

EMI

Filter

85 to

265 VAC

D2

+

C1

10mF

400V

D3

D4

T1

D5 1N4934

R1 56

D8

MBR340

6.0 V

2.0 A

C5

300mF

Line

R5

47 K

Vcc UVLO

Vcc

Ref UVLO

C4

1mF

Reference

R6

47 K

StartUp

C3

20mF

15 / 7.6

Vref

Buffer

4.7

D6

MUR160

Restart

Delay

ZCD

R2

22 k

10V

5k

1.2/1.0

Watchdog

Timer

MC33364D

Vcc

VREF

FB

R

Q1

MTD1N60

C10

0.1mF

GATE

R

S

Q

R4 470

(optional)

Current Sense

1.25V

R7

2.2

Thermal

shutdown

PGND

CS

45k

15k

R8

430

Frequency

clamp

2V

R10

14 k

0.1V

LEB

10V

4k

5

4

1

2

FC

AGND

U3

MOC8102

C7

10 nF

R9

39 k

C8

330 pF

3

1

2

U2

TL431

R11

10 k

Figure 12. Circuit in the Design Example

http://onsemi.com

12

MC33364

The described critical conduction mode flyback converter has the following performance and maximum ratings:

12W

Output power

Output

Input voltage range

12V @ 1Amp max

90VAC − 270VAC

J1

1

D1

S380

Line

J2

J3

D4

2

T1

9

7

4

10uF

C4

400V

1

10uF

1

220

R1

2

1

MBRD360

+Vout

D2

1N4148

Gnd

C6

300uF

R3 47k

R6

2k7

R7

820

R8

18k

R4

47k

R2

100k

C5 1nF

2

D3

MURS160T3

U1

Q1

MTD1N60

6

1

GATE

MC33364

GND

C9

5

100nF

2

CS

1

R5

2.2

U2

TL431

U3

MOC8102

1

2

J4

1

5

R9

4k7

0.1uF

4

−Vout

Figure 13. Critical Conduction Mode Flyback Converter

Conditions

CONVERTER TEST DATA

Test

Line Regulation

Load

Results

V

in

V

in

V

in

V

in

V

in

V

in

V

in

V

in

V

in

= 120VAC to 240VAC, I = 0.8A

DV = 50mV

DV = 40mV

DV = 290mV

DV = 24mV

h = 78.0%

h = 79.4%

Pf = 0.491

Pf = 0.505

out

= 120VAC, I = 0.2A to 0.8A

out

= 240VAC, I = 0.2A to 0.8A

out

Output Ripple

Efficiency

= 120VAC, I = 0.8A

out

= 240VAC, I = 0.8A

out

= 120VAC, I = 0.8A

out

= 240VAC, I = 0.8A

out

Power Factor

= 120VAC, I = 0.8A

out

= 240VAC, I = 0.8A

out

Vout

Iout

Vout

Iout

Ch1: 2.0V/div

Ch2: 200mA/div

2.0 msec/div

Ch1: 2.0V/div

Ch2: 200mV/div

2.0 msec/div

Figure 14. Load Regulation 120V

Figure 15. Load Regulation 240V

http://onsemi.com

13

MC33364

J2

Output 12 V @ 0.8 Amp max

Input Voltage Range 90 − 270 Vac, 50/60 Hz

1

2

R13

22 k

R12

82 k

R11

10 k

5

6

V

GND

CMP

4

3

S

CSB

U2

MC33341

R10

0.25

5.1 V

CTA

CSA

2

1

7

8

V

C7

33 nF

CC

DO

D8

B2X84C5V1LT1

R8

4.7 k

R9

100

C5

100 mF

C6

1.0 mF

D7

1N4148

D6

MURS320T3

R7

100

2

5

1

4

9

7

T1

5

4

3

2

Q1

MTD1N60E

R4

2.2

R6

47 k

D5

MURS

160T3

R5

47 k

U3

MOC8102

D3

1N4148

R1

220

R3

22 k

C2

20 mF

6

2

CS

Gate

1

ZCD

FB

3

4

U1

MC33364D1

7

8

V

CC

C3

Line

V

ref

0.1 mF

GND

5

C1

10 mF

400 V

D1 B250R

F1

T 0.2 A

T1 = 139 Turns #28 Awg, primary winding 2 − 3

7 Turns, Bifilar 2 x #26 Awg, output winding 9 − 7

19 Turns #28 Awg, auxiliary winding 4 − 5 on Philips

EF20−3C85 core gap for a primary inductor of 1.92 mH.

1 2

J1

Line

Figure 16. Universal Input Battery Charger

http://onsemi.com

14

MC33364

PACKAGE DIMENSIONS

(SO-8)

D1, D2 SUFFIX

PLASTIC PACKAGE

CASE 751-07

ISSUE AA

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

-X-

A

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.

8

5

4

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN

EXCESS OF THE D DIMENSION AT MAXIMUM

MATERIAL CONDITION.

S

M

B

0.25 (0.010)

Y

1

K

-Y-

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDAARD IS 751−07

G

MILLIMETERS

INCHES

DIM MIN

MAX

5.00

4.00

1.75

0.51

MIN

MAX

0.197

0.157

0.069

0.020

A

B

C

D

G

H

J

4.80

3.80

1.35

0.33

0.189

0.150

0.053

0.013

0.050 BSC

0.004

0.007

0.016

0

0.010

0.228

C

N X 45

_

SEATING

PLANE

-Z-

1.27 BSC

0.10 (0.004)

0.10

0.19

0.40

0

0.25

1.27

8

0.010

0.050

8

M

J

H

D

K

M

N

S

_

0.25

5.80

0.50

6.20

0.020

0.244

M

S

0.25 (0.010)

Z

Y

X

(SO-16)

D SUFFIX

PLASTIC PACKAGE

CASE 751K-01

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

-A-

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

16

9

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN

EXCESS OF THE D DIMENSION AT MAXIMUM

MATERIAL CONDITION.

_

M

-B-

P

F

1

8

MILLIMETERS

INCHES

MIN

0.368

G

DIM MIN

MAX

0.393

0.157

0.068

0.019

0.049

A

B

C

D

F

9.80

3.80

1.35

0.35

0.40

10.00

R ^{X 45}

_

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

C

G

J

1.27 BSC

0.050 BSC

SEATING

PLANE

-T-

0.19

0.10

0.25 0.008

0.25 0.004

0.009

14 X D

K

M

P

R

J

K

0

5.80

0.25

7

0

7

_

M

S

0.25 (0.010)

T

A

B

6.20 0.229

0.50 0.010

0.244

0.019

http://onsemi.com

15

MC33364

The product described herein (MC33364), may be covered by one or more of the following U.S. patents: 5,418,410; 5,862,045;

5,973,528. There may be other patents pending.

GreenLine is a trademark of Motorola, Inc.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make

changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all

liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment:

JAPAN: ON Semiconductor, Japan Customer Focus Center

2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051

Phone: 81-3-5773-3850

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada

Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local

Sales Representative.

N. American Technical Support: 800-282-9855 Toll Free USA/Canada

MC33364/D

http://onsemi.com

16


型号：	MC33364DR2
厂家：	ONSEMI
描述：	Critical Conduction GreenLine SMPS Controller 临界导电绿线SMPS控制器稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件：	总16页 (文件大小：174K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC33364DR2 [ONSEMI]

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