MC33365_06 [ONSEMI]
High Voltage Switching Regulator; 高压开关稳压器
| 型号： | MC33365_06 |
| 厂家： | 
ONSEMI |
| 描述： | High Voltage Switching Regulator |
| 文件： | 总11页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC33365
High Voltage Switching
Regulator
The MC33365 is a monolithic high voltage switching regulator that
is specifically designed to operate from a rectified 240 Vac line source.
This integrated circuit features an on−chip 700 V/1.0 A SENSEFETt
power switch, 450 V active off−line startup FET, duty cycle controlled
oscillator, current limiting comparator with a programmable threshold
and leading edge blanking, latching pulse width modulator for double
pulse suppression, high gain error amplifier, and a trimmed internal
bandgap reference. Protective features include cycle−by−cycle current
limiting, input undervoltage lockout with hysteresis, bulk capacitor
voltage sensing, and thermal shutdown. This device is available in a
16−lead dual−in−line package.
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MARKING
DIAGRAM
16
PDIP−16
P SUFFIX
CASE 648E
MC33365P
AWLYYWW
16
• On−Chip 700 V, 1.0 A SENSEFET Power Switch
1
1
• Rectified 240 Vac Line Source Operation
• On−Chip 450 V Active Off−Line Startup FET
• Latching PWM for Double Pulse Suppression
• Cycle−By−Cycle Current Limiting
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
• Input Undervoltage Lockout with Hysteresis
• Bulk Capacitor Voltage Comparator
• Trimmed Internal Bandgap Reference
• Internal Thermal Shutdown
PIN CONNECTIONS
Power Switch
Drain
Startup Input
1
16
V
3
4
5
6
7
8
CC
AC Input
13
12
Startup Input
1
Gnd
Gnd
Regulator
Output
Startup
Mirror
R
11 BOK
T
V
CC
Reg
3
Voltage Feedback
Input
Compensation
8
C
DC Output
10
9
T
UVLO
BOK
Regulator Output
6
BOK
R
C
11
16
T
(Top View)
PWM Latch
Osc
T
Power Switch
Drain
7
Driver
S
Q
R
ORDERING INFORMATION
PWM
Device
MC33365P
Package
Shipping
25 Units/Rail
LEB
I
pk
PDIP−16
Compensation
9
Thermal
10
EA
Voltage
Feedback
Input
Gnd 4, 5, 12, 13
Figure 1. Simplified Application
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006− Rev. 4
MC33365/D
MC33365
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Switch (Pin 16)
Drain Voltage
Drain Current
V
I
700
1.0
V
A
DS
DS
Startup Input Voltage (Pin 1, Note 1)
Pin 3 = Gnd
Pin 3 ≤ 1000 μF to ground
V
in
V
400
500
Power Supply Voltage (Pin 3)
V
40
V
V
CC
Input Voltage Range
V
−1.0 to V
IR
reg
Voltage Feedback Input (Pin 10)
Compensation (Pin 9)
Bulk OK Input (Pin 11)
R
T
C
T
(Pin 6)
(Pin 7)
Thermal Characteristics
°C/W
P Suffix, Dual−In−Line Case 648E
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
R
R
80
15
θ
JA
θ
JC
Operating Junction Temperature
Storage Temperature
T
−25 to +125
−55 to +150
°C
°C
J
T
stg
NOTE: ESD data available upon request.
ELECTRICAL CHARACTERISTICS (V
= 20 V, R = 10 k, C = 390 pF, C
= 1.0 μF, for typical values T = 25°C,
Pin 8 J
CC
T
T
for min/max values T is the operating junction temperature range that applies, unless otherwise noted.)
J
Characteristic
Symbol
Min
Typ
Max
Unit
REGULATOR (Pin 8)
Output Voltage (I = 0 mA, T = 25°C)
V
reg
5.5
−
6.5
30
44
−
7.5
500
200
8.0
V
mV
mV
V
O
J
Line Regulation (V = 20 V to 40 V)
Reg
line
CC
Load Regulation (I = 0 mA to 10 mA)
Reg
−
O
load
Total Output Variation over Line, Load, and Temperature
V
reg
5.3
OSCILLATOR (Pin 7)
Frequency
f
kHz
OSC
C
= 390 pF
T
T = 25°C (V = 20 V)
260
255
285
−
310
315
J
CC
T = T
to T
(V = 20 V to 40 V)
CC
J
low
high
C
= 2.0 nF
T
T = 25°C (V = 20 V)
60
59
67.5
−
75
76
J
CC
T = T
to T
(V = 20 V to 40 V)
CC
J
low
high
Frequency Change with Voltage (V = 20 V to 40 V)
Δf
OSC
/ΔV
−
0.1
2.0
kHz
CC
ERROR AMPLIFIER (Pins 9, 10)
Voltage Feedback Input Threshold
V
2.52
−
2.6
0.6
20
2.68
5.0
V
mV
nA
dB
MHz
V
FB
Line Regulation (V = 20 V to 40 V, T = 25°C)
Reg
I
CC
J
line
Input Bias Current (V = 2.6 V, T = 0 − 125°C)
−
500
94
FB
J
IB
Open Loop Voltage Gain (T = 25°C)
A
VOL
70
82
J
Gain Bandwidth Product (f = 100 kHz, T = 25°C)
GBW
0.85
1.0
1.15
J
Output Voltage Swing
High State (I
= 100 μA, V < 2.0 V)
V
OH
4.0
−
5.3
0.2
−
0.35
Source
FB
Low State (I
= 100 μA, V > 3.0 V)
V
OL
Sink
FB
1. Maximum power dissipation limits must be observed.
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MC33365
ELECTRICAL CHARACTERISTICS (continued) (V
= 20 V, R = 10 k, C = 390 pF, C
= 1.0 μF, for typical values
Pin 8
CC
T
T
T = 25°C, for min/max values T is the operating junction temperature range that applies, unless otherwise noted.)
J
J
Characteristic
Symbol
Min
Typ
Max
Unit
BULK OK (Pin 11)
Input Threshold Voltage
V
1.18
−
1.25
100
−
1.32
500
53
V
th
Input Bias Current (V < V , T = 0 − 125°C)
I
IB
nA
μA
BK
th
J
Source Current (Turn on after V > V , T = 25°C − 125°C)
I
SC
39
BK
th
J
PWM COMPARATOR (Pins 7, 9)
Duty Cycle
Maximum (V = 0 V)
%
DC
DC
48
−
50
0
52
0
FB
(max)
Minimum (V = 2.7 V)
FB
(min)
POWER SWITCH (Pin 16)
Drain−Source On−State Resistance (I = 200 mA)
R
Ω
D
DS(on)
T = 25°C
T = −25°C to +125°C
J
−
−
15
−
17
39
J
Drain−Source Off−State Leakage Current
I
μA
D(off)
V
= 650 V
−
−
−
0.2
50
50
100
−
DS
Rise Time
t
ns
ns
r
Fall Time
t
−
f
OVERCURRENT COMPARATOR (Pin 16)
Current Limit Threshold (R = 10 k)
I
lim
0.5
0.72
0.9
A
T
STARTUP CONTROL (Pin 1)
Peak Startup Current (V = 400 V) (Note 2)
I
mA
in
start
V
CC
V
CC
= 0 V
−
−
2.0
2.0
4.0
4.0
= (V
− 0.2 V)
th(on)
Off−State Leakage Current (V = 50 V, V = 20 V)
I
−
40
200
μA
in
CC
D(off)
UNDERVOLTAGE LOCKOUT (Pin 3)
Startup Threshold (V Increasing)
V
11
15.2
9.5
18
V
V
CC
th(on)
Minimum Operating Voltage After Turn−On
V
7.5
11.5
CC(min)
TOTAL DEVICE (Pin 3)
Power Supply Current
I
mA
CC
Startup (V = 10 V, Pin 1 Open)
Operating
−
−
0.25
3.2
0.5
5.0
CC
2. The device can only guarantee to start up at high temperature below +115°C.
1.0 M
500 k
1.0
0.8
C
C
= 100 pF
= 200 pF
T
V
= 20 V
CC
V
= 20 V
CC
C = 1.0 μF
T = 25°C
A
T
T = 25°C
A
T
0.6
C
C
= 500 pF
= 1.0 nF
200 k
100 k
50 k
T
0.4
0.3
T
C
T
= 2.0 nF
0.2
C
C
= 5.0 nF
= 10 nF
0.15
T
20 k
10 k
Inductor supply voltage and inductance value are
adjusted so that I turn−off is achieved at 5.0 μs.
pk
T
0.1
7.0
7.0
10
15
20
30
50
70
10
15
20
30
40
50
70
R , TIMING RESISTOR (kΩ)
T
R , TIMING RESISTOR (kΩ)
T
Figure 3. Power Switch Peak Drain Current
versus Timing Resistor
Figure 2. Oscillator Frequency
versus Timing Resistor
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MC33365
0.8
0.5
70
V
= 20 V
C = 2.0 nF
R /R Ratio
T
Discharge Resistor
Pin 6 to Gnd
CC
D
V
= 20 V
CC
T
T = 25°C
A
T = 25°C
A
60
50
40
30
0.3
0.2
0.15
R /R Ratio
T
Charge Resistor
Pin 6 to V
C
0.1
reg
0.08
7.0
10
15
20
30
50
70
1.0
2.0
3.0
5.0
7.0
10
R , TIMING RESISTOR (kΩ)
T
TIMING RESISTOR RATIO
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor Ratio
Figure 4. Oscillator Charge/Discharge
Current versus Timing Resistor
100
0
0
−1.0
−ꢀ2.0
V
V
= 20 V
= 1.0 to 4.0 V
CC
Source Saturation
(Load to Ground)
V
ref
O
80
60
30
R = 5.0 MΩ
L
C = 2.0 pF
T = 25°C
A
Gain
L
60
Phase
40
20
90
2.0
1.0
120
Sink Saturation
(Load to V
V
= 20 V
CC
)
ref
T = 25°C
A
0
150
180
Gnd
−20
10
0
100
1.0 k
10 k
100 k
1.0 M
10 M
0
0.2
0.4
0.6
0.8
1.0
f, FREQUENCY (Hz)
I , OUTPUT LOAD CURRENT (mA)
O
Figure 6. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 7. Error Amp Output Saturation
Voltage versus Load Current
V
CC
A = −1.0
= 20 V
V
CC
A = −1.0
= 20 V
V
V
C = 10 pF
L
T = 25°C
A
C = 10 pF
L
T = 25°C
A
1.80 V
3.00 V
1.75 V
0.50 V
1.75 V
1.70 V
1.0 μs/DIV
1.0 μs/DIV
Figure 8. Error Amplifier Small Signal
Transient Response
Figure 9. Error Amplifier Large Signal
Transient Response
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MC33365
0
2.0
V
= 400 V
Pin 1
V
CC
R = 10 k
= 20 V
T = 25°C
A
T
C
= 1.0 μF
Pin 8
−20
T = 25°C
A
−40
−60
−80
1.0
Pulse tested with an on−time of 20 μs to 300 μs
at < 1.0% duty cycle. The on−time is adjusted at
Pin 1 for a maximum peak current out of Pin 3.
0
0
4.0
8.0
12
16
20
0
2.0
4.0
V , POWER SUPPLY VOLTAGE (V)
CC
6.0
8.0
10
12
14
I , REGULATOR SOURCE CURRENT (mA)
reg
Figure 11. Peak Startup Current
versus Power Supply Voltage
Figure 10. Regulator Output Voltage
Change versus Source Current
32
24
16
8.0
0
160
I
D
= 200 mA
V
= 20 V
CC
T = 25°C
A
120
80
40
0
Pulse tested at 5.0 ms with < 1.0% duty cycle
so that T is as close to T as possible.
J
A
C
OSS
measured at 1.0 MHz with 50 mVpp.
−50
−25
0
25
50
75
100
125
150
1.0
10
100
1000
T , AMBIENT TEMPERATURE (°C)
A
V
DS
, DRAIN−SOURCE VOLTAGE (V)
Figure 12. Power Switch Drain−Source
On−Resistance versus Temperature
Figure 13. Power Switch
Drain−Source Capacitance versus Voltage
3.2
100
C = 390 pF
T
L = 12.7 mm of 2.0 oz. copper.
Refer to Figure 15.
C = 2.0 nF
T
2.4
1.6
0.8
0
10
R = 10 k
T
Pin 1 = Open
Pin 4, 5, 10, 11,
12, 13 = Gnd
T = 25°C
A
1.0
0.01
0
10
20
, SUPPLY VOLTAGE (V)
30
40
0.1
1.0
10
100
V
CC
t, TIME (s)
Figure 14. Supply Current versus Supply Voltage
Figure 15. P Suffix Transient Thermal
Resistance
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MC33365
100
80
5.0
4.0
Printed circuit board heatsink example
2.0 oz
Copper
L
R
L
θ
JA
3.0 mm
60
40
20
3.0
2.0
1.0
0
Graphs represent symmetrical layout
P
D(max)
for T = 70°C
A
0
0
10
20
30
40
50
L, LENGTH OF COPPER (mm)
Figure 16. P Suffix (DIP−16) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
PIN FUNCTION DESCRIPTION
Description
Pin
Function
1
Startup Input
This pin connects directly to the rectified ac line voltage source. Internally Pin 1 is tied to the
drain of a high voltage startup MOSFET. During startup, the MOSFET supplies internal bias, and
charges an external capacitor that connects from the VCC pin to ground.
2
3
−
This pin has been omitted for increased spacing between the rectified ac line voltage on Pin 1
and the VCC potential on Pin 3.
V
CC
This is the positive supply voltage input. During startup, power is supplied to this input from
Pin 1. When V reaches the UVLO upper threshold, the startup MOSFET turns off and power is
CC
supplied from an auxiliary transformer winding.
4, 5, 12, 13
Gnd
RT
These pins are the control circuit grounds. They are part of the IC lead frame and provide a
thermal path from the die to the printed circuit board.
6
7
Resistor R connects from this pin to ground. The value selected will program the Current Limit
T
Comparator threshold and affect the Oscillator frequency.
CT
Capacitor C connects from this pin to ground. The value selected, in conjunction with resistor
T
R , programs the Oscillator frequency.
T
8
Regulator Output
Compensation
This 6.5 V output is available for biasing external circuitry. It requires an external bypass
capacitor of at least 1.0 μF for stability.
9
This pin is the Error Amplifier output and is made available for loop compensation. It can be used
as an input to directly control the PWM Comparator.
10
Voltage Feedback
Input
This is the inverting input of the Error Amplifier. It has a 2.6 V threshold and normally connects
through a resistor divider to the converter output, or to a voltage that represents the converter
output.
11
BOK
This is the non−inverting input of the bulk capacitor voltage comparator. It has an input threshold
voltage of 1.25V. This pin is connected through a resistor divider to the bulk capacitor line
voltage.
14, 15
16
−
These pins have been omitted for increased spacing between the high voltages present on the
Power Switch Drain, and the ground potential on Pins 12 and 13.
Power Switch Drain This pin is designed to directly drive the converter transformer and is capable of switching a
maximum of 700 V and 1.0 A.
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MC33365
AC Input
Startup Input
1
Startup
Control
Current
Mirror
V
Regulator Output
CC
Band Gap
Regulator
6.5 V
8
3
UVLO
DC Output
I
2.25 I
14.5 V/
9.5 V
6
BOK
11
R
T
4 I
1.25 V
Oscillator
16
C
7
T
PWM Latch
Power Switch
Drain
Driver
S
Q
R
PWM
Comparator
Leading Edge
Blanking
8.1
Thermal
Shutdown
Compensation
9
Current Limit
Comparator
405
2.6 V
Error
Amplifier
270 μA
10
Voltage
Feedback Input
Gnd 4, 5, 12, 13
Figure 17. Representative Block Diagram
2.6 V
Capacitor C
T
0.6 V
Compensation
Oscillator
Output
PWM
Comparator
Output
PWM Latch
Q Output
Current Limit
Propagation
Delay
Power Switch
Gate Drive
Current
Limit
Threshold
Leading Edge
Blanking Input
(Power Switch
Drain Current)
Normal PWM Operating Range
Output Overload
Figure 18. Timing Diagram
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MC33365
OPERATING DESCRIPTION
Introduction
The formula for the charge/discharge current along with
the oscillator frequency are given below. The frequency
The MC33365 represents a new higher level of integration
by providing all the active high voltage power, control, and
protection circuitry required for implementation of a
flyback or forward converter on a single monolithic chip.
This device is designed for direct operation from a rectified
240 Vac line source and requires a minimum number of
external components to implement a complete converter. A
description of each of the functional blocks is given below,
and the representative block and timing diagrams are shown
in Figures 17 and 18.
formula is a first order approximation and is accurate for C
T
values greater than 500 pF. For smaller values of C , refer to
T
Figure 2. Note that resistor R also programs the Current
T
Limit Comparator threshold.
I
chgńdscg
4C
T
5.4
T
I
+
f [
chgńdscg
R
PWM Comparator and Latch
The pulse width modulator consists of a comparator with
the oscillator ramp voltage applied to the non−inverting
input, while the error amplifier output is applied into the
inverting input. The Oscillator applies a set pulse to the
Oscillator and Current Mirror
The oscillator frequency is controlled by the values
selected for the timing components R and C . Resistor RT
programs the oscillator charge/discharge current via the
T
T
PWM Latch while C is discharging, and upon reaching the
T
valley voltage, Power Switch conduction is initiated. When
Current Mirror 4 I output, Figure 4. Capacitor C is charged
T
C
T
charges to a voltage that exceeds the error amplifier
and discharged by an equal magnitude internal current
source and sink. This generates a symmetrical 50 percent
duty cycle waveform at Pin 7, with a peak and valley
threshold of 2.6 V and 0.6 V respectively. During the
discharge of CT, the oscillator generates an internal blanking
pulse that holds the inverting input of the AND gate Driver
high. This causes the Power Switch gate drive to be held in
a low state, thus producing a well controlled amount of
output deadtime. The amount of deadtime is relatively
constant with respect to the oscillator frequency when
operating below 1.0 MHz. The maximum Power Switch
duty cycle at Pin 16 can be modified from the internal 50%
limit by providing an additional charge or discharge current
output, the PWM Latch is reset, thus terminating Power
Switch conduction for the duration of the oscillator ramp−up
period. This PWM Comparator/Latch combination
prevents multiple output pulses during a given oscillator
clock cycle. The timing diagram shown in Figure 18
illustrates the Power Switch duty cycle behavior versus the
Compensation voltage.
Current Limit Comparator and Power Switch
The MC33365 uses cycle−by−cycle current limiting as a
means of protecting the output power switch from
overstress. Each on−cycle is treated as a separate situation.
Current limiting is implemented by monitoring the output
switch current buildup during conduction, and upon sensing
an overcurrent condition, immediately turning off the switch
for the duration of the oscillator ramp−up period.
path to C , Figure 19. In order to increase the maximum duty
T
cycle, a discharge current resistor RD is connected from
Pin 7 to ground. To decrease the maximum duty cycle, a
charge current resistor R is connected from Pin 7 to the
C
The Power Switch is constructed as a SENSEFET
allowing a virtually lossless method of monitoring the drain
current. It consists of a total of 1462 cells, of which 36 are
connected to a 8.1 Ω ground−referenced sense resistor. The
Current Sense Comparator detects if the voltage across the
sense resistor exceeds the reference level that is present at
the inverting input. If exceeded, the comparator quickly
resets the PWM Latch, thus protecting the Power Switch.
The current limit reference level is generated by the 2.25 I
output of the Current Mirror. This current causes a reference
voltage to appear across the 405 Ω resistor. This voltage
level, as well as the Oscillator charge/discharge current are
Regulator Output. Figure 5 shows an obtainable range of
maximum output duty cycle versus the ratio of either R or
C
R with respect to R .
D
T
Current
Mirror
Regulator Output
8
1.0
2.25 I
I
R
R
Current
Limit
Reference
C
D
6
R
T
both set by resistor R . Therefore when selecting the values
T
4 I
for R and C , R must be chosen first to set the Power
T
T
T
Oscillator
Switch peak drain current, while C is chosen second to set
T
Blanking
Pulse
C
7
T
the desired Oscillator frequency. A graph of the Power
Switch peak drain current versus R is shown in Figure 3
T
with the related formula below.
PWM
Comparator
R
− 1.077
T
+ 8.8 ǒ Ǔ
I
1000
pk
Figure 19. Maximum Duty Cycle Modification
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MC33365
The Power Switch is designed to directly drive the converter
V
BULK
transformer and is capable of switching a maximum of
700 V and 1.0 A. Proper device voltage snubbing and
heatsinking are required for reliable operation.
V
ref
A Leading Edge Blanking circuit was placed in the current
sensing signal path. This circuit prevents a premature reset
of the PWM Latch. The premature reset is generated each
time the Power Switch is driven into conduction. It appears
as a narrow voltage spike across the current sense resistor,
and is due to the MOSFET gate to source capacitance,
transformer interwinding capacitance, and output rectifier
recovery time. The Leading Edge Blanking circuit has a
dynamic behavior in that it masks the current signal until the
Power Switch turn−on transition is completed. The current
limit propagation delay time is typically 262 ns. This time is
measured from when an overcurrent appears at the Power
Switch drain, to the beginning of turn−off.
R
R
Upper
BOK
11
50 mA
1.25 V
Protection Logic
Lower
Figure 20. Bulk OK Functional Operation
Undervoltage Lockout
An Undervoltage Lockout comparator has been
incorporated to guarantee that the integrated circuit has
sufficient voltage to be fully functional before the output
Error Amplifier
An fully compensated Error Amplifier with access to the
inverting input and output is provided for primary side
voltage sensing, Figure 17. It features a typical dc voltage
gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with
78 degrees of phase margin, Figure 6. The noninverting
input is internally biased at 2.6 V ±3.1% and is not pinned
out. The Error Amplifier output is pinned out for external
loop compensation and as a means for directly driving the
PWM Comparator. The output was designed with a limited
sink current capability of 270 μA, allowing it to be easily
overridden with a pull−up resistor. This is desirable in
applications that require secondary side voltage sensing.
stage is enabled. The UVLO comparator monitors the V
CC
voltage at Pin 3 and when it exceeds 14.5 V, the reset signal
is removed from the PWM Latch allowing operation of the
Power Switch. To prevent erratic switching as the threshold
is crossed, 5.0 V of hysteresis is provided.
Startup Control
An internal Startup Control circuit with a high voltage
enhancement mode MOSFET is included within the
MC33365. This circuitry allows for increased converter
efficiency by eliminating the external startup resistor, and its
associated power dissipation, commonly used in most
off−line converters that utilize a UC3842 type of controller.
Rectified ac line voltage is applied to the Startup Input,
Pin 1. This causes the MOSFET to enhance and supply
Bulk Capacitor Voltage Comparator
In order to avoid output voltage bouncing during
electricity brownout condition, a Bulk Capacitor Voltage
Comparator with programmable hysteresis is included in
this device. The non−inverting input, pin 11, is connected to
internal bias as well as charge current to the V bypass
capacitor that connects from Pin 3 to ground. When V
CC
CC
reaches the UVLO upper threshold of 15.2 V, the IC
commences operation and the startup MOSFET is turned
off. Operating bias is now derived from the auxiliary
transformer winding, and all of the device power is
efficiently converted down from the rectified ac line.
The startup MOSFET will provide a steady current of
the voltage divider comprised of R
and R
as
Upper
Lower
shown in Figure 20 monitoring the bulk capacitor voltage
level. The inverting input is connected to a threshold voltage
of 1.25 V internally. As bulk capacitor voltage drops below
the pre−programmed level, (Pin 11 drops below 1.25 V), a
reset signal will be generated via internal protection logic to
the PWM Latch so turning off the Power Switch
immediately. An internal current source controlled by the
state of the comparator provides a means to program the
voltage hysteresis. The following equation shows the
1.7 mA, Figure 11, as V increases or shorted to ground.
CC
The startup MOSFET is rated at a maximum of 400 V with
V
CC
shorted to ground, and 500 V when charging a V
CC
capacitor of 1000 μF or less.
relationship between V
network resistors.
levels and the voltage divider
BULK
Regulator
A low current 6.5 V regulated output is available for
biasing the Error Amplifier and any additional control
system circuitry. It is capable of up to 10 mA and has
R
+ 20 [ V
* V
* V
]
]
in K Ohm
in K Ohm
Upper
Bulk_H
Bulk_L
Bulk_L
25 [ V
Bulk_H
R
+
Lower
V
* 1.25
Bulk_H
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9
MC33365
short−circuit protection. This output requires an external
bypass capacitor of at least 1.0 μF for stability.
The MC33365 is contained in a heatsinkable plastic
dual−in−line package in which the die is mounted on a
special heat tab copper alloy lead frame. This tab consists of
the four center ground pins that are specifically designed to
improve thermal conduction from the die to the circuit
board. Figure 16 shows a simple and effective method of
utilizing the printed circuit board medium as a heat
dissipater by soldering these pins to an adequate area of
copper foil. This permits the use of standard layout and
mounting practices while having the ability to halve the
junction to air thermal resistance. The examples are for a
symmetrical layout on a single−sided board with two ounce
per square foot of copper.
Thermal Shutdown and Package
Internal thermal circuitry is provided to protect the Power
Switch in the event that the maximum junction temperature
is exceeded. When activated, typically at 150°C, the Latch
is forced into a ‘reset’ state, disabling the Power Switch. The
Latch is allowed to ‘set’ when the Power Switch temperature
falls below 140°C. This feature is provided to prevent
catastrophic failures from accidental device overheating. It
is not intended to be used as a substitute for proper
heatsinking.
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10
MC33365
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
CASE 648E−01
ISSUE O
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
R
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION A AND B DOES NOT INCLUDE MOLD
PROTRUSION.
16
1
9
8
M
−B−
L
5. MOLD FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.25 (0.010).
6. ROUNDED CORNER OPTIONAL.
P
J
F
INCHES
DIM MIN MAX
MILLIMETERS
MIN
18.80
6.23
3.69
0.39
1.27
MAX
19.30
6.60
4.44
0.53
1.77
A
B
C
D
F
0.740
0.245
0.145
0.015
0.050
0.760
0.260
0.175
0.021
0.070
C
G
H
J
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
−T−
SEATING
PLANE
0.008
0.015
0.140
0.305
10
0.21
0.38
3.55
7.74
10
S
K
L
0.120
0.295
0
3.05
7.50
0
K
H
M
P
R
S
_
_
_
_
0.200 BSC
0.300 BSC
5.08 BSC
7.62 BSC
G
D 13 PL
0.015
0.035
0.39
0.88
M
S
S
A
0.25 (0.010)
T
B
The product described herein (MC33365), may be covered by one or more of the following U.S. patents: 4,553,084; 5,418,410; 5,477,175. There may be
other patents pending.
SENSEFET is a trademark of Semiconductor Components Industries, LLC (SCILLC)
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC33365/D
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