MC44605_06_技术文档

MC44605

High Safety, Latched Mode,

GreenLinet PWM Controller

for (Multi) Synchronized

Applications

The MC44605 is a high performance current mode controller that is

specifically designed for off−line converters. This circuit has several

distinguishing features that make it particularly suitable for

multisynchronized monitor applications.

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MARKING

DIAGRAM

The MC44605 synchronization arrangement enables operation from

16 kHz up to 130 kHz. This product was optimized to operate with

universal mains voltage, i.e., from 80 V to 280 V, and its high current

totem pole output makes it ideally suited for driving a power MOSFET.

The MC44605 protections enable a well−controlled and safe power

management. Four major faults while detected, activate the analogic

counter of a disabling block designed to perform a latched circuit

output inhibition.

16

PDIP−16

P SUFFIX

MC44605P

AWLYYWWG

CASE 648

1

A

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

= Pb−Free Package

Features

• Pb−Free Package is Available*

Current Mode Controller

G

• Current Mode Operation up to 250 kHz Output Switching Frequency

PIN CONNECTIONS

• Inherent Feed Forward Compensation

• Latching PWM for Cycle−by−Cycle Current Limiting

• Oscillator with Precise Frequency Control

• Externally Programmable Reference Current

• Secondary or Primary Sensing (Availability of Error Amplifier Output)

• Synchronization Facility

V

R

ref

CC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

WSCD* Program

C

Output

GND

Voltage Feedback Input

Error Amp Output

• High Current Totem Pole Output

Max Power Limitation

Disabling Block (C

)

ext

Overheating

Detection

• V Undervoltage Lockout with Hysteresis

cc

Soft−Start Input

• Low Output dV/dT for Low EMI Radiations

Current Sense Input

Osc Capacitor (C )

T

• Low Startup and Operating Current

Demagnetization

Detection Input

Sync and

EHTOVP Input

Safety/Protection Features

• Soft−Start Feature

(Top View)

• Demagnetization (Zero Current Detection) Protection

• Overvoltage Protection Facility against Open Loop

• EHT Overvoltage Protection (E.H.T.OVP): Detection of too High

Synchronization Pulses

*Winding Short Circuit Detection

ORDERING INFORMATION

• Winding Short Circuit Detection (W.S.C.D.)

• Limitation of the Maximum Input Power (M.P.L.): Calculation of

Input Power for Overload Protection

Device

Package

Shipping

MC44605P

PDIP−16

25 Units/Rail

• Overheating Detection (O.H.D.): to Prevent the Power Switch from

MC44605PG

PDIP−16

(Pb−Free)

an Excessive Heating

Latched Disabling Mode

• When one of the following faults is detected: EHT overvoltage,

Winding Short Circuit (WSCD), a too high input power (M.P.L.),

power switch overheating (O.H.D.), an analogic counter is activated

• If the counter is activated for a time that is long enough, the circuit

gets definitively disabled. The latch can only be reset by making

decrease the V down to about 3.0 V, i.e., practically by unplugging

cc

or turning off the SMPS.

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

©

Semiconductor Components Industries, LLC, 2006

1

Publication Order Number:

June, 2006 − Rev. 5

MC44605/D

MC44605

Block Diagram

R

V

ref

CC

1

16

i

V

enable

ref

cc

Demagnetization

Detection Input

V

demag out

Demagnetization

Management

18 V

8

Supply

Initialization

Block

Reference

Block

UVLO1

UVLO2

V

Output

V

DT

I

2

3

4

C

ref

C

T

Dis

out

10

9

Oscillator

V

S

Output

Gnd

Buffer

Synchronization

and EHTOVP

Input

Set

PWM

Latch

Q

V

cs

Sf

Current

Sense

I

Reset

sense

W.S.C.D*

Comparator

V

CC

ref

E.H.T.OVP

Block

Thermal

Shutdown

V

shift

Over Voltage

Management

V

CC

V

WSCD

V

Level

shift

Programmation

V

UVLO2

CC

enable

V

cs

dis

C

Disabling

Block

MPL

OHD

ext 12

WSCD

Programmation

15

Sf

MPL

Dis

out

I

ref

dis

OHD

V

+

ref

V

2

Error

AMP

cs

Voltage

Feedback

Input

UVLO1

14

MPL

block

O.H.D.

block

−

Soft−Start

V

enable

CC

E/A Output 13

MC44605

7

5

6

11

Current Maximum

Over

Soft−Start

Input

Sense

Input

Power

Heating

Limitation Detection

*W.S.C.D. = Winding Short Circuit Detection

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2

MC44605

MAXIMUM RATINGS

Rating

Pin #

Symbol

(I + I )

Value

40

Unit

mA

V

Total Power Supply and Zener Current

CC

Z

Output Supply Voltage with Respect to Ground

2

1

V

18

C

V

CC

Output Current

Source

3

mA

I

−750

750

O(Source)

Sink

I

O(Sink)

Output Energy (Capacitive Load per Cycle)

Soft−Start

W

5.0

ꢀ J

V

−0.3 to 2.2 V

−0.3 to 5.5 V

SS

Current Sense, Voltage Feedback, E/A Output, C , R , MPL, OHD, C , WSCD

V

in

V

T

ref

ext

E.H.T.OVP, Sync Input Current

Source

mA

9

6

I

sync (Source)

EHT (Source)

−4.0

10

Sink

9

6

I

sync (Sink)

I

EHT (Sink)

Demagnetization Detection Input Current

8

mA

Source

Sink

I

−4.0

10

demag−ib (Source)

I

demag−ib (Sink)

Error Amplifier Output Sink Current

13

I

20

E/A (Sink)

Power Dissipation and Thermal Characteristics

Maximum Power Dissipation at T = 85°C

P

0.6

100

W

°C/W

A

D

Thermal Resistance, Junction−to−Air

Operating Junction Temperature

Operating Ambient Temperature

R

ꢁ

T

JA

150

°C

J

−25 to +85

A

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

ELECTRICAL CHARACTERISTICS (V and V = 12 V, R = 10 kꢂ, C = 2.2 nF, for typical values T = 25°C, for

CC

C

ref

T

A

min/max values T = −25° to +85°C unless otherwise noted.) (Note 1)

A

Characteristic

OUTPUT SECTION (Note 2)

Pin #

Symbol

Min

Typ

Max

Unit

Output Voltage (Note 3)

3

V

Low Level Drop Voltage (I

= 100 mA)

= 500 mA)

V

−

1.0

1.4

1.5

2.0

1.2

2.0

2.7

Sink

OL

(I

High Level Drop Voltage (I

(I

= 200 mA)

= 500 mA)

V

OH

Source

Output Voltage During Initialization Phase

3

V

OL

V

− 0 to 1.0 V, I

− 1.0 to 5.0 V, I

− 5.0 to 13 V, I

= 10 ꢀ A

−

0.1

1.0

CC

Sink

= 100 ꢀ A

= 1.0 ꢀ A

Sink

Output Voltage Rising Edge Slew−Rate (C = 1.0 nF, T = 25°C)

dVo/dT

−

300

−

V/ꢀ s

L

J

Output Voltage Falling Edge Slew−Rate (C = 1.0 nF, T = 25°C)

−300

L

J

1. Adjust V above the startup threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction

CC

temperature as close to ambient as possible.

2. No output signal when the Error Amplifier output is in Low State, i.e., when for instance, V = 2.7 V.

FB

3. V must be greater than 5.0 V.

C

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3

MC44605

ELECTRICAL CHARACTERISTICS (V and V = 12 V, R = 10 kꢂ, C = 2.2 nF, for typical values T = 25°C, for

CC

C

ref

T

A

min/max values T = −25° to +85°C unless otherwise noted.) (Note 4)

A

Characteristic

Pin #

Symbol

Min

Typ

Max

Unit

ERROR AMPLIFIER SECTION

Voltage Feedback Input (V

= 2.5 V)

14

V

2.4

−2.0

65

2.5

−0.6

70

2.6

−

V

ꢀ A

E/A out

FB

Input Bias Current (V = 2.5 V)

I

FB−ib

FB

Open Loop Voltage Gain (V

Unity Gain Bandwidth

= 2.0 V to 4.0 V)

A

VOL

−

dB

E/A out

BW

MHz

T = 25°C

A

−

5.5

J

T = −25° to +85°C

Voltage Feedback Input Line Regulation (V = 10 V to 15 V)

V

−10

−

10

mV

mA

CC

FBline−reg

Output Current

13

Sink (V

= 1.5 V, V = 2.7 V)

I

Sink

E/A out

FB

T = −25° to +85°C

2.0

12

−

A

Source (V

= 5.0 V, V = 2.3 V)

I

Source

E/A out

FB

T = −25° to +85°C

A

−2.0

−0.2

Output Voltage Swing

V

High State (I

Low State (I

= 0.5 mA, V = 2.3 V)

V

OH

5.5

−

6.5

1.0

7.5

1.1

E/A out (source)

E/A out (sink)

FB

= 0.33 mA, V = 2.7 V)

V

FB

OL

CURRENT SENSE SECTION

Maximum Current Sense Input Threshold

7

V

0.96

1.0

1.04

cs−th

(V

= 2.3 V and V

= 1.2 V)

Feedback (pin14)

Soft−Start (pin11)

Input Bias Current

I

−10

−

−2.0

120

−

ꢀ

A

cs−ib

Propagation Delay (Current Sense Input to Output at V of MOS

t

200

ns

TH

PLH(In/Out)

transistor = 3.0 V)

OSCILLATOR AND SYNCHRONIZATION SECTION

Frequency (T = −25° to +85°C)

F

16

−

0.05

−

20

−

kHz

%/V

%/°C

−

A

OSC

Frequency Change with Voltage (V = 10 V to 15 V)

ꢃ F

I

/ꢃ V

/ꢃ T

CC

OSC

Frequency Change with Temperature (T = −25° to +85°C)

−

A

OSC

Ratio Charge Current/Reference Current (T = −25° to +85°C)

/I

0.39

72

0.48

78

A

charge ref

Free Mode Oscillator Ratio = I

/(I

+ I

)

charge

D

75

%

discharge discharge

Synchronization Input Threshold Voltage

Negative Clamp Level (I = 2.0 mA)

9

V

−250

−0.65

−200

−0.5

−150

−0.34

mV

V

syncth

NEG−SYNC

syncth−in

UNDERVOLTAGE LOCKOUT SECTION

Startup Threshold

1

V

13.6

8.3

14.5

−

15.4

9.6

V

stup−th

Disable Voltage After Threshold Turn−On (UVLO 1)

V

disable1

(T = −25° to +85°C)

A

Disable Voltage After Threshold Turn−On (UVLO 2)

1

V

7.0

7.5

8.0

V

disable2

(T = −25° to +85°C)

A

4. Adjust V above the startup threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction

CC

temperature as close to ambient as possible.

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4

MC44605

ELECTRICAL CHARACTERISTICS (V and V = 12 V, R = 10 kꢂ, C = 2.2 nF, for typical values T = 25°C, for

CC

C

ref

T

A

min/max values T = −25° to +85°C unless otherwise noted.) (Note 5)

A

Characteristic

Pin #

Symbol

Min

Typ

Max

Unit

REFERENCE SECTION

Reference Output Voltage (V = 10 V to 15 V)

16

V

2.4

−500

−40

2.5

−

2.6

−100

40

V

CC

ref

Reference Current Range (I = V /R , R = 5.0 k to 25 kꢂ)

I

ꢀ A

mV

ref

ref ref

ref

Reference Voltage Over I Range

ꢃ

V

−

ref

DEMAGNETIZATION DETECTION SECTION (Note 6)

Demagnetization Detect Input

8

Demagnetization Comparator Threshold (V

Decreasing)

V

50

−

−0.5

65

0.5

−

80

−

mV

ꢀ s

ꢀ A

pin9

demag−th

Propagation Delay (Input to Output, Low to High)

Input Bias Current (V = 65 mV)

t

PLH(In/Out)

demag

I

demag−lb

Minimum Off−Time when the pin 8 is grounded

Negative Clamp Level (I = −2.0 mA)

T

1.5

3.0

4.5

ꢀ s

V

DEM−GND

CLVL−neg

−0.50

0.50

−0.38

0.72

−0.25

0.85

demag

Positive Clamp Level (I

= +2.0 mA)

CLVL−pos

V

demag

SOFT−START SECTION (Note 7)

Ratio Charge Current/I (T = −25° to +85°C)

I /I

ss−ch ref

0.37

1.5

−

0.43

−

mA

V

ref

A

Discharge Current (V

Clamp Level

= 1.0 V)

I

5.0

2.4

−

soft−start

discharge

V

2.2

2.6

150

0.55

SS−CLVL

Circuit Inhibition Threshold (Note 8)

Soft−Start Clamp Level (R

V

30

mV

V

SSinhi

CSsoft−start

V

= 5 kꢂ)

soft−start

V

0.45

0.5

CS

OVERVOLTAGE SECTION

Propagation Delay (V > 18.1 V to V Low)

T

1.0

−

4.0

ꢀ

s

CC

out

PHL(In/Out)

Protection Level on V (T = −25° to +85°C)

V

15.9

18.1

V

CC

A

CC prot

EHT OVP SECTION (Note 9)

Negative Clamp Level (I

= −2.0 mA)

NEG−SYN

C

−0.65

−0.5

−0.35

V

synch−in

EHT OVP Input Threshold

V

7.0

7.4

−

7.8

0

V

ref

EHT OVP Input Bias Current (V

= 0 V)

9

I

−5.0

ꢀ

A

EHT OVP(pin 9)

EHTOVP

WINDING SHORT CIRCUIT DETECTION SECTION

WSCD Threshold with I

= 200 ꢀ A

Vshift

70

100

120

mV

pin15

MPL & OHD SECTION

−1

MPL Parameter (Note 10)

Γ

0.185

2.4

0.240

2.5

0.295

2.6

V

MPL

MPL Comparator Threshold (Note 11)

OHD Parameter (Note 12)

V

MPL−th

−1

Γ

OHD

1.15

2.4

1.50

2.5

1.85

2.6

V

OHD Comparator Threshold (Note 13)

V

OHD−th

5. Adjust V above the startup threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction

CC

temperature as close to ambient as possible.

6. This function can be inhibited by connecting pin 8 to GND. In this case, there is a minimum off−time equal to T

7. The MC44605 can be shut down by connecting soft−start pin (pin 11) to GND.

.

DEM−GND

8. The circuit is shutdown if the soft−start pin voltage is lower than this level.

9. This function can be inhibited by connecting pin 9 to GND. In this case, the synchronization block is inhibited too and the MC44605 works

in free mode.

10.This parameter is defined in the MPL §. This parameter is obtained by measuring the MPL pin average current and dividing this result by the

corresponding squared V , the measured frequency value and the C value deducted from the measured frequency value.

CS

T

Measurement conditions: V

= 2.3 V, V

= 0.5 V and pins 7, 8, and 9 connected to GND (the working frequency

Feedback(pin 14)

soft−start(pin 11)

is typically equal to 18 kHz − R = 10 kꢂ "1%, C = 2.2 nF).

ref

T

11. The MPL comparator output is Dis

.

MPL

12.This parameter is defined in the OHD §. This parameter is obtained by measuring the OHD pin average current and dividing this result by

the corresponding squared V value and multiplying it by the R value.

CS

ref

Measurement conditions: V

= 2.3 V, V

= 0.5 V and pins 7, 8, and 9 connected to GND (the working frequency

Feedback(pin 14)

soft−start(pin 11)

is typically equal to 18 kHz − R = 10 kꢂ "1%, C = 2.2 nF).

ref

T

13. The OHD comparator output is Dis

.

OHD

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5

MC44605

ELECTRICAL CHARACTERISTICS (V and V = 12 V, R = 10 kꢂ, C = 2.2 nF, for typical values T = 25°C, for

CC

C

ref

T

A

min/max values T = −25° to +85°C unless otherwise noted.) (Note 14)

A

Characteristic

Pin #

Symbol

Min

Typ

Max

Unit

DISABLING BLOCK SECTION

Delay Pulse Width

T

−

4.0

100

3.1

−

ꢀ s

%

WSCD

Ratio (EHTOVP and WSCD Disabling Capacitor Charge Current)I

I

/I

Dis−H ref

90

110

3.5

5.0

ref

Ratio (MPL and OHD Disabling Capacitor Charge Current)I

I

/I

Dis−L ref

2.7

1.0

ref

Minimum V Value Enabling the Disabling Block Latch (Note 15)

V

CC

CCDis

TOTAL DEVICE

Power Supply Current

I

mA

CC

Startup−Up (V = 5.0 V with V increasing)

−

0.35

20

0.55

25

CC

Startup−Up (V = 9.0 V with V increasing)

CC

Startup−Up (V = 12 V with V increasing)

−

CC

Operating T = −25°C to +85°C (Note 16)

−

A

Disabling Mode (V = 6.0 V) (Note 17)

−

0.55

−

CC

Power Supply Zener Voltage (I = 35 mA)

V

18.5

−

V

CC

Z

Thermal Shutdown

−

155

−

°C

14.Adjust V above the startup threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction

CC

temperature as close to ambient as possible.

15.Once a fault detection activated it, the Disabling Block Latch gets reset when the V becomes lower than this threshold.

CC

16.Refer to Note 14.

17.This consumption is measured while the circuit is inhibited by the Definitive Latch.

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6

MC44605

1

Name

Pin Description

This pin is the positive supply of the IC.

V

CC

2

V

The output high state, V , is set by the voltage applied to this pin. With a separate

C

OH

connection to the power source, it gives the possibility to set by means of an external

resistor the output source current at a different value than the sink current.

3

4

Output

GND

The output current capability is suited for driving a power MOSFET.

The ground pin is a single return typically connected back to the power source. It is used as

control and power ground.

5

Maximum Power Limitation

This block enables to estimate the input power. When this calculated power is detected as

too high, a fault information is sent to the disabling block in order to definitively disable the

circuit.

6

7

Over−Heating Detection

Current Sense Input

This block estimates the MOSFET heating. When this calculated heating is too high, the

device gets definitively disabled (disabling block action).

A voltage proportional to the current flowing into the power switch is connected to this input.

The PWM latch uses this information to terminate the conduction of the output buffer. A

maximum level of 1 V allows to limit the inductor current.

8

Demagnetization Detection

A voltage delivered by an auxiliary transformer winding provides to the demagnetization pin

an indication of the magnetization state of the flyback energy reservoir. A zero voltage

detection corresponds to a complete core demagnetization. The demagnetization detection

prevents the oscillator from a re−start and so the circuit from a new conduction phase, if the

fly−back is not in a dead−time state. This function can be inhibited by connecting Pin 8 to

GND but in this case, there is a minimum off−time typically equal to 3 ꢀ s.

9

Synchronization and

E.H.T.OVP Input

Activating the synchronization input pin with a pulse higher or equal to the negative

threshold (typically −200 mV) allows the next switching period to be reinitialized. The

oscillator is free when connecting Pin 9 to GND.

When the E.H.T.OVP pin receives a voltage that is greater than 7.5 V, the disabling block

C

ext

capacitor is charged so that the circuit gets definitively disabled if the C voltage

ext

becomes higher than V . This block is incorporated to detect and disable the device when

ref

the synchronization pulses are too high.

10

11

12

Oscillator Capacitor C

Soft−Start

The free mode oscillator frequency is programmed by the capacitor C choice together with

T

the R resistance value. C , connected between pin 10 and GND, generates the oscillator

ref

T

sawtooth.

A capacitor connected to this pin can temporary reduce the maximum inductor peak

current. By this way, a soft−start can be performed. By connecting pin 11 to Ground, the

MC44605 is shutdown.

C

ext

(Disabling Block)

When a too high synchronization pulse voltage (E.H.T.OVP) or a winding short circuit

(WSCD) is detected, the capacitor C is charged using a current source I

. In the

Dis− H

ext

case of a MPL or OHD fault detection, C is charged using I

. If the C capacitor

Dis−L ext

ext

voltage gets higher than V , the circuit is definitively disabled. Then, to re−start, the

ref

converter must be switched off in order to make V decrease down to about 0 V.

CC

13

14

E/A Output

Voltage Feedback

The error amplifier output is made available for loop compensation.

This is the inverting input of the Error Amplifier. It can be connected to the Switching Mode

Power Supply output through an optical (or else) feedback loop or to the subdivided V

voltage in case of primary sensing technic.

CC

15

16

Winding Short Circuit

Detection Programmation

The W.S.C.D. block is incorporated to detect the transformer Winding Short Circuits. This

function is performed by detecting the inductor overcurrents thanks to a comparator which

threshold is programmable to be well adapted to any application.

R

ref

The R value fixes the internal reference current that is particularly used to perform the

ref

precise oscillator waveform. The current range goes from 100 ꢀ A up to 500 ꢀ A.

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7

MC44605

Summary of the Main Design Equations

The following table consists of equations enabling to dimension a multisynchronized SMPS operating in discontinuous

mode.

Pout

is the maximum power the load may draw in normal working.

max

Pout

max

+

The maximum input power Pin

efficiency (η). In this kind of application, the efficiency is generally taken equal to

80%.

is easily deducted by dividing Pout

by the

max

η

The inductor value Lp must be chosen lower than Lp

value (to optimize the application design−in).

or ideally equal to this

max

2

Ǹ

2·Vac

NVo

min

ƪ ƫ

Ǹ

2·Vac

)NVo

min

fsync

In effect, if Lp was higher than Lp

, a synchronized and discontinuous working

max

Lp

+

could not be guaranteed (in some cases, the demagnetization phase would not be

finished while a new conduction phase should start to follow the synchronization).

max

Ipk

2 Pin

max

Ipk

is the maximum inductor peak current. This current is obtained when the

max

2 Pin

max

L fsync

power to transfer is maximum at the minimum synchronization frequency (60 W

output, 30 kHz in the proposed application).

+

Ǹ

max

min

d

is the maximum duty cycle. The duty cycle is maximum at the lowest input

max

Ǹ_Pin

Lp fsync

max

voltage when the power demand is maximum while the synchronization frequency

also is maximum.

d

+

max

Vac

min

Pon

is the maximum MOSFET on−time losses that are proportional to Ipk

,

max

d

max

and Rds (on−time MOSFET resistor).

on

1

3

2

Pon

+

Rds Ipk

d

max

on

max

This conduction losses estimation enables to dimension the power MOSFET.

(V )max is the maximum voltage the power switch must be able to face. In fact,

this calculation does not take into account the turnings off spikes. So, it is

necessary to take a margin of at least about 50 V.

DS

Ǹ

_{max +}ǒ

_maxǓ_{) (N Vout)}

)

(V

2 Vac

DS

(V )max is the maximum voltage the high voltage secondary diode must be able

to face. Because of the turning off spikes, a margin must also be taken.

D

Vac

max

Ǹ

_{(V ) max +}ǒ ₂Ǔ_) Vout

D

N

(A ) and (ni) are the magnetic parameters.

L

(ni)

+ N n

Ipk

max

Vout

(ni)

must not exceed the ferrite (ni). Otherwise, the transformer may get

max

saturated when the peak current is high.

(A ) is the ferrite constant that links the primary inductor value to the squared

L

P

2

number of primary turns: Lp = A x n

.

A

+

L

p

L

2

(N n

)

Vout

+

Error Amplifier

1.0 mA

Compensation

A fully compensated Error Amplifier with access to the

inverting input and output is provided. It features a typical

DC voltage gain of 70 dB. The non inverting input is

internally biased at 2.5 V and is not pinned out. The

converter output voltage is typically divided down and

monitored by the inverting input. The maximum input bias

current with the inverting input at 2.5 V is −2.0 ꢀ A. This can

cause an output voltage error that is equal to the product of

the input bias current and the equivalent input divider source

resistance.

Error

Amplifier

13

14

R

f

FB

2R

2.5 V

C

f

R

Voltage

Feedback

Input

Current

Sense

Comparator

1.0 V

GND

MC44605

4

From Power Supply Output

R

2

R

1

Figure 1. Error Amplifier Compensation

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8

MC44605

The Error Amp Output (Pin 13) is provided for external

V

* 1.4 V

(pin13)

I

[

loop compensation. The output voltage is offset by two

diodes drops ([1.4 V) and divided by three before it

connects to the inverting input of the Current Sense

Comparator. This guarantees that no drive pulses appear at

the Source Output (Pin 3) when Pin 13 is at its lowest state

pk

3 R

S

The Current Sense Comparator threshold is internally

clamped to 1.0 V. Therefore the maximum peak switch

current is:

(V ). This occurs when the power supply is operating and

1 V

OL

I

+

pk(max)

R

the load is removed, or at the beginning of a soft−start

interval. The Error Amp minimum feedback resistance is

limited by the amplifier’s minimum source current (0.2 mA)

S

Undervoltage Lockout Section

and the required output voltage (V ) to reach the current

OH

As depicted in Figure 3, an undervoltage lockout has been

incorporated to guarantee that the IC is fully functional

before allowing the system working.

sense comparator’s 1.0 V clamp level:

(3 1 V) ) 1.4 V

R1(min) +

+ 22 kΩ

0.2 mA

In effect, the V is connected to the non inverting input

CC

of a comparator that has an upper threshold equal to 14.5 V

Current Sense Comparator and PWM Latch

(typical V

) and a lower one equal to 7.5 V (typical

stup−th

The MC44605 operates as a current mode controller. The

circuit uses a current sense comparator to compare the

inductor current to the threshold level established by the

Error Amplifier output (Pin 13). When the current reaches

the threshold, the current sense comparator terminates the

output switch conduction that has been initiated by the

oscillator, by resetting the PWM Latch. Thus the error signal

controls the peak inductor current on a cycle−by−cycle

basis. This configuration ensures that only one single pulse

appears at the Source Output during the appropriate

oscillator cycle.

V

). This hysteresis comparator enables or disables

disable 2

the reference block that generates the voltage and current

sources required by the system.

This block particularly, produces V (pin 16 voltage) and

ref

I

that is determined by the resistor R connected between

ref

pin 16 and the ground:

V

ref

I

+

where V + 2.5 V (typically)

ref

R

ref

V

CC

R

ref

(Pin 1)

V

in

Pin 16

V

ref enable

V

C

STARTUP

14

UVLO

Dis

out

Reference Block:

Voltage and Current

Sources Generator

1

0

R

2

Q1

V

demag out

3

1

0

(V , I , ...)

ref ref

VS

S

R

3

V

STARTUP

14.5 V

disable

Q

7.5 V

R

Thermal

Protection

C

UVLO1

PWM

Latch

UVLO1

(to SOFT−START)

Current

Sense

V

Substrate

disable1

9.0 V

R

MC44605

Current Sense

Comparator

7

R

C

S

Figure 3. V_CCManagement

Figure 2. Output Totem Pole

In addition to this, V is compared to a second threshold

CC

level that is nearly equal to 9.0 V (V

UVLO1 is generated to reset the soft−start block and so, to

disable the output stage (refer to the Soft−Start §) as soon as

) so that a signal

disable1

The inductor current is converted to a voltage by inserting

the ground referenced sense resistor R in series with the

S

power switch Q1.

V

CC

becomes lower than V

. In this way, the circuit

disable 1

This voltage is monitored by the Current Sense Input

(Pin 7) and compared to a level derived from the Error Amp

output. The peak inductor current under normal operating

conditions is controlled by the voltage at Pin 13 where:

is reset and made ready for a next startup, before the

reference block is disabled (refer to Figure 3). Thus, finally

the upper limit for the minimum normal operating voltage

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9

MC44605

is 9.4 V (maximum value of V

) and so the minimum

The MC44605 oscillator achieves four functions:

disable 1

hysteresis is 4.2 V. [(V

)

= 13.6 V].

— it fixes the free mode frequency

stup−th min

The large hysteresis and the low startup current of the

MC44605 make it ideally suited for off−line converter

applications where efficient bootstrap startup techniques are

required.

— it takes into account the synchronization signal

— it does not allow a new power switch conduction if the

flyback is not in a dead−time state when the circuit

works in demagnetization mode (pin 8 connected)

— it builds the Sf pulse required by the MPL block

During the operating mode, the oscillator sawtooth can

vary between a valley value (1.6 V typically) and a peak one

(3.6 V typically) and presents three distinct phases:

Soft−Start Control Section

The V value is clamped down to the pin 11 voltage.

cs

So, if a capacitor is connected to this pin, its voltage

increases slowly at the startup (the capacitor is charged by

— the C charge

T

— the C discharge

T

an internal current source 0.4 I ). So, V is limited during

ref

cs

— the phase during which the oscillator voltage is

maintained equal to its valley value. This happens at

the end of a discharge cycle when the synchronization

the startup and then a soft−start is performed.

This pin can be used to inhibit the circuit by applying a

voltage that is lower than V

(refer to page 4).

SSinhi

or demagnetization condition does not allow a new C

T

Particularly, the MC44605 can be shutdown by connecting

the soft−start pin to ground.

charge phase. During this sequence, I

REGUL

compensates the charge current I

.

charge

As soon as V

is detected (that is V lower than

dis1

cc

The oscillator has two working modes:

— a free one when there is no synchronization

— a synchronized one.

In the free working, the oscillator grows up from its valley

value to its peak one for the charge phase and when once the

V

disable1

), a signal UVLO1 is generated until the V falls

cc

down to V

(refer to the undervoltage lockout section §).

dis2

During the delay between the disable1 and the disable2,

using a transistor controlled by UVLO1, the pin 11 voltage

is made equal to zero in order to make the soft−start

arrangement ready to work for the next re−start.

peak value is reached, a discharge sequence makes the C

T

voltage decrease down to its valley value. When the

decrease phase is finished, a new charge cycle occurs if the

V

ref

demagnetization condition is achieved (V

high).

DT

Vcs

0.4 I

Otherwise there is a REGUL phase until V gets high.

ref

DT

In the synchronized mode, the charge cycle is only

allowed when the synchronization signal gets high while a

Pin 11

Soft

Start

Capacitor

Output

Inhibition

D

Z

2.4 V

dead time has been detected (V high). This charge phase

DT

UVLO1

is stopped when the synchronization signal has got low and

when the oscillator voltage is higher than V , the

int

intermediary voltage level used to generate the calibrated

V

SSlnhi

pulse Sf by comparing the C voltage to this threshold. So,

T

when these two conditions are performed, a discharge

sequence is set until the oscillator voltage is equal to its

MC44605

valley value. Then, the C voltage is maintained constant

T

thanks to the “REGUL” arrangement until the next

synchronization pulse.

Figure 4. Soft−Start

In both cases, during the charge phase, a signal V is

S

generated. When Sf becomes high. V gets high and remains

Oscillator Section (Figures 5 & 5b)

S

in this state until the PWN latch is set of Sf is low. Then, V

S

The oscillator and synchronization behavior is

represented in Figure 5b.

keeps low until the next Sf high level. This oscillator

behavior is obtained using the process described in

Figure 5b.

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10

MC44605

a − Free mode

Inductor

current

V

DT

Oscillator

V

int

Sf

Output

b − Synchronized mode

Synchro

input

Inductor

current

V

DT

Oscillator

V

int

Sf

Output

Figure 5b. Oscillator Behavior

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11

MC44605

V

ref

In effect, the output of the latch L1 is:

— high during the oscillator capacitor charge and during

the REGUL phase

— low for the oscillator capacitor discharge

Now, the latch L2 is set when the L1 output is high and the

synchronization condition is performed (that is: sync = 1 −

free mode or synchro signal high state) and during the

I

charge

C

OSCINT

Vint

&

sync

DISCH

PWM

Latch

Output

C

OSC HIGH

dead−time (V high). So, this latch is set for the C charge.

DT

T

3.6 V

On the other hand, this latch is reset by the signal used to

reset L1. Consequently, it is reset at the end of the charge

phase.

&

Sf

C

PWM

Latch

Set

OSCINT

&

So, in any case, Q is:

L2

VS

— high during the C charge cycle

C

T

OSC LOW

— low in the other cases

Q

L2

1.6 V

Thus, this latch enables to obtain a signal that is high for

the charge phase and low in the other cases, whatever the

mode (synchronized or free) and whatever the

synchronization pulses width (higher than the delay

necessary for the oscillator to reach its intermediary value or

lower than this delay) in the synchronized mode.

That is why:

V

(from demag

block)

DT

C <1.6 V

T

sync

&

S Q

L2

S Q

L1

R

10

C

T

Q

R

DISCH

C

OSC REGUL

— the discharge current source must be connected to the

1

0

oscillator capacitor when Q is low. The condition (C

L1

T

voltage higher than the valley value) is added to stop

the discharge phase as soon as the oscillator voltage is

detected as lower than the valley value (without any

delay due to the L1 latch propagation time).

&

0

1

Q

L2

I

regul

— the REGUL current source must be connected when:

I

discharge

MC44605

• Q is high (charge or REGUL phase)

L1

• Q is low (the oscillator is not in a charge phase)

L2

On the other hand, the oscillator charge is stopped when:

— the oscillator voltage reaches the peak value in the

free mode

Figure 5. Oscillator

Synchronization Section (Note 1)

— the oscillator voltage is higher than the intermediary

The synchronization block consists of a protection

arrangement similar to the demagnetization block one (a

diode + a negative active clamping system (Note 2)). In

addition to this, a high value resistor (R − about 50 kꢂ) is

incorporated as the pin 9 input is also used by the EHTOVP

section.

The signal obtained at the output of this protection

arrangement, is compared to a negative threshold (−200 mV,

typically) so that when the synchronization pulse applied to

the pin 9 (through a resistor or a resistors divider to adapt this

input to the EHTOVP function), is higher than this

threshold, the system considers that the synchronization

condition is performed (free mode or synchronization signal

high level).

value (V ) and the synchronization signal is negative,

int

in the synchronized mode.

Consequently, in any case, Q that is high during the

L2

oscillator charge phase, is high for the delay during which

the oscillator voltage grows from the valley value up to the

intermediary one. That is why the signal Sf (refer to the MPL

block) that must be high when the oscillator voltage is

between the valley value and the intermediary one during

the charge phase (Q high), is obtained using an AND gate

L2

with the following inputs:

— Q (Q high <=> charge phase)

L2

— C

(C high <=> the C voltage is lower

OSCINT T

OSCINT

than the intermediary value).

So, using the output of this AND gate, Sf is obtained.

This signal Sf is connected to a logic block consisting of

two AND gates and an OR one. This block aims at supplying

a signal VS that:

— gets high as soon as Sf becomes high if the PWM

latch output is low

Note 1. The synchronization can be inhibited by connecting the

pin 9 to the ground. By this means, a free mode is

obtained.

Note 2. This negative active clamping system works even if the

circuit is off. This feature is really useful as

synchronization pulses may be applied while the product

is off.

— gets low as soon as the PWM latch is set and then

remains low until the next cycle.

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12

MC44605

V

CC

A diode D is incorporated to clamp the positive applied

Synchro.

Signal

voltages while an active clamping system limit the negative

voltages to typically −0.33 V. This negative clamp level is

high enough to avoid the substrate diode switching on.

E.H.T. OVP

Block

Negative Active

Clamping System

A

latch system is incorporated to keep the

Pin 9

demagnetization block output level low as soon as a voltage

lower than 65 mV is detected and as long as a new restart is

produced (high level on the output (refer to Figure 8). This

process avoids that any ringing on the signal used on the

pin 8, disrupts the demagnetization detection (refer to

Figure 7). Finally, this method results in a very accurate

R

sync

−200 mV

MC44605

demagnetization phase detection, and the signal V drawn

DT

from this block is high only for the dead time. Therefore, an

oscillator re−start and so, a new power switch conduction is

only allowed during the dead−time.

Figure 6. Synchronization

For a higher safety, the V

output of the

demagout

Demagnetization Section

demagnetization block is also directly connected to the

output, to disable it during the demagnetization phase (refer

to the block diagram).

The demagnetization detection can be inhibited by

connecting pin 8 to the ground but in this case, a timer (about

3 ꢀ s) that is incorporated to set the latch when it can not be

This block is incorporated to detect the complete core

demagnetization in order to prevent the power MOSFET

from switching on if the converter is not in a dead time

phase. That is why this block inhibits any oscillator re−start

as long as the inductor current is not finished (from the

beginning of the on−time to the end of the demagnetization

phase).

set by V

, results in a minimum off−time (refer to

demagout

Figure 8).

In a fly−back, a good means to detect the demagnetization

phase consists in using the V winding voltage. In effect,

Output

CC

this voltage is:

Buffer

— negative during the on−time,

— positive during the off−time,

— equal to zero for the dead−time with generally a

ringing (refer to Figure 7).

ꢀ

s

3

R

Q

Demag

V

CC

Q

S

Zero

Current

Detection

0.75 V

Negative Active

Clamping System

V

demag out

V

pin 8

Pin 8

65 mV

C DEM

D

65 mV

Oscillator

V

DT

−0.33 V

Figure 8. Demagnetization Block

On−Time Off−Time Dead−Time

Overvoltage Protection Section

The overvoltage arrangement compares a portion V to

Figure 7. Demagnetization Detection

cc

V

(2.5 V) (refer to Figure 9). In fact, this threshold

ref

That is why, the MC44605 demagnetization detection

corresponds to a V equal to to 17 V. When the V is

higher than this level, the output is latched off until a new

circuit re−start.

CC

cc

consists of a comparator that compares the V winding

CC

voltage to a reference that is typically equal to 65 mV.

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13

MC44605

V

ref

For instance, if this threshold value is required to be equal

to 30 V, V must be equal to 7.5 V when the

V

pin9

CC

synchronization pulse value is 30 V.

So, in this case:

In

Delay

Out

τ ^{5.0 ꢀ s}

T

r2

30

+ 7.5

2.5 V

r1 ) r2

0

Enable

Then, the ratio (r1/r2) can be deducted:

V

OVP out

r1

+ 3

τ

In

Out

r2

Delay

C

OVLO

So, as r1 and r2 must be negligible in relation to R (about

50 kꢂ), the couple of resistors can be chosen as follows:

2.0 ꢀ s

2.5 V

(V

(If V

= 1.0,

OVP out

)

ref

the Output is Disabled)

r1 + 3 kΩ

and:

Figure 9. Overvoltage Protection

r2 + 1 kΩ

A delay (2 ꢀ s) is incorporated in order to avoid any

activation due to interferences by only taking into account

the overvoltages that last at least 2 ꢀ s.

Winding Short Circuit Detection Section (WSCD)

The MC44605 being designed to control a Fly−Back

SMPS, this block is incorporated to detect a short circuit on

a transformer winding or on an output diode (refer to

Figure 11).

The V

is connected when once the circuit has

CC

started−up in order to limit the circuit startup consumption

(T is switched on when once V has been generated).

ref

The overvoltage section is enabled 5 ꢀ s after the regulator

has started to allow the reference V to stabilize.

ref

+

E.H.T. Overvoltage Protection Section

AC Line

L

p

+

This block uses the synchronization input as this section

is incorporated to detect too high synchronization pulses and

then to activate the device definitive latch in this case.

L

leak

MC44605

V

CC

Synchro.

Pulses

R

S

Synchronization

Block

Negative Active

Clamping System

r1

Disabling

Block

Figure 11. Winding Short Circuit Fault

Pin 9

r2

C

2R

EHTOVP

In the case of a Winding Short Circuit, the primary

inductor L is short circuited and then the current increase

E.H.T.

OVP

p

4 V

R

is only controlled by the leakage inductor L

In current mode, the power switch conduction is stopped

when the inductor current is detected as high enough, by the

.

leak

V

ref

MC44605

controller. In fact, when the current sense resistor (R )

s

voltage gets equal to V , the current sense comparator

switches to reset the output.

cs

Figure 10. E.H.T. OVP

Now, the circuit has a propagation delay and the power

switch needs some time to turn off. Consequently, there is a

This block consists of a high impedance resistors bridge

(R is nearly equal to 50 kꢂ − refer to Figure 10) so that the

EHTovp threshold is 7.5 V. So, using an external resistors

bridge (r1, r2 <<R), the synchronization pulse level above

which the working must be considered as wrong, can be

adjusted.

delay ꢃt between the moment at which the R voltage gets

s

equal to V and the actual current increase stop. So, this

cs

results in an overcurrent (refer to Figure 12).

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14

MC44605

Finally, when there is a winding short circuit, an

overcurrent is detected by the WSCD comparator. The

output of this comparator, V , is connected to the

(V + V )/R

(Vin x ꢄt/L

leak

CS

shift

S

WSCD

disabling block (refer to the disabling block §).

Vin x ꢄt/L

p

Maximum Power Limitation Section (MPL)

V

/R

CS S

The MPL block is designed to calculate this input power

using the following equation:

1

2

Pin + L Ipk f

P

where: Lp is the inductor value

Ipk is the inductor peak current

f is the switching frequency

time

ꢄt

Figure 12. Overcurrent in a WSCD Case

As V is proportional to the inductor peak current

cs

(V = R x Ipk), the squared Ipk value is estimated by

cs

s

2

Now, in normal working, this overcurrent ꢃIpk is equal to:

building a current source proportional to V . This current

cs

is chopped by a calibrated pulse Sf, generated at each new

oscillator cycle (refer to Figure 14).

Finally, using an external resistor and capacitor network

Vin δt

ꢃ

I

p

k

+

L

P

where: V is the input voltage (rectified a.c. line)

in

(R

MPL

, C

) on the MPL pin, a voltage V

,

MPL

While in a WSCD case:

proportional to the input power can be obtained.

Vin δt

In effect,

(ꢃIpk)

+

WSCD

L

Leak

(Sf)

T

2

V

+ R

k

Vcs

MPL

Consequently, as the leakage inductor value is generally

much lower than the primary one (less than 5% generally),

the overcurrent is much higher in the WSCD case. That is

why this fault can be detected by detecting the high

overcurrents.

where: k

is the multiplier gain

MPL

(Sf) is the width of the calibrated pulse

T is the switching (oscillator) period

Now, as Sf is built comparing the oscillator to a constant

level, (Sf) is proportional to R and C :

So, the WSCD block consists of comparing the sensed

ref

T

current to a reference equal to: (V + V ), where V is

cs

shift

(Sf) + k1 R C

ref

a voltage proportional to the current injected in the pin 15

(refer to Figure 13).

T

where: k1 is a constant

On the other hand, k

that is depending on the reference

MPL

Vin

current source I , is proportional to 1/R

:

ref

1

C

WSCD

k

+ k2

I

R

sense

MPL

R

Disabling

Block

Pin 7

ref

V

WSCD

where: k2 is a constant

So:

Pin 15

3.75 ꢂ

2

V

= 500 ꢂ

V

+ R

k1 k2 Vcs f C

V

shift shift

shift

MPL

T

I

shift

where: C is the oscillator capacitor

T

Vcs

Finally:

MC44605

2

V

+ R

Γ

Vcs f C

MPL

T

Figure 13. WSCD

where: Γ

is the MPL parameter as defined in the

MPL

specification. This is a constant equal to the product

(k1 x k2).

Now, as the overcurrent level depends on the input voltage

V , it is preferable to use a V proportional to this input

in

shift

voltage instead of a constant V . So, the WSCD pin must

Now, as:

shift

be connected to V through a resistor that fixes V

adjusting the current injected in this pin 15.

by

in

shift

1

2

Pin + L Ipk f

P

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15

MC44605

and:

So:

As in the MPL section, the squared Ipk term is estimated

by building a current source proportional to Vcs .

2

Vcs + R Ipk

S

The duty cycle is taken into account thanks to the action

on this current source of a “chopper” controlled by the

circuit output. By this means, the pin 6 average current is

proportional to the squared peak current multiplied to the

duty cycle (refer to Figure 14).

2

2 R

Γ

C R

MPL

T

S

V

+

MPL

L

P

So, using an external resistor and capacitor network

A comparator is used to compare V

to V , the output

ref

MPL

(R

, C

) on this pin, a voltage V

, proportional to

OHD OHD

OHD

of which, Dis

, is connected to the “definitive inhibition

MPL

the conduction losses can be obtained.

Like in the MPL block, this voltage V

latch” of the disabling block. So, when the calculated power

is higher than the threshold, the circuit is definitively

disabled (the system considers that there is an overload

condition).

, is compared to

OHD

2.5 V. If V

gets higher than this threshold, the disabling

OHD

block is activated by Dis

(output of the comparator).

OHD

The external resistor R

choice enables to obtain a

OHD

Finally, replacing V

by 2.5 V (the threshold value),

MPL

calculated V

equal to 2.5 V when the conduction losses

OHD

the R

value to be used, can be deducted:

MPL

are equal to their maximum value.

1.25 L

P

2

R

+

In effect,

MPL

Γ

C R (Pin)

max

MPL

T

S

2

V

+ R

k

Vcs d

OHD

Vcs

where: k

is the multiplier gain

OHD

Now, as k

that is depending on the reference current

OHD

source I , is proportional to 1/R

:

ref

x

1

k

+ k2

OHD

R

ref

2

k

Vcs

OHD

k

Vcs

MPL

where: k2 is a constant

So:

T

MPL

OHD

Output

Sf

2

Vcs

R

V

+ R

k2

Γ

d

OHD

ref

V

MPL

Finally:

Dis

OHD

2

R

Vcs d

OHD

V

+

OHD

R

2.5 V

ref

Disabling

Block

where: Γ

is the OHD parameter as defined in the

specification. This is a constant equal to k2.

OHD

V

MPL

Dis

MPL

Now, as:

2.5 V

Vcs + R Ipk

S

MC44605

So, replacing Vcs and using the p equation:

on

2

R

3 R

Γ

R

OHD

dson

Figure 14. OHD and MPL

S

V

+

p

on

OHD

R

ref

So, by choosing the value of R

, the heating

OHD

Overheating Detection Section (O.H.D.)

corresponding to V is determined. If the MOSFET

ref

dissipation is such that the heating is higher than this

threshold, the “definitive inhibition latch” of the Disabling

Block is activated and so, the output gets definitively

disabled.

In the MPL block, the converter input power is calculated.

In the O.H.D. block, that is the power MOSFET heating

which is calculated, using the following equation:

1

3

2

p

+

R

Ipk d

on

dson

where: p are the power switch on−time losses

on

R

dson

is the conduction MOSFET resistor

d is the duty cycle

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16

MC44605

Consequently, by replacing V

value) in the last equation, the value R

deducted:

by 2.5 V (threshold

OHD

V

1

ref

to use, can be

OHD

104% I

0

ref

3.4% I

ref

2.5 R R

ref

dson

R

+

OHD

2

S

1

0

3 Γ

R (p

)

E.H.T.

on max

Dis

OVP

OHD

Q

V

S

WSCD

MPL

where: (p )

are the maximum on time losses that are

on max

Pin 12

R

acceptable.

V

CC

Delay

Disabling Block Section

4ꢀ S

Definitive

Inhibition

Latch

This section consists of a “definitive inhibition latch”

(directly supplied by the V ) that disables the output (the

cc

output is forced to zero).

2.5 V

In effect, this block aims at definitively disabling the

circuit when one of the following faults is detected:

— a Winding Short Circuit

Output

Buffer

— too high synchronization pulses

— a too high input power

MC44605

— a too high power switch (MOSFET) heating

The signals corresponding to these faults are high when a

fault is detected (for instance, when the input power is

Figure 15. Disabling Block

This latch is reset when the V falls down to about 3.0 V.

detected as too high, Dis

is high).

cc

MPL

In this case, if a new startup is performed, the circuit will

work normally (until this fault or another one is detected).

Practically, to re−start after a fault has shutdown the

circuit, the converter must be turned off for a time long

When one (or several) of these four faults is detected, a

current source charges C (with a certain duty cycle) and

ext

when its voltage becomes higher than V , the definitive

ref

inhibition latch is activated. Thus, the circuit gets

enough to enable the V capacitor discharge (repair time...).

definitively disabled after a delay depending on C

.

cc

ext

According to the detected fault, the current that charges

is not the same:

The typical values are:

— 260 ꢀ A for EHTOVP and WSCD

— 8.5 ꢀ A for OHD and MPL

Note: As V

is generally a really narrow pulse, it is

WSCD

C

ext

necessary to add a latch and a delay to build a 4 ꢀ s width

pulse when V becomes high.

WSCD

when R is equal to 10 kꢂ .

ref

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17

MC44605

Application Schematic

90 Vac to

264 Vac

1nF / 1KV

RFI

R1

Filter

4.7 Mꢂ

1ꢂ / 5W

C4....C7

1nF/500V

V

in

160 V/0.1 A

D1 ... D4

1N4007

100 ꢀ F

400 V

MR856

100 ꢀ F

2x150 Kꢂ//

47 Kꢂ

1.8 Mꢂ

47 nF

1N4934

70 V/0.2 A

47 kꢂ/2W

SYNC

1N4937

100 ꢀ F

25 V

1N4937

Laux

100 kꢂ

3.3 kꢂ

1ꢀ F

1.2 kꢂ

27 Kꢂ

120 pF

8

7

6

5

4

3

2

1

9

2.2 nF

40 V/0.5 A

10

11

12

13

14

15

16

1nF

1N4937

470 ꢀ F

1 ꢀ F

100 kꢂ

4.7 ꢀ F

Lp

105

kꢂ

4.7 ꢀF

10 nF

470

kꢂ

1N4148

1 nF

340 Kꢂ

470 pF

1305 V/0.65 A

MTA4N60E

1 kꢂ

1N4934

1000 ꢀ F

22 kꢂ

1N4937

470 ꢂ

39 ꢂ

10 kꢂ

100 ꢂ

330 ꢂ

8 V/0.5 A

0.22 ꢂ

1 kꢂ

22 kꢂ

10 kꢂ

220 nF

1N4934

1000 ꢀ F

2.2 kꢂ

270 ꢂ

226 kꢂ

MOC8103

10 kꢂ

1N4733

100 nF

V

in

2.2 kꢂ

6.8 nF

33 nF

TL431

3.6 kꢂ

65 W output SMPS controlled by the MC44605

Mains input range: 90 Vac <−> 264 Vac

Synchronization range: 30 kHz <−> 100 kHz

Orega Transformer ref. G5984−00

(Lp = 195 ꢀH)

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18

MC44605

Performances

Input Voltage

90−260 Vac

Synchronization Range

30 to 100 kHz

160 V

100 mA

200 mA

500 mA

650 mA

500 mA

70 V

40 V

Outputs

13.5 V

8.0 V

110 Vac (Input)

220 Vac

80%

83%

81%

82%

80%

30 kHz

60 kHz

110 Vac

Measured Efficiency

(Pout = 64 W)

220 Vac

110 Vac

100 kHz

220 Vac

110 Vac

220 Vac

2.0 W

3.2 W

Standby Losses

(No Load − Pout = 0)

EHTovp Threshold

28 V

110 Vac (Input)

220 Vac

86 W (Input)

87 W

30 kHz

110 Vac

90 W

Maximum Power

Limitation

60 kHz

220 Vac

95 W

110 Vac

94 W

100 kHz

220 Vac

110 W

30 kHz

85 V

Overheating Detection

(Pout = 64 W):

The input rms levels at which

the circuit detects an OHD case.

60 kHz

76 V

100 kHz

Winding Short Circuit

Detection

Fully Functional

(Tested by short circuiting one output diode or one transformer winding)

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19

MC44605

PACKAGE DIMENSIONS

PDIP−16

CASE 648−08

ISSUE T

NOTES:

−A−

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

16

1

9

8

B

S

5. ROUNDED CORNERS OPTIONAL.

INCHES

DIM MIN MAX

0.740 0.770 18.80 19.55

MILLIMETERS

F

C

L

MIN MAX

A

B

C

D

F

0.250 0.270

0.145 0.175

0.015 0.021

6.35

3.69

0.39

1.02

6.85

4.44

0.53

1.77

SEATING

PLANE

−T−

0.040

0.70

G

H

J

K

L

0.100 BSC

2.54 BSC

1.27 BSC

K

M

H

0.050 BSC

0.008 0.015

0.110 0.130

0.295 0.305

J

0.21

0.38

3.30

7.74

10

G

2.80

7.50

0

D 16 PL

M

0.25 (0.010)

T A

M

S

0

10

_

0.020 0.040

0.51

1.01

GreenLine is a trademark of Motorola, Inc.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

MC44605/D

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20


型号：	MC44605_06
厂家：	ONSEMI
描述：	High Safety, Latched Mode, GreenLine TM PWM Controller for (Multi) Synchronized Applications 高安全性，锁存模式， GREENLINE TM的PWM控制器（多）同步应用控制器
文件：	总20页 (文件大小：183K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC44605_06 [ONSEMI]

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