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MC5474HC4053 [ONSEMI]

Analog Multiplexers/ Demultiplexers;
MC5474HC4053
型号： MC5474HC4053
厂家： ONSEMI    ONSEMI
描述：

Analog Multiplexers/ Demultiplexers
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This document,  
MC74HC4051/D  
has been canceled and  
replaced by  
MC74HC4051A/D  
LAN was sent 9/28/01  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
Analog Multiplexers/  
Demultiplexers  
High–Performance Silicon–Gate CMOS  
The MC54/74HC4051, MC74HC4052 and MC54/74HC4053 utilize sili-  
con–gate CMOS technology to achieve fast propagation delays, low ON  
resistances, and low OFF leakage currents. These analog multiplexers/  
demultiplexers control analog voltages that may vary across the complete  
power supply range (from VCC to VEE).  
The HC4051, HC4052 and HC4053 are identical in pinout to the  
metal–gate MC14051B, MC14052B and MC14053B. The Channel–Select  
inputs determine which one of the Analog Inputs/Outputs is to be connected,  
by means of an analog switch, to the Common Output/Input. When the  
Enable pin is HIGH, all analog switches are turned off.  
MC54/74HC4051  
MC74HC4052  
MC54/74HC4053  
J SUFFIX  
CERAMIC PACKAGE  
16  
CASE 620–10  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
The Channel–Select and Enable inputs are compatible with standard  
CMOS outputs; with pullup resistors they are compatible with LSTTL  
outputs.  
These devices have been designed so that the ON resistance (Ron) is  
more linear over input voltage than Ron of metal–gate CMOS analog  
switches.  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751G–02  
16  
16  
For multiplexers/demultiplexers with channel–select latches, see  
HC4351, HC4352 and HC4353.  
1
1
•
•
•
•
•
•
Fast Switching and Propagation Speeds  
Low Crosstalk Between Switches  
Diode Protection on All Inputs/Outputs  
Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V  
Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V  
Improved Linearity and Lower ON Resistance Than Metal–Gate  
Counterparts  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
ORDERING INFORMATION  
MC54HCXXXXJ  
MC74HCXXXXN  
MC74HCXXXXD  
MC74HCXXXXDW  
MC74HCXXXXDT  
Ceramic  
Plastic  
SOIC  
SOIC Wide  
TSSOP  
•
•
•
Low Noise  
In Compliance With the Requirements of JEDEC Standard No. 7A  
Chip Complexity: HC4051 — 184 FETs or 46 Equivalent Gates  
HC4052 — 168 FETs or 42 Equivalent Gates  
HC4053 — 156 FETs or 39 Equivalent Gates  
FUNCTION TABLE – MC54/74HC4051  
Control Inputs  
LOGIC DIAGRAM  
MC54/74HC4051  
Select  
Single–Pole, 8–Position Plus Common Off  
Enable  
C
B
A
ON Channels  
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X0  
X1  
X2  
X3  
X4  
X5  
X6  
X7  
NONE  
13  
X0  
14  
X1  
L
15  
X2  
H
H
H
H
X
ANALOG  
INPUTS/  
OUTPUTS  
12  
1
MULTIPLEXER/  
DEMULTIPLEXER  
X3  
X4  
X5  
X6  
X7  
A
3
COMMON  
OUTPUT/  
INPUT  
L
X
V
H
H
X
5
2
4
X = Don’t Care  
Pinout: MC54/74HC4051 (Top View)  
11  
10  
9
X2  
X1  
X0  
X3  
A
B
C
9
CC  
CHANNEL  
SELECT  
INPUTS  
B
16  
15  
14  
13  
12  
11  
10  
C
6
ENABLE  
PIN 16 = V  
CC  
PIN 7 = V  
EE  
PIN 8 = GND  
1
2
3
4
5
6
7
8
X4  
X6  
X
X7  
X5 Enable  
V
EE  
GND  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
FUNCTION TABLE – MC74HC4052  
LOGIC DIAGRAM  
MC74HC4052  
Double–Pole, 4–Position Plus Common Off  
Control Inputs  
Select  
Enable  
B
A
ON Channels  
12  
X0  
L
L
L
L
H
L
L
H
H
X
L
H
L
H
X
Y0  
Y1  
Y2  
Y3  
X0  
X1  
X2  
X3  
14  
X1  
X2  
X3  
13  
X SWITCH  
Y SWITCH  
X
Y
15  
11  
COMMON  
OUTPUTS/INPUTS  
ANALOG  
INPUTS/OUTPUTS  
NONE  
1
5
Y0  
Y1  
Y2  
Y3  
A
X = Don’t Care  
3
2
4
Pinout: MC74HC4052 (Top View)  
10  
9
V
X2  
15  
X1  
14  
X
X0  
12  
X3  
11  
A
B
CHANNELĆSELECT  
INPUTS  
CC  
PIN 16 = V  
CC  
PIN 7 = V  
B
16  
13  
10  
9
EE  
PIN 8 = GND  
6
ENABLE  
1
2
3
4
5
6
7
8
Y0  
Y2  
Y
Y3  
Y1 Enable  
V
EE  
GND  
FUNCTION TABLE – MC54/74HC4053  
Control Inputs  
LOGIC DIAGRAM  
MC54/74HC4053  
Triple Single–Pole, Double–Position Plus Common Off  
Select  
Enable  
C
B
A
ON Channels  
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
Z0  
Y0  
Y0  
Y1  
Y1  
Y0  
Y0  
Y1  
Y1  
NONE  
X0  
12  
Z0  
Z0  
Z0  
Z1  
Z1  
Z1  
Z1  
X1  
X0  
X1  
X0  
X1  
X0  
X1  
X0  
X1  
14  
X
13  
X SWITCH  
L
H
H
H
H
X
2
1
L
Y0  
Y1  
15  
4
COMMON  
OUTPUTS/INPUTS  
ANALOG  
INPUTS/OUTPUTS  
Y
Z
Y SWITCH  
Z SWITCH  
H
H
X
5
3
Z0  
Z1  
X = Don’t Care  
11  
10  
9
A
B
C
CHANNELĆSELECT  
INPUTS  
PIN 16 = V  
CC  
PIN 7 = V  
PIN 8 = GND  
EE  
Pinout: MC54/74HC4053 (Top View)  
6
V
Y
X
X1  
X0  
A
B
C
9
CC  
ENABLE  
16  
15  
14  
13  
12  
11  
10  
NOTE: This device allows independent control of each switch.  
Channel–Select Input A controls the X–Switch, Input B controls  
the Y–Switch and Input C controls the Z–Switch  
1
2
3
4
Z
5
6
7
8
Y1  
Y0  
Z1  
Z0 Enable  
V
EE  
GND  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
Unit  
This device contains protection  
circuitry to guard against damage  
due to high static voltages or electric  
fields. However, precautions must  
be taken to avoid applications of any  
voltage higher than maximum rated  
voltages to this high–impedance cir-  
V
CC  
Positive DC Supply Voltage (Referenced to GND)  
– 0.5 to + 7.0  
– 0.5 to + 14.0  
V
(Referenced to V  
)
EE  
V
EE  
Negative DC Supply Voltage (Referenced to GND)  
Analog Input Voltage  
– 7.0 to + 5.0  
V
V
V
IS  
V
V
– 0.5 to  
EE  
+ 0.5  
CC  
cuit. For proper operation, V and  
in  
V
should be constrained to the  
V
Digital Input Voltage (Referenced to GND)  
DC Current, Into or Out of Any Pin  
– 0.5 to V + 0.5  
V
out  
in  
CC  
range GND v (V or V ) v V  
.
in  
out  
CC  
I
± 25  
mA  
mW  
Unused inputs must always be  
tied to an appropriate logic voltage  
P
Power Dissipation in Still Air, Plastic or Ceramic DIP†  
SOIC Package†  
750  
500  
450  
D
level (e.g., either GND or V ).  
Unused outputs must be left open.  
CC  
TSSOP Package†  
T
Storage Temperature Range  
– 65 to + 150  
_C  
_C  
stg  
T
Lead Temperature, 1 mm from Case for 10 Seconds  
Plastic DIP, SOIC or TSSOP Package  
Ceramic DIP  
L
260  
300  
* Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C  
Ceramic DIP: – 10 mW/_C from 100_ to 125_C  
SOIC Package: – 7 mW/_C from 65_ to 125_C  
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Positive DC Supply Voltage  
Min  
Max  
Unit  
V
CC  
(Referenced to GND)  
(Referenced to V  
2.0  
2.0  
6.0  
12.0  
V
)
EE  
V
EE  
Negative DC Supply Voltage, Output (Referenced to  
GND)  
– 6.0 GND  
V
V
Analog Input Voltage  
V
V
V
V
V
IS  
EE  
CC  
V
Digital Input Voltage (Referenced to GND)  
Static or Dynamic Voltage Across Switch  
Operating Temperature Range, All Package Types  
GND  
in  
CC  
V
IO  
*
1.2  
– 55 + 125  
V
T
_C  
ns  
A
t , t  
r
Input Rise/Fall Time  
(Channel Select or Enable Inputs)  
V
CC  
V
CC  
V
CC  
= 2.0 V  
= 4.5 V  
= 6.0 V  
0
0
0
1000  
500  
400  
f
* For voltage drops across switch greater than 1.2V (switch on), excessive V current may be  
CC  
drawn; i.e., the current out of the switch may contain both V and switch input components. The  
CC  
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) V = GND, Except Where Noted  
EE  
Guaranteed Limit  
V
CC  
–55 to 25°C ≤85°C ≤125°C  
V
Symbol  
Parameter  
Condition  
= Per Spec  
Unit  
V
IH  
Minimum High–Level Input Voltage,  
Channel–Select or Enable Inputs  
R
R
2.0  
4.5  
6.0  
1.50  
3.15  
4.20  
1.50  
3.15  
4.20  
1.50  
3.15  
4.20  
V
on  
on  
V
IL  
Maximum Low–Level Input Voltage,  
Channel–Select or Enable Inputs  
= Per Spec  
2.0  
4.5  
6.0  
0.3  
0.9  
1.2  
0.3  
0.9  
1.2  
0.3  
0.9  
1.2  
V
I
Maximum Input Leakage Current,  
Channel–Select or Enable Inputs  
V
V
= V or GND,  
6.0  
± 0.1  
± 1.0  
± 1.0  
µA  
µA  
in  
in  
CC  
= – 6.0 V  
EE  
I
Maximum Quiescent Supply  
Current (per Package)  
Channel Select, Enable and  
CC  
V
V
= V or GND;  
V
EE  
V
EE  
= GND  
= – 6.0  
6.0  
6.0  
2
8
20  
80  
40  
160  
IS  
CC  
= 0 V  
IO  
DC CHARACTERISTICS — Analog Section  
Guaranteed Limit  
–55 to 25°C ≤85°C ≤125°C  
Symbol  
Parameter  
Condition  
V
CC  
V
EE  
Unit  
R
Maximum “ON” Resistance  
V
V
= V or V ; V = V to  
4.5  
4.5  
6.0  
0.0  
– 4.5  
– 6.0  
190  
120  
100  
240  
150  
125  
280  
170  
140  
Ω
on  
in  
IL  
IH  
IS  
CC  
; I ≤ 2.0 mA  
EE  
S
(Figures 1, 2)  
V
V
= V or V ; V = V or  
4.5  
4.5  
6.0  
0.0  
– 4.5  
– 6.0  
150  
100  
80  
190  
125  
100  
230  
140  
115  
in  
IL  
IH  
IS  
CC  
(Endpoints); I ≤ 2.0 mA  
EE  
S
(Figures 1, 2)  
∆R  
Maximum Difference in “ON”  
Resistance Between Any Two  
Channels in the Same Package  
V
V
= V or V ;  
IH  
4.5  
4.5  
6.0  
0.0  
– 4.5  
– 6.0  
30  
12  
10  
35  
15  
12  
40  
18  
14  
Ω
on  
in  
IL  
= 1/2 (V – V );  
IS  
CC  
EE  
I
S
≤ 2.0 mA  
I
off  
Maximum Off–Channel Leakage  
Current, Any One Channel  
V
V
= V or V  
IH  
;
µA  
in  
IL  
= V – V  
;
6.0  
– 6.0  
0.1  
0.5  
1.0  
IO  
CC  
EE  
Switch Off (Figure 3)  
Maximum Off–Channel HC4051  
V
V
= V or V  
IH  
;
6.0  
6.0  
6.0  
– 6.0  
– 6.0  
– 6.0  
0.2  
0.1  
0.1  
2.0  
1.0  
1.0  
4.0  
2.0  
2.0  
in  
IL  
Leakage Current,  
Common Channel  
HC4052  
HC4053 Switch Off (Figure 4)  
= V – V  
;
IO  
CC  
EE  
I
on  
Maximum On–Channel HC4051  
V
= V or V  
;
IH  
6.0  
6.0  
6.0  
– 6.0  
– 6.0  
– 6.0  
0.2  
0.1  
0.1  
2.0  
1.0  
1.0  
4.0  
2.0  
2.0  
µA  
in  
IL  
Leakage Current,  
HC4052 Switch–to–Switch =  
HC4053 – V ; (Figure 5)  
Channel–to–Channel  
V
CC  
EE  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)  
L
r
f
Guaranteed Limit  
V
CC  
–55 to 25°C  
≤85°C  
≤125°C  
V
Symbol  
Parameter  
Unit  
t
t
t
t
,
Maximum Propagation Delay, Channel–Select to Analog Output  
(Figure 9)  
2.0  
4.5  
6.0  
370  
74  
63  
465  
93  
79  
550  
110  
94  
ns  
PLH  
t
PHL  
,
Maximum Propagation Delay, Analog Input to Analog Output  
(Figure 10)  
2.0  
4.5  
6.0  
60  
12  
10  
75  
15  
13  
90  
18  
15  
ns  
ns  
ns  
PLH  
t
PHL  
,
Maximum Propagation Delay, Enable to Analog Output  
(Figure 11)  
2.0  
4.5  
6.0  
290  
58  
49  
364  
73  
62  
430  
86  
73  
PLZ  
t
PHZ  
,
Maximum Propagation Delay, Enable to Analog Output  
(Figure 11)  
2.0  
4.5  
6.0  
345  
69  
59  
435  
87  
74  
515  
103  
87  
PZL  
t
PZH  
C
Maximum Input Capacitance, Channel–Select or Enable Inputs  
10  
35  
10  
35  
10  
35  
pF  
pF  
in  
C
Maximum Capacitance  
(All Switches Off)  
Analog I/O  
I/O  
Common O/I: HC4051  
HC4052  
130  
80  
130  
80  
130  
80  
HC4053  
50  
50  
50  
Feedthrough  
1.0  
1.0  
1.0  
Typical @ 25°C, V = 5.0 V, V = 0 V  
CC  
EE  
45  
80  
45  
C
Power Dissipation Capacitance (Figure 13)*  
HC4051  
HC4052  
HC4053  
pF  
PD  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)  
Limit*  
25°C  
‘52  
V
V
V
EE  
V
CC  
Symbol  
Parameter  
Condition  
= 1MHz Sine Wave; Adjust f Voltage to  
Unit  
BW  
Maximum On–Channel Bandwidth  
or Minimum Frequency Response  
(Figure 6)  
f
‘51  
‘53  
MHz  
in  
in  
Obtain 0dBm at V ; Increase f Frequency  
OS  
in  
80  
80  
80  
95  
95  
95  
120  
120  
120  
2.25  
4.50  
6.00  
–2.25  
–4.50  
–6.00  
Until dB Meter Reads –3dB;  
R = 50Ω, C = 10pF  
L
L
—
—
Off–Channel Feedthrough Isolation  
(Figure 7)  
f
= Sine Wave; Adjust f Voltage to Obtain  
2.25 –2.25  
4.50 –4.50  
–50  
–50  
–50  
dB  
in  
in  
0dBm at V  
IS  
f
in  
= 10kHz, R = 600Ω, C = 50pF 6.00 –6.00  
L L  
2.25 –2.25  
4.50 –4.50  
–40  
–40  
–40  
f
in  
= 1.0MHz, R = 50Ω, C = 10pF 6.00 –6.00  
L L  
Feedthrough Noise.  
Channel–Select Input to Common  
I/O (Figure 8)  
V
≤ 1MHz Square Wave (t = t = 6ns);  
2.25 –2.25  
4.50 –4.50  
25  
105  
135  
mV  
PP  
in  
r
f
Adjust R at Setup so that I = 0A;  
Enable = GND  
L
S
R = 600Ω, C = 50pF 6.00 –6.00  
L L  
2.25 –2.25  
4.50 –4.50  
R = 10kΩ, C = 10pF 6.00 –6.00  
35  
145  
190  
L
L
—
Crosstalk Between Any Two  
Switches (Figure 12)  
(Test does not apply to HC4051)  
f
= Sine Wave; Adjust f Voltage to Obtain  
2.25 –2.25  
4.50 –4.50  
–50  
–50  
–50  
dB  
in  
in  
0dBm at V  
IS  
f
in  
= 10kHz, R = 600Ω, C = 50pF 6.00 –6.00  
L
L
2.25 –2.25  
4.50 –4.50  
= 1.0MHz, R = 50Ω, C = 10pF 6.00 –6.00  
L L  
–60  
–60  
–60  
f
in  
THD  
Total Harmonic Distortion  
(Figure 14)  
f
= 1kHz, R = 10kΩ, C = 50pF  
%
in  
L
L
THD = THD  
– THD  
measured  
source  
V
V
= 4.0V sine wave  
2.25 –2.25  
4.50 –4.50  
6.00 –6.00  
0.10  
0.08  
0.05  
IS  
IS  
PP  
= 8.0V sine wave  
PP  
V
IS  
= 11.0V sine wave  
PP  
* Limits not tested. Determined by design and verified by qualification.  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
300  
250  
120  
100  
80  
125°C  
25°C  
200  
125°C  
150  
60  
25°C  
-ā55°C  
100  
40  
-ā55°C  
50  
20  
0
0
0
0.25 0.50 0.75  
1.0  
1.25  
1.5 1.75  
2.0 2.25  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V  
IS  
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V  
IS  
EE  
EE  
Figure 1a. Typical On Resistance, VCC – VEE = 2.0 V  
Figure 1b. Typical On Resistance, VCC – VEE = 4.5 V  
120  
105  
90  
75  
125°C  
125°C  
90  
60  
75  
25°C  
25°C  
60  
45  
-ā55°C  
45  
-ā55°C  
30  
30  
15  
0
15  
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0  
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V  
0
1.0  
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V  
EE  
2.0  
3.0  
4.0  
5.0  
6.0  
7.0  
8.0  
9.0  
IS  
EE  
IS  
Figure 1c. Typical On Resistance, VCC – VEE = 6.0 V  
Figure 1d. Typical On Resistance, VCC – VEE = 9.0 V  
80  
70  
PLOTTER  
125°C  
25°C  
60  
50  
40  
30  
20  
PROGRAMMABLE  
POWER  
SUPPLY  
MINI COMPUTER  
DC ANALYZER  
-
+
V
CC  
-ā55°C  
DEVICE  
UNDER TEST  
10  
0
ANALOG IN  
COMMON OUT  
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0  
GND  
V
EE  
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V  
IS  
EE  
Figure 1e. Typical On Resistance, VCC – VEE = 12.0 V  
Figure 2. On Resistance Test Set–Up  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
V
CC  
V
CC  
V
V
CC  
CC  
16  
16  
V
V
V
V
EE  
EE  
ANALOG I/O  
OFF  
OFF  
OFF  
OFF  
A
V
CC  
CC  
COMMON O/I  
NC  
COMMON O/I  
V
IH  
6
7
8
6
7
8
IH  
V
EE  
V
EE  
Figure 3. Maximum Off Channel Leakage Current,  
Any One Channel, Test Set–Up  
Figure 4. Maximum Off Channel Leakage Current,  
Common Channel, Test Set–Up  
V
CC  
V
OS  
V
V
CC  
V
CC  
16  
16  
0.1µF  
A
dB  
METER  
f
in  
ON  
ON  
N/C  
R
L
C *  
L
EE  
CC  
COMMON O/I  
OFF  
V
ANALOG I/O  
V
IL  
6
7
8
6
7
8
V
EE  
V
EE  
*Includes all probe and jig capacitance  
Figure 5. Maximum On Channel Leakage Current,  
Channel to Channel, Test Set–Up  
Figure 6. Maximum On Channel Bandwidth,  
Test Set–Up  
V
CC  
V
CC  
V
IS  
V
OS  
16  
16  
0.1µF  
dB  
METER  
R
L
f
in  
OFF  
ON/OFF  
OFF/ON  
COMMON O/I  
TEST  
POINT  
ANALOG I/O  
R
L
R
L
C *  
L
R
L
C *  
L
R
L
6
7
8
6
7
8
V
CC  
V
≤ 1 MHz  
11  
in  
t = t = 6 ns  
r
f
V
EE  
V
EE  
V
CC  
CHANNEL SELECT  
*Includes all probe and jig capacitance  
CHANNEL SELECT  
*Includes all probe and jig capacitance  
V
IL  
or V  
GND  
IH  
Figure 7. Off Channel Feedthrough Isolation,  
Test Set–Up  
Figure 8. Feedthrough Noise, Channel Select to  
Common Out, Test Set–Up  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
V
CC  
V
CC  
16  
V
CC  
ON/OFF  
OFF/ON  
COMMON O/I  
C *  
CHANNEL  
SELECT  
TEST  
POINT  
50%  
ANALOG I/O  
GND  
L
t
t
PHL  
PLH  
6
7
8
ANALOG  
OUT  
50%  
CHANNEL SELECT  
*Includes all probe and jig capacitance  
Figure 9a. Propagation Delays, Channel Select  
to Analog Out  
Figure 9b. Propagation Delay, Test Set–Up Channel  
Select to Analog Out  
V
CC  
16  
COMMON O/I  
C *  
ANALOG I/O  
TEST  
POINT  
V
CC  
ON  
ANALOG  
IN  
50%  
L
GND  
t
t
PHL  
PLH  
6
7
8
ANALOG  
OUT  
50%  
*Includes all probe and jig capacitance  
Figure 10a. Propagation Delays, Analog In  
to Analog Out  
Figure 10b. Propagation Delay, Test Set–Up  
Analog In to Analog Out  
t
t
POSITION 1 WHEN TESTING t  
AND t  
PZH  
POSITION 2 WHEN TESTING t AND t  
f
r
PHZ  
1
2
PLZ  
PZL  
V
CC  
90%  
50%  
10%  
ENABLE  
V
CC  
GND  
1kΩ  
V
CC  
16  
t
t
PLZ  
PZL  
HIGH  
IMPEDANCE  
1
2
ANALOG I/O  
ENABLE  
TEST  
POINT  
ON/OFF  
ANALOG  
OUT  
50%  
C *  
L
10%  
V
OL  
t
t
PHZ  
PZH  
6
7
8
V
OH  
90%  
ANALOG  
OUT  
50%  
HIGH  
IMPEDANCE  
Figure 11a. Propagation Delays, Enable to  
Analog Out  
Figure 11b. Propagation Delay, Test Set–Up  
Enable to Analog Out  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
V
CC  
V
IS  
A
V
CC  
16  
16  
R
L
V
OS  
ON/OFF  
OFF/ON  
COMMON O/I  
f
in  
ON  
NC  
ANALOG I/O  
0.1µF  
OFF  
V
EE  
R
L
R
L
C *  
L
C *  
L
V
CC  
R
L
6
7
8
6
7
8
11  
V
EE  
CHANNEL SELECT  
*Includes all probe and jig capacitance  
Figure 12. Crosstalk Between Any Two  
Switches, Test Set–Up  
Figure 13. Power Dissipation Capacitance,  
Test Set–Up  
0
-ā10  
-ā20  
-ā30  
-ā40  
V
IS  
FUNDAMENTAL FREQUENCY  
V
CC  
V
OS  
16  
0.1µF  
TO  
DISTORTION  
METER  
f
in  
ON  
R
L
C *  
L
-ā50  
-ā60  
DEVICE  
SOURCE  
6
7
8
-ā70  
-ā80  
V
EE  
-ā90  
*Includes all probe and jig capacitance  
-100  
1.0  
2.0  
3.125  
FREQUENCY (kHz)  
Figure 14a. Total Harmonic Distortion, Test Set–Up  
Figure 14b. Plot, Harmonic Distortion  
APPLICATIONS INFORMATION  
The Channel Select and Enable control pins should be at  
VCC or GND through a low value resistor helps minimize  
crosstalk and feedthrough noise that may be picked up by an  
unused switch.  
Although used here, balanced supplies are not a require-  
ment. The only constraints on the power supplies are that:  
VCC or GND logic levels. VCC being recognized as a logic  
high and GND being recognized as a logic low. In this exam-  
ple:  
VCC = +5V = logic high  
GND = 0V = logic low  
VCC – GND = 2 to 6 volts  
VEE – GND = 0 to –6 volts  
VCC – VEE = 2 to 12 volts  
and VEE ≤ GND  
The maximum analog voltage swings are determined by  
the supply voltages VCC and VEE. The positive peak analog  
voltage should not exceed VCC. Similarly, the negative peak  
analog voltage should not go below VEE. In this example, the  
difference between VCC and VEE is ten volts. Therefore,  
using the configuration of Figure 15, a maximum analog sig-  
nal of ten volts peak–to–peak can be controlled. Unused  
analog inputs/outputs may be left floating (i.e., not con-  
nected). However, tying unused analog inputs and outputs to  
When voltage transients above VCC and/or below VEE are  
anticipated on the analog channels, external Germanium or  
Schottky diodes (Dx) are recommended as shown in Figure  
16. These diodes should be able to absorb the maximum  
anticipated current surges during clipping.  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
V
CC  
V
CC  
+5V  
V
CC  
D
D
16  
x
16  
ON/OFF  
x
+5V  
-5V  
+5V  
-5V  
ANALOG  
SIGNAL  
ANALOG  
SIGNAL  
ON  
D
x
D
x
V
EE  
V
EE  
TO EXTERNAL CMOS  
CIRCUITRY 0 to 5V  
DIGITAL SIGNALS  
6
7
8
11  
10  
9
7
8
-5V  
V
EE  
Figure 15. Application Example  
Figure 16. External Germanium or  
Schottky Clipping Diodes  
+5V  
+5V  
16  
16  
+5V  
+5V  
+5V  
+5V  
ANALOG  
SIGNAL  
ANALOG  
SIGNAL  
ANALOG  
SIGNAL  
ANALOG  
SIGNAL  
ON/OFF  
ON/OFF  
V
EE  
V
EE  
V
EE  
V
EE  
+5V  
*
R
R
R
+5V  
6
7
8
11  
10  
9
6
7
8
11  
10  
9
LSTTL/NMOS  
CIRCUITRY  
LSTTL/NMOS  
CIRCUITRY  
V
EE  
V
EE  
* 2K ≤ R ≤ 10K  
HCT  
BUFFER  
a. Using Pull–Up Resistors  
b. Using HCT Interface  
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs  
11  
13  
X0  
LEVEL  
SHIFTER  
A
14  
X1  
10  
15  
X2  
LEVEL  
SHIFTER  
B
12  
X3  
9
1
LEVEL  
SHIFTER  
C
X4  
5
X5  
6
2
LEVEL  
SHIFTER  
ENABLE  
X6  
4
X7  
3
X
Figure 18. Function Diagram, HC4051  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
10  
12  
X0  
LEVEL  
SHIFTER  
A
B
14  
X1  
9
15  
X2  
LEVEL  
SHIFTER  
11  
X3  
13  
X
6
1
LEVEL  
SHIFTER  
ENABLE  
Y0  
5
Y1  
2
Y2  
4
Y3  
3
Y
Figure 19. Function Diagram, HC4052  
11  
10  
9
13  
LEVEL  
SHIFTER  
A
X1  
12  
14  
1
X0  
X
LEVEL  
SHIFTER  
B
Y1  
2
15  
3
Y0  
Y
LEVEL  
SHIFTER  
C
Z1  
5
4
Z0  
Z
6
LEVEL  
SHIFTER  
ENABLE  
Figure 20. Function Diagram, HC4053  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
OUTLINE DIMENSIONS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
ISSUE V  
–A  
–
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION L TO CENTER OF LEAD WHEN  
FORMED PARALLEL.  
16  
1
9
8
–B  
–
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE  
THE LEAD ENTERS THE CERAMIC BODY.  
L
C
INCHES  
MIN MAX  
0.750 0.785 19.05 19.93  
MILLIMETERS  
DIM  
A
B
C
D
E
MIN MAX  
0.240 0.295  
0.200  
0.015 0.020  
0.050 BSC  
6.10  
Ċ
0.39  
7.49  
5.08  
0.50  
–T  
Ċ
SEATING  
PLANE  
N
K
–
1.27 BSC  
F
0.055 0.065  
0.100 BSC  
1.40  
2.54 BSC  
1.65  
E
M
G
J
0.008 0.015  
0.125 0.170  
0.300 BSC  
0.21  
3.18  
7.62 BSC  
0.38  
4.31  
J 16 PL  
F
G
K
L
M
S
T B  
0.25 (0.010)  
D 16 PL  
15°  
0.040  
15°  
1.01  
M
N
0°  
0.020  
0°  
0.51  
M
S
0.25 (0.010)  
T
A
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
ISSUE R  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION L TO CENTER OF LEADS WHEN  
FORMED PARALLEL.  
–A  
–
16  
1
9
B
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.  
5. ROUNDED CORNERS OPTIONAL.  
8
INCHES  
MIN MAX  
0.740 0.770 18.80 19.55  
MILLIMETERS  
DIM  
A
MIN MAX  
F
C
L
B
C
D
F
0.250 0.270  
0.145 0.175  
0.015 0.021  
0.040 0.070  
0.100 BSC  
6.35  
3.69  
0.39  
1.02  
6.85  
4.44  
S
0.53  
1.77  
2.54 BSC  
1.27 BSC  
0.38  
SEATING  
PLANE  
–T  
G
H
J
–
0.050 BSC  
M
K
0.008 0.015  
0.110 0.130  
0.295 0.305  
0.21  
2.80  
7.50  
0°Ă  
H
J
K
L
3.30  
7.74  
G
D 16 PL  
M
S
0°Ă 10°  
0.020 0.040  
10°  
1.01  
M
M
0.25 (0.010)  
T
A
0.51  
D SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751B–05  
ISSUE J  
–A  
–
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
16  
9
–B  
–
P 8 PL  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
M
M
B
0.25 (0.010)  
1
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.127 (0.005) TOTAL  
IN EXCESS OF THE D DIMENSION AT  
MAXIMUM MATERIAL CONDITION.  
G
MILLIMETERS  
MIN MAX  
9.80 10.00  
INCHES  
MIN MAX  
DIM  
A
0.386 0.393  
0.150 0.157  
0.054 0.068  
0.014 0.019  
0.016 0.049  
0.050 BSC  
F
K
R X 45°  
B
3.80  
1.35  
0.35  
0.40  
4.00  
1.75  
0.49  
1.25  
C
D
C
F
1.27 BSC  
G
J
–T  
0.19  
0.10  
0.25  
0.25  
7°  
0.008 0.009  
0.004 0.009  
J
SEATING  
PLANE  
–
M
K
DĂ16ĂPL  
M
P
0°  
0°  
0.229 0.244  
7°  
5.80  
0.25  
6.20  
0.50  
M
S
S
A
0.25 (0.010)  
T
B
R
0.010 0.019  
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
OUTLINE DIMENSIONS  
DW SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751G–02  
ISSUE A  
–A–  
NOTES:  
1. DIMENSIONING AND TOLERANCING  
PER ANSI Y14.5M, 1982.  
16  
9
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD  
PROTRUSION.  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER  
SIDE.  
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN  
EXCESS OF D DIMENSION AT MAXIMUM  
MATERIAL CONDITION.  
–B–  
8X P  
M
M
B
0.010 (0.25)  
1
8
J
16X D  
MILLIMETERS  
INCHES  
MIN  
0.400  
M
S
S
B
DIM MIN  
MAX  
MAX  
0.411  
0.299  
0.104  
0.019  
0.035  
0.010 (0.25)  
T
A
A
B
C
D
F
10.15  
7.40  
2.35  
0.35  
0.50  
10.45  
F
7.60 0.292  
2.65 0.093  
0.49 0.014  
0.90 0.020  
R X 45  
_
G
J
1.27 BSC  
0.050 BSC  
0.25  
0.10  
0
0.32 0.010  
0.25 0.004  
0.012  
0.009  
7
C
K
M
P
R
7
10.55  
0
0.395  
–T–  
SEATING  
PLANE  
_
_
_
_
10.05  
0.25  
0.415  
0.029  
M
14X G  
K
0.75 0.010  
DT SUFFIX  
PLASTIC TSSOP PACKAGE  
CASE 948F–01  
ISSUE O  
16X KREF  
M
S
S
0.10 (0.004)  
T
U
V
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
S
0.15 (0.006) T  
U
K
K1  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.  
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR  
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER  
SIDE.  
16  
9
2X L/2  
J1  
4. DIMENSION B DOES NOT INCLUDE INTERLEAD  
FLASH OR PROTRUSION. INTERLEAD FLASH OR  
PROTRUSION SHALL NOT EXCEED  
B
–U–  
SECTION N–N  
L
0.25 (0.010) PER SIDE.  
J
5. DIMENSION K DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION  
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K  
DIMENSION AT MAXIMUM MATERIAL CONDITION.  
6. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
PIN 1  
IDENT.  
8
1
N
0.25 (0.010)  
7. DIMENSION A AND B ARE TO BE DETERMINED AT  
DATUM PLANE -W-.  
S
0.15 (0.006) T  
U
A
M
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN  
–V–  
MAX  
0.200  
0.177  
0.047  
0.006  
0.030  
N
A
B
4.90  
4.30  
---  
5.10 0.193  
4.50 0.169  
F
C
1.20  
---  
D
0.05  
0.50  
0.15 0.002  
0.75 0.020  
F
DETAIL E  
G
H
0.65 BSC  
0.026 BSC  
0.18  
0.09  
0.09  
0.19  
0.19  
0.28 0.007  
0.20 0.004  
0.16 0.004  
0.30 0.007  
0.25 0.007  
0.011  
0.008  
0.006  
0.012  
0.010  
J
J1  
K
–W–  
C
K1  
L
6.40 BSC  
_
0.252 BSC  
0
0.10 (0.004)  
M
0
8
8
_
_
_
DETAIL E  
H
SEATING  
PLANE  
–T–  
D
G
MC54/74HC4051 MC74HC4052 MC54/74HC4053  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes  
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular  
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,  
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or  
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be  
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.  
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or  
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold  
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable  
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim  
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.  
PUBLICATION ORDERING INFORMATION  
Literature Fulfillment:  
JAPAN: ON Semiconductor, Japan Customer Focus Center  
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031  
Phone: 81–3–5740–2700  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada  
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada  
Email: ONlit@hibbertco.com  
Email: r14525@onsemi.com  
ON Semiconductor Website: http://onsemi.com  
For additional information, please contact your local  
Sales Representative.  
N. American Technical Support: 800–282–9855 Toll Free USA/Canada  
MC74HC4051/D  

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SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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