MC642P [ONSEMI]
BRUSH DC MOTOR CONTROLLER, PDIP8, PLASTIC, DIP-8;
| 型号： | MC642P |
| 厂家： | 
ONSEMI |
| 描述： | BRUSH DC MOTOR CONTROLLER, PDIP8, PLASTIC, DIP-8 电动机控制 光电二极管 |
| 文件： | 总16页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC642 is a pulse width modulation (PWM) fan speed
controller for use with DC motors. It provides temperature
proportional speed control. A thermistor connected to the VIN input
furnishes the required control voltage of 1.25V to 2.65V for 0% to
100% PWM duty cycle. Minimum fan speed is set by a simple resistor
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divider on the V
input. An integrated Start–Up Timer ensures
MIN
reliable motor start–up at turn–on, coming out of Shutdown Mode, or
following a transient fault. A stalled, open, or unconnected fan causes
the MC642 to trigger its start–up timer once. If the fault persists, the
FAULT output goes low, and the device is latched in Shutdown Mode.
SO–8
D SUFFIX
CASE TBD
Features
• Shutdown Mode for Power Saving
PRELIMINARY INFORMATION
• Supports Low Cost NTC/PTC Thermistors
• Temperature Proportional Speed for Acoustic Control /
Longer Fan Life
• Fan Voltage Independent of MC642 Supply Voltage
• Fault Detection Circuits Protect Against Fan Failure and
Aid System Testing
• Operating Temperature Range: 0°C to +85°C
8–Pin DIP
P SUFFIX
CASE TBD
Typical Applications
• Power Supplies
PRELIMINARY INFORMATION
• Personal Computers
• UPS’s, Power Amplifiers, etc.
PIN CONFIGURATION
TYPICAL APPLICATION DIAGRAM
V
DD
V
V
V
8
7
6
5
1
2
3
4
IN
DD
C
MC642D
MC642P
F
OUT
V
FAULT
MIN
GND
+12 V
SENSE
D1
D2
+5 V
8
MC642
Reset
FAN
Q1
From
Temp
Sensor
V
DD
1
0
V
V
FAULT
in
1
6
Fault
MC642
Detected
R
BASE
ORDERING INFORMATION
V
min
out
3
7
5
Device
Package
Shipping
MC642DR2
8–Pin SOIC
2500 Tape/Reel
50 Tape/Reel
C
SENSE
GND
F
2
+
C
SENSE
R
(Optional)
SENSE
MC642P
8–Pin Plastic DIP
4
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
February, 2000 – Rev. 0
MC642/D
MC642
FUNCTIONAL BLOCK DIAGRAM
V
V
DD
+
–
V
IN
V
OTF
–
+
OTF
SHDN
–
+
OUT
Control
Logic
C
F
3 X T
PWM
Timer
Clock
Generator
FAULT
Start–Up
Timer
V
MIN
+
–
V
SHDN
Missing
Pulse
Detector
MC642
GND
+
–
SENSE
10 k
70 mV (typ.)
PIN DESCRIPTION
Pin No. Symbol
Description
The thermistor network (or other temperature sensor) connects to this input. A voltage range of 1.25V to 2.65V
1
V
IN
(typical) on this pin drives an active duty cycle of 0% to 100% on the V pin.
OUT
2
3
C
Positive terminal for the PWM ramp generator timing capacitor. The recommended C is 1µF for 30Hz PWM operation.
F
F
V
MIN
An external resistor divider connected to this input sets the minimum fan speed by fixing the minimum PWM duty
cycle (1.25V to 2.65V = 0% to 100%, typical). The MC642 enters Shutdown mode when 0 ≤ V
≤ V
. During
MIN
SHDN
Shutdown, the FAULT output is inactive, and supply current falls to 25µA (typical). The MC642 exits Shutdown
mode when V ≥ V . See Applications section for more details.
MIN REL
4
5
GND
Ground Terminal
SENSE
Pulses are detected at this pin as fan rotation chops the current through a sense resistor. The absence of pulses
indicates a fault.
6
FAULT
Fault (open collector) output. This line goes low to indicate a fault condition. When FAULT goes low due to a fan
fault, the device is latched in Shutdown Mode until deliberately cleared or until power is cycled. FAULT may be
connected to V
if a hard shutdown is desired. FAULT will also be asserted when the PWM reaches 100% duty
MIN
cycle, however the device will not latch itself off unless FAULT is tied to V
externally.
MIN
7
8
V
PWM signal output. This active high complimentary output connects to the base of an external NPN motor drive
transistor. This output has asymmetrical drive. – See Electrical Characteristics section.
OUT
V
Power Supply Input. May be independent of fan power supply. See Electrical Characteristics section.
DD
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MC642
ABSOLUTE MAXIMUM RATINGS*
Parameter
Value
Unit
Package Power Dissipation (T ≤ 70°C)
Plastic DIP
Small Outline (SOIC)
mW
A
730
470
Derating Factors
8.0
6.0
mW/°C
V
Supply Voltage
CC
Input Voltage, Any Pin
(GND – 0.3) to (V
0 to +85
+ 0.3)
V
Operating Temperature Range
Maximum Chip Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 Seconds)
°C
150
°C
–65 to +150
+300
°C
°C
* Maximum Ratings are those values beyond which damage to the device may occur.
ELECTRICAL CHARACTERISTICS (T
< T < T
, V = 3.0V to 5.5V, unless otherwise noted.)
MAX DD
MIN
A
Symbol
Characteristic
Min
Typ
Max
Unit
V
DD
Supply Voltage
3.0
—
5.5
V
I
I
I
Supply Current, Operating
mA
DD
—
0.5
1.0
Pins 3, 5, 7 Open, C = 1µF, V = V
F
IN
(CMAX)
Supply Current, Shutdown Mode
µA
µA
DD(SHDN)
—
25
—
—
Pins 1, 5, 6, 7 Open, C = 1µF, V = 0.35V (Note 1.)
F
IN
–1.0
1.0
V , V
IN MIN
Input Leakage (Note 1.)
IN
V
OUT
Output
t
—
—
—
—
50
50
µsec
µsec
µsec
V
V
Rise Time (I
= 5.0mA) (Note 1.)
= 1.0mA) (Note 1.)
R
OUT
OH
t
F
Fall Time (I
OH
OUT
t
Pulse Width (On V
) to Clear Fault Mode
(SHDN)
MIN
Specifications
30
1.0
5.0
—
—
—
—
—
—
V
, V
SHDN HYST
I
I
Sink Current at V
Output
mA
mA
OL
OUT
= 10% of V
DD
V
OL
Source Current at V
OUT
Output
OH
V
= 80% of V
DD
OH
V
V
V
V
V
, V , Inputs
IN MIN
, V
Input Voltage at V or V
IN
for 100% PWM Duty Cycle
2.5
1.3
—
2.65
1.4
—
2.8
1.5
V
V
V
V
C(MAX) OTF
C(SPAN)
SHDN
MIN
V
– V
C(MIN)
C(MAX)
Voltage Applied to V
to Guarantee Shutdown Mode
to Release Shutdown Mode
V
x 0.13
MIN
MIN
DD
Voltage Applied to V
REL
V
x 0.19
—
30
70
—
34
90
V
DD
= 5V
DD
Pulse–Width Modulator
F
PWM Frequency (C = 1.0µF)
26
50
Hz
F
Sense Input
V
SENSE Input Threshold Voltage with Respect to GND
mV
TH(SENSE)
Fault Output
V
Output Low Voltage (I
= 2.5mA)
OH
—
—
—
—
—
0.3
—
—
—
Hz
OL
t
t
t
Missing Pulse Detector Timeout
Startup Time
32/F
32/F
3/F
Sec
Sec
Sec
MP
STARTUP
DIAG
Diagnostic Timer Period
1. Guaranteed by design, not tested.
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MC642
DETAILED OPERATING DESCRIPTION
PWM
CAUTION: Shutdown mode is unconditional. i.e., the
fan will not activate regardless of the voltage on VIN. (Note:
The fan should not be shut down until all heat–producing
activity in the system is at a negligible level.)
The PWM (Pulse Width Modulation) circuit consists of a
ramp generator and threshold detector. The frequency of the
PWM is determined by the value of the capacitor connected
to the CF input. A frequency of 30Hz is recommended (CF
= 1µF). The PWM is also the timebase for the startup and
fault timer (see below). The PWM voltage control range is
1.25V to 2.65V (typical) for 0% to 100% output duty cycle.
SENSE Input
The SENSE input, pin 5, is connected to a low–value
current sensing resistor in the ground return leg of the fan
circuit. Duringnormal fanoperationcommutation occurs as
each pole of the fan is energized. This commutation causes
brief interruptions in the fan current, which is seen as pulses
across the sense resistor. When the device is not in
Shutdown Mode and pulses are not appearing at the SENSE
input, a fault condition exists.
V
Output
OUT
The VOUT pin is designed to drive a low–cost transistor or
MOSFET as the low side power switching element in the
system. Various examples of driver circuits are shown in the
The short, rapid changes in fan current (high dI/dt) cause
following pages.
This output has asymmetric
correspondingdV/dt pulses across the sense resistor, RSENSE
.
complementary drive and is optimized for driving NPN
transistors or N–channel MOSFET’s. Since the system
relies on PWM rather than linear power control, the
dissipation in the power switch is kept to a minimum.
Generally, very small devices (TO–92 or SOT package) will
suffice. (See Output Drive Transistor Selection paragraph in
Applications Information section.)
The waveform on RSENSE is differentiated and converted to
a logic–level pulse–train by CSENSE and the internal signal
processing circuitry (See Figure 1). The presence and
frequency of this pulse–train is a direct indication of fan
operation. See the Applications Information section for
more details.
FAULT Output
Start–Up Timer
The MC642 detects faults in two ways:
To ensure reliable fan startup, the StartUp Timer turns the
VOUT output on for 32 cycles of the PWM whenever the fan
is started from the off–state. This occurs at power–up and
whencoming out of shutdown mode. IfthePWMfrequency
is 30Hz (CF = 1µF), the resulting start–up time will be about
onesecond. IfaFaultisdetected(seebelow), theDiagnostic
Timer is triggered once, followed by the Startup–Up Timer.
If the fault persists, the device is shut down. See FAULT
Output below.
(1) Pulses appearing at SENSE due to the PWM turning on
are blanked and the remaining pulses are filtered by a
missing pulse detector. If consecutive pulses are not
detected for 32 PWM cycles (1 Sec if CF = 1µF), the
Diagnostic Timer is activated and VOUT is driven
continuously for three PWM cycles (100msec if CF = 1µF).
If a pulse is not detected within this window, the
Startup–Timer is triggered. This should clear a transient
fault condition. If the Missing Pulse Detector times out
again, the PWM is stopped and FAULT goes low. When
FAULT is activated due to this condition, the device is
latched in Shutdown mode and will remain off indefinitely.
(Diodes D1, D2 and resistor R5 (See Figure 1) are provided
to ensure that fan restarting is the result of a fan fault, and not
an over–temperature fault. A CMOS logic OR gate may be
substituted for these components if available).
Shutdown Control (Optional)
When VMIN (pin 3) is pulled below VSHDN, the MC642 will
go into Shutdown mode. This can be accomplished by
driving VMIN with an open drain logic signal or using an
external transistor as shown in Figure 1. All functions are
suspended until the voltage on VMIN becomes higher than
VREL (0.85V @ VDD = 5.0V). Pulling VMIN below VSHDN will
WhenFAULTisactivatedduetothiscondition, thedevice
is latched in Shutdown mode and will remain off
indefinitely. Important: At this point, action must be
taken to restart the fan by momentarily pulling VMIN
below VSHDN, or by cycling system power. In either case
the fan cannot be permitted to remain disabled due to a
fault condition, as severe system damage could result. If
the fan cannot be restarted, the system should be shut
down. The MC642 may be configured to continuously
attempt fan restarts if so desired.
always result in complete device shutdown and reset. The
FAULT output is unconditionally inactive in Shutdown
mode.
Asmallamountofhysteresis, typicallyonepercentofVDD
(50mV at VDD = 5.0V), is designed into the VSHDN/VREL
threshold. The levels specified for VSHDN and VREL in the
Electrical Characteristics section include this hysteresis
plus adequate margin to account for normal variations in the
absolute value of the threshold and hysteresis.
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MC642
V
DD
R5
10 k
+12 V
0.1
F
D1
D2
+5 V
8
MC642
Reset
FAN
Q1
V
DD
+5 V
1
0
From
V
V
FAULT
in
1
3
2
6
7
5
Temp
Sensor
R
R3
MC642
BASE
Fault Detected
V
min
out
0.01
C
B
R1
From
C
SENSE
GND
R4
F
System
Shutdown
Controller
+
C
SENSE
(Optional)
C
1
R
F
SENSE
F
4
* The parallel combination of R3 and R4 must be > 10 k.
Figure 1. Typical Fan Control Application
Continuous restart mode is enabled by connecting the
FAULT output to VMIN through a 0.1µF capacitor as shown
in Figure 1. When so connected, the MC642 automatically
attempts to restart the fan whenever a fault condition occurs.
When the fault output is driven low, the VMIN input is
momentarily pulled below VSHDN, initiating a reset and
clearing the fault condition. Normal fan startup is then
attempted as previously described. The FAULT output may
be connected to external logic (or the interrupt input of a
microcontroller) to shut down the MC642 if multiple fault
pulses are detected at approximately one second intervals.
(2) FAULT is also asserted when the PWM control
voltage applied to VIN becomes greater than that needed to
drive 100% duty cycle (see ElectricalCharacteristics). This
indicates that the fan is at maximum drive and the potential
exists for system overheating. Either heat dissipation in the
system has gone beyond the cooling system’s design limits
or some other fault exists such as fan bearing failure or an
airflow obstruction. This output may be treated as a System
Overheat warning and used to trigger system shutdown.
However in this case, the fan will continue to run even when
FAULT is asserted. If a shutdown is desired, FAULT may be
connected to VMIN outside the device. This will latch the
MC642 in Shutdown Mode when any fault occurs.
SYSTEM BEHAVIOR
The flowcharts describing the MC642’s behavioral
algorithm are shown in Figure 3. They can be summarized
as follows:
Power–Up
(1) Assumingthe device is not being held in Shutdown
mode (VMIN > VREL):
(2) Turn VOUT output on for 32 cycles of the PWM
clock. This ensures that the fan will start from a dead stop.
(3) During this Start–up time, if a fan pulse is detected
then branch to Normal Operation; if none are received.
(4) Activate the 32–cycle Start–up Timer one more
time and look for fan pulses; if a fan pulse is detected,
proceed to Normal Operation; if none are received....
(5) Proceed to Fan Fault
(6) End
After this period elapses, the MC642 begins normal
operation.
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5
MC642
+5 V*
1
C
F
+12 V
R1
NTC
B
0.01
R2
FAN
Q1
C
B
8
V
DD
Thermal
Shutdown
V
V
FAULT
in
1
3
2
6
7
5
R
R3
MC642
BASE
V
out
min
0.01
C
B
Shutdown
C
SENSE
GND
R4
F
+
C
SENSE
(Optional)
C
1
R
F
SENSE
F
4
NOTE: *See Cautions Regarding Latch–Up Considerations in the Applications Section.
Figure 2. Typical Fan Control Application using NTC thermistor
Normal Operation
(7) Activate the 3–cycle Diagnostic Timer and look
for pulses; if a fan pulse is detected, branch back to the
start of the loop; if none are received...
Normal Operation is an endless loop which may only be
exited by entering Shutdown mode or Fan Fault. The loop
can be thought of as executing at the frequency of the
oscillator and PWM.
(8) Activate the 32–cycle Startup Timer and look for
pulses; if a fan pulse is detected, branch back to the start of
the loop; if none are received...
(1) Reset the Missing Pulse Detector
(2) Is MC642 in Shutdown? If so...
a. VOUT duty–cycle goes to zero.
b. FAULT is disabled.
(9) Quit Normal Operation and go to Fan Fault.
(10) End
Fan Fault
c. Exit the loop and wait for VMIN > VREL to
resume operation (indistinguishable from Power–Up).
Fan Fault is essentially an infinite loop wherein the
MC642 is latched in Shutdown Mode. This mode can only
be released by a Reset, i.e., VMIN being brought below VSDHN
then above VREL, or by power–cycling.
,
(3) If an over–temperature fault occurs (VIN > VOTF
then activate FAULT; release FAULT when VIN < VOTF
)
.
(1) While in this state, FAULT is latched on (low), and
the VOUT output is disabled.
(4) Drive VOUT to a duty–cycle porportional to greater
of VIN and VMIN on a cycle by cycle basis.
(2) A Reset sequence applied to the VMIN pin will exit
the loop to Power Up.
(5) If a fan pulse is detected, branch back to the start of
the loop.
(3) End
(6) If the missing pulse detector times out ...
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MC642
Normal
Operation
Power–Up
Clear
Missing Pulse
Detector
Power–On
Reset
FAULT = 1
YES
SHDN
Shutdown
V
< V
IN
V
= 0
OUT
YES
Shutdown
V
< V
SHDN?
IN
V
= 0
OUT
NO
NO
NO
V
> V
REL?
IN
NO
V
> V
REL
IN
Initiate Start–
Up Timer
(1 Sec)
YES
YES
Power–Up
YES
Initiate Start–
Up Timer
(1 Sec)
NO
Fan Pulse
Detected?
V
> V
OTF?
IN
FAULT = 0
NO
YES
YES
Fan Pulse
Detected?
V
OUT
Proportional
To Greater
of V or V
Normal
Operation
NO
IN
MIN
Fan Fault
YES
NO
Fan Pulse
Detected?
M.P.D.
Expired?
Fan Fault
NO
YES
Initiate
Diagnostic Timer
(100 mSec)
FAULT = Low,
Disabled
V
OUT
YES
NO
Initiate Start–
Up Timer
(1 Sec)
NO
Fan Pulse
Detected?
NO
Cycling
Power?
V
< V
IN
SHDN?
YES
Fan Pulse
Detected?
YES
YES
NO
NO
V
> V
REL?
IN
Fan Fault
YES
Power–Up
Figure 3. MC642 Behavioral Algorithm Flowchart
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MC642
APPLICATIONS INFORMATION
Designing with the MC642 involves the following:
(5) If Shutdown capability is desired, the drive
requirements of the external signal or circuit must be
considered.
(1) The temp sensor network must be configured to
deliver 1.25V to 2.65V on VIN for 0% to 100% of the
temperature range to be regulated.
Temperature Sensor Design
The temperature signal connected to VIN must output a
voltage in the range of 1.25V to 2.65V (typical) for 0% to
100% of the temperature range of interest. The circuit of
Figure 4 is a convenient way to provide this signal.
(2) The minimum fan speed (VMIN) must be set.
(3) The output drive transistor and associated circuitry
must be selected.
(4) The Sense Network, RSENSE and CSENSE, must be
designedformaximumefficiencywhiledeliveringadequate
signal amplitude.
V
DD
V
DD
I
DIV
T1
R1
R2
R1
I
IN
V
MIN
I
V
in
DIV
R2
GND
Figure 4. Temperature Sensing Circuit
Figure 5. V
Circuit
MIN
V
DD
V
DD
FAN
FAN
R
R
BASE
BASE
Q1
Q1
V
OH
= 80% V
DD
V
OUT
+
V
–
R(BASE)
+
V
–
BE(SAT)
SENSE
+
C
SENSE
(0.1 F Typ.)
V
R
R
SENSE
R(SENSE)
–
SENSE
GND
GND
Figure 6. Circuit for Determining R
BASE
Figure 7. SENSE Network
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MC642
Figure 4 illustrates a simple temperature dependent
voltage divider circuit. T1 is a conventional NTC
5.0V
–4
= 1e A =
I
, therefore
DIV
thermistor, andR1andR2arestandardresistors. Thesupply
voltage, VDD, is divided between R2 and the parallel
combination of T1 and R1. (For convenience, the parallel
combination of T1 and R1 will be referred to as RTEMP.) The
resistance of the thermistor at various temperatures is
obtained from the manufacturer’s specifications.
Thermistors are often referred to in terms of their resistance
at 25°C. A thermistor with a 25°C resistance on the order of
R1 + R2
(4.)
5.0V
–4
R1 + R2 =
= 50,000 = 50k
1e
A
We can further specify R1 and R2 by the condition that the
divider voltage is equal to our desired VMIN. This yields the
following equation:
100k will result in reasonable values for R1, R2, and IDIV
.
In order to determine R1 and R2, we must specify the fan
duty–cycle, i.e. VIN, at any two temperatures. Equipped with
these two points on the system’s operating curve and the
thermistor data, we can write the defining equations:
R1
(5.)
V
=V x
DD
MIN
R1 + R2
Solving for the relationship between R1 and R2 results in
the following equation:
V
x R2
DD
= V(t1)
= V(t2)
R
R
(t1) + R2
TEMP
(1.)
V
– V
DD
MIN
(6.)
R1 = R2 x
V
x R2
DD
V
MIN
(t2) + R2
TEMP
In the case of this example, R1 = (1.762) R2. Substituting
this relationship back into Equation 4 yields the resistor
values:
Where t1 and t2 are the chosen temperatures and RTEMP is
the parallel combination of the thermistor and R1. These
two equations permit solving for the two unknown
variables, R1 and R2. Note that resistor R1 is not absolutely
necessary, but it helps to linearize the response of the
network.
R2 = 18.1k , and
R1 = 31.9k
Minimum Fan Speed
In this case, the standard values of 32k and 18k are
very close to the calculated values and would be more than
adequate.
A voltage divider on VMIN sets the minimum PWM duty
cycle and, thus, the minimum fan speed. As with the VIN
input, 1.25V to 2.65V corresponds to 0% to 100% duty
cycle. Assuming that fan speed is linearly related to
duty–cycle, the minimum speed voltage is given by the
equation:
One boundary condition which may impact the selection
of the minimum fan speed is the irregular activation of the
Diagnostic Timer due to the MC642 “missing” fan
commutation pulses at low speeds. Typically, this only
occurs at very low duty–cycles (25% or less). It is a natural
consequence of low PWM duty–cycles. Recall that the
SENSE function detects commutation of the fan as
disturbances in the current through RSENSE. These can only
occur when the fan is energized, i.e., VOUT is “on”. At very
low duty–cycles, the VOUT output is “off” most of the time.
The fan may be rotating normally, but the commutation
events are occuring during the PWM’s off–time.
Minimum Speed
V
=
x (1.4V) + 1.25V (2.)
MIN
Full Speed
Forexample, if2500RPMequatesto100%fanspeed, and
a minimum speed of 1000 RPM is desired, then the VMIN
voltage is:
The phase relationship between the fan’s commutation
and the PWM edges tends to “walk around” as the system
operates. At certain points, the MC642 may fail to capture
a pulse within the 32–cycle Missing Pulse Detector window.
When this happens, the 3–cycle Diagnostic Timer will be
activated, the VOUT output will be active continuously for
three cycles and, if the fan is operating normally, a pulse will
be detected. If all is well, the system will return to normal
operation. There is no harm in this behavior, but it may be
1000
V
=
x (1.4V) + 1.25V = 1.81V
(3.)
MIN
2500
The VMIN voltage may be set using a simple resistor
divider as shown in Figure 5. Per the Electrical
Characteristics, the leakage current at the VMIN pin is no
more than 1µA. It would be very conservative to design for
a divider current, IDIV, of 100µA. If VDD = 5.0V then...
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9
MC642
audible to the user as the fan will accelerate briefly when the
Diagnostic Timer fires. For this reason, it is recommended
that VMIN be set no lower than 1.8V.
Table 1. R vs. Fan Current
SENSE
Nominal Fan Current (mA)
R
(
SENSE
50
9.1
SENSE Network (R
and C )
SENSE
SENSE
100
150
200
250
300
350
400
450
500
4.7
3.0
2.4
2.0
1.8
1.5
1.3
1.2
1.0
The network comprised of RSENSE and CSENSE allow the
MC642 to detect commutation of the fan motor. This
network can be thought of as a differentiator and threshold
detector. The function of RSENSE is to convert the fan current
into a voltage. CSENSE serves to AC–couple this voltage
signal and provide a ground–referenced input to the SENSE
pin. Designing a proper SENSE Network is simply a matter
of scaling RSENSE to provide the necessary amount of gain,
i.e., the current–to–voltage conversion ratio. A 0.1µF
ceramic capacitor is recommended for CSENSE. Smaller
values require larger sense resistors, and higher value
capacitors are bulkier and more expensive. Using a 0.1µF
results in reasonable values for RSENSE. Figure 7 illustrates
a typical SENSE Network. Figure 8 shows the waveforms
observed using a typical SENSE Network.
Table 1 lists the recommended values of RSENSE according
to the nominal operating current of the fan. Note that the
current draw specified by the fan manufacturer may not be
the fan’snominaloperatingcurrent, butmaybeaworst–case
rating for near–stall conditions. The values in the table refer
to actual average operating current. If the fan current falls
between two of the values listed, use the higher resistor
value. The end result of employing Table 1 is that the signal
developedacross the sense resistor is approximately 450mV
in amplitude.
Figure 8. SENSE Waveforms
V
DD
V
DD
V
DD
FAN
FAN
FAN
R
BASE
R
BASE
Q1
V
OUT
Q1
Q1
V
OUT
V
OUT
Q2
R
R
SENSE
SENSE
R
SENSE
GND
a) Single Bipolar Transistor
GND
b) Darlington Transistor Pair
GND
c) N–Channel MOSFET
Figure 9. Output Drive Transistor Circuit Topologies
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10
MC642
Output Drive Transistor Selection
A base–current limiting resistor is required with bipolar
transistors. This is shown in Figure 6. The correct value for
this resistor can be determined as follows: (see Figure 6).
The MC642 is designed to drive an external transistor for
modulating power to the fan. This is shown as “Q1” in
Figures 2, 6, 7, 9, 10, and 11. The VOUT pin has a minimum
source current of 5mA and a minimum sink current of 1mA
atVDD =5.0V. BipolartransistorsorMOSFET’smaybeused
as the power switching element as shown below. When high
current gain is needed to drive larger fans, two transistors
may be used in a Darlington configuration. These circuit
topologies are shown in Figure 9: (a) shows a single NPN
transistor used as the switching element; (b) Illustrates the
Darlington pair; and (c) shows an N–channel MOSFET.
One major advantage of the MC642’s PWM control
scheme versus linear speed control is that the dissipation in
the pass element is kept very low. Generally, low–cost
devices in very small packages such as TO–92 or SOT, can
be used effectively. For fans with nominal operating
currents of no more than 200mA, a single transistor usually
suffices. Above 200mA, the Darlington or MOSFET
solution is recommended. For the fan sensing function to
work correctly it is imperative that the pass transistor be
fully saturated when “on”. The minimum gain (hFE) of the
transistor in question must be adequate to fully saturate the
transistor when passing the full fan current while being
driven within the 5mA IOH of the VOUT output.
Table 2 gives examples of some commonly available
transistors. This table is a guide only. There are many
transistor types which might work as well as those listed.
The only critical issues when choosing a device to use as Q1
are: (1) the breakdown voltage, VCE(BR), must be large
enough to stand off the highest voltage applied to the fan
(NOTE: this may be when the fan is off!); (2) the gain (hFE)
must be high enough for the device to remain fully saturated
while conducting the maximum expected fan current and
being driven with no more than 5mA of base/gate drive at
maximum temperature; (3) rated fan current draw must be
within the transistor’s current handling capability; and (4)
power dissipation must be kept within the limits of the
chosen device.
V
= V
+ V
+ V
BE(SAT)
OH
SENSE
X R
RBASE
V
= I
RSENSE FAN
SENSE
X I
(7.)
V
= R
RBASE
BASE BASE
/ h
I
= I
BASE FAN FE
VOH is specified as 80% of VDD in the Electrical
Characteristics table; VBE(SAT) is given in the transistor
datasheet. It is now possible to solve for RBASE
.
V
– V
BE(SAT)
– V
RSENSE
OH
(8.)
R
=
BASE
I
RBASE
Some applications require the fan to be powered from the
negative 12V supply to keep motor noise out of the positive
voltage power supplies. As shown in Figure 10, Zener diode
D2 offsetsthe –12V power supply voltage holding transistor
Q1 OFF when VOUT is LOW. When VOUT is HIGH, the
voltage at the anode of D2 increases by VOH, causing Q1 to
turn ON. Operation is otherwise the same as the case of fan
operation +12V.
Latch–up Considerations
As with any CMOS IC, the potential exists for latch–up if
signals are applied to the device which are outside the power
supply range. This is of particular concern during power–up
if the external circuitry, such as the sensor network, VMIN
divider, shutdown circuit, or fan, are powered by a supply
different from that of the MC642. Care should be taken to
ensure that the MC642’s VDD supply powers–up first. If
possible, the networks attached to VIN and VMIN should
connect to the VDD supply at the same physical location as
the IC itself. Even if the IC and any external networks are
powered by the same supply, physical separation of the
connecting points can result in enough parasitic capacitance
and/or inductance in the power supply connections to delay
one power supply “routing” versus another.
Power Supply Routing and Bypassing
Noise present on the VIN and VMIN inputs may cause
erroneous operation of the FAULT output. As a result, these
inputs should be bypassed with a 0.01µF capacitor mounted
as close to the package as possible. This is particularly true
of VIN, which usually is driven from a high impedance
source (such as a thermistor). In addition, the VDD input
should be bypassed with a 1µF capacitor. Grounds should be
kept as short as possible. To keep fan noise off the MC642
groundpin, individualgroundreturnsfortheMC642andthe
low side of the fan current sense resistor should be used.
Table 2. Transistors for Q1
Device
VBE(SAT) MIN hFE VBR(CEO) IC
RBASE
( )
MPS2222
MPS2222A
2N4400
1.3
1.2
100
100
50
30
40
40
40
25
40
150
150
150
150
500
500
800
800
820
820
780
780
0.95
0.95
1.2
2N4401
100
50
MPS6601
MPS6602
1.2
50
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11
MC642
5 V
V
DD
FAN
R2
2.2 k
MC642
Q1
V
out
D2
12 V
Zener
R4
10 k
R3
2.2
GND
–12 V
Figure 10. Powering Fan From –12V Supply
Design Example (Figure 11)
Limit the divider current to 100µA from
which R5 = 33k and R6 = 18k
Step 1. Circulate R1 and R2 based on using an NTC
having a resistance of 4.6k at TMIN and
1.1k at TMAX
.
Step 3. Design the output circuit
R1 = 75k
R2 = 1k
Maximum fan motor current = 250mA. Q1
beta is chosen at 100 from which R7 = 1.5k
Step 2. Set minimum fan speed
VMIN = 1.8V
+5 V
+5 V
NTC
10 k
@ 25°C
+12 V
FAN
R1
R2
1
C
F
B
+
0.01
F
C
B
8
4
V
CC
GND
+5 V
System
Q1
V
V
FAULT
in
Fault
1
3
2
6
7
5
R7
1.5 k
R5
33 k
MC642
V
out
min
0.01
C
B
R8
10 k
Fan
Shutdown
Q2
C
SENSE
R6
F
+
C
SENSE
R
SENSE
2.2
(Optional)
C1
0.1
F
1
F
Figure 11. Design Example
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12
MC642
MC642 as a Microcontroller Peripheral
(Figure 12)
translates the 3–bit code from the processor’s outputs into a
1.6V DC control signal. (A monolithic DAC or digital pot
may be used instead of the circuit shown.)
In a system containing a microcontroller or other host
intelligence, the MC642 can be effectively managed as a
CPU peripheral. Routine fan control functions can be
performed by the MC642 without processor intervention.
The micro–controller receives temperature data from one or
more points throughout the system. It calculates a fan
operating speed based on an algorithm specifically designed
for the application at hand. The processor controls fan speed
using complementary port bits I/01 through I/03. Resistors
R1 through R6 (5% tolerance) form a crude 3–bit DAC that
With V
set to 1.8V, the MC642 has a minimum
MIN
operating speed of approximately 40% of full rated speed
when the processor’s output code is 000. Output codes 001
to 111 operate the fan from roughly 40% to 100% of full
speed. An open drain output from the processor can be used
to reset the MC642 following detection of a fault condition.
The FAULT output can be connected to the processor’s
interrupt input, or to an I/O pin for polled operation.
+5 V
+12 V
Open
Drain
Output
(RESET) (Optional)
I/O
I/O
I/O
I/O
0
1
2
3
+5 V
R1
+
110 k
(MSB)
FAN
V
V
DD
in
+
8
7
1
F
C
0.01
C
1
B
B
F
R2
240 k
–
R9
MC642
CMOS
Outputs
1.5 k
2N2222A
C
V
out
F
R3
360 k
+5 V
2
F
+
R7
33 k
1
R10
10 k
(LSB)
+5 V
R4
18 k
V
min
FAULT
3
F
6
5
C
0.01
+5 V
B
CMOS
Microcontroller
R8
18 k
R5
1.5 k
R6
1 k
GND
SENSE
4
0.1
F
R11
2.2
GND
INT
Figure 12. Design Example
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13
MC642
PACKAGE DIMENSIONS
8–Pin DIP
PLASTIC PACKAGE
CASE TBD
ISSUE TBD
PIN 1
.260 (6.60)
.240 (6.10)
.045 (1.14)
.030 (0.76)
.070 (1.78)
.045 (1.14)
.310 (7.87)
.290 (7.37)
.400 (10.16)
.348 (8.84)
.200 (5.08)
.140 (3.56)
.040 (1.02)
.015 (0.38)
.008 (0.20)
.020 (0.51)
3° MIN.
.150 (3.81)
.115 (2.92)
.400 (10.16)
.310 (7.87)
.110 (2.79)
.090 (2.29)
.022 (0.56)
.015 (0.38)
Dimensions: inches (mm)
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14
MC642
PACKAGE DIMENSIONS
8–Pin SOIC
PLASTIC PACKAGE
CASE TBD
ISSUE TBD
PIN 1 indicated by dot and/or beveled edge
.244 (6.20)
.228 (5.79)
.157 (3.99)
.150 (3.81)
.050 (1.27) TYP.
.197 (5.00)
.189 (4.80)
.069 (1.75)
.053 (1.35)
.010 (0.25)
.007 (0.18)
8
MAX.
.010 (0.25)
.004 (0.10)
.050 (1.27)
.016 (0.40)
.018 (0.46)
.014 (0.36)
Dimensions: inches (mm)
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15
MC642
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment:
CENTRAL/SOUTH AMERICA:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email: ONlit–spanish@hibbertco.com
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
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Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
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German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)
Email: ONlit–german@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549
Phone: 81–3–5740–2745
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)
Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)
Email: ONlit@hibbertco.com
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
For additional information, please contact your local
Sales Representative.
*Available from Germany, France, Italy, England, Ireland
MC642/D
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