MC74AC299DTR2 [ONSEMI]
IC AC SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, TSSOP-20, Shift Register;
| 型号： | MC74AC299DTR2 |
| 厂家： | 
ONSEMI |
| 描述： | IC AC SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, TSSOP-20, Shift Register 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74AC299, MC74ACT299
8-Input Universal
Shift/Storage Register with
Common Parallel I/O Pins
The MC74AC299/74ACT299 is an 8–bit universal shift/storage
register with 3–state outputs. Four modes of operation are possible:
hold (store), shift left, shift right and load data. The parallel load inputs
and flip–flop outputs are multiplexed to reduce the total number of
package pins. Additional outputs are provided for flip–flops Q , Q to
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PDIP–20
N SUFFIX
CASE 738
0
7
allow easy serial cascading. A separate active LOW Master Reset is
used to reset the register.
20
1
SO–20
DW SUFFIX
CASE 751
• Common Parallel I/O for Reduced Pin Count
• Additional Serial Inputs and Outputs for Expansion
• Four Operating Modes: Shift Left, Shift Right, Load and Store
• 3–State Outputs for Bus–Oriented Applications
• Outputs Source/Sink 24 mA
20
1
TSSOP–20
DT SUFFIX
CASE 948E
20
• ′ACT299 Has TTL Compatible Inputs
1
V
CC
S
1
DS
7
Q
7
I/O
7
I/O
5
I/O
3
I/O
1
CP DS
0
ORDERING INFORMATION
20
19
18
17
16
15
14
12
13
11
Device
Package
PDIP–20
PDIP–20
SOIC–20
Shipping
MC74AC299N
18 Units/Rail
18 Units/Rail
38 Units/Rail
MC74ACT299N
MC74AC299DW
MC74AC299DWR2
MC74ACT299DW
SOIC–20 1000 Tape & Reel
SOIC–20 38 Units/Rail
1
2
3
4
5
6
7
9
8
10
S
0
OE
1
OE
2
I/O
6
I/O
4
I/O
2
I/O
0
Q
0
MR GND
Figure 1. Pinout: 20–Lead Packages Conductors
MC74ACT299DWR2 SOIC–20 1000 Tape & Reel
(Top View)
MC74AC299DT
MC74AC299DTR2
MC74ACT299DT
TSSOP–20
TSSOP–20 2500 Tape & Reel
TSSOP–20 75 Units/Rail
75 Units/Rail
PIN ASSIGNMENT
PIN
FUNCTION
MC74ACT299DTR2 TSSOP–20 2500 Tape & Reel
CP
Clock Pulse Input
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
DS
DS
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
0
7
S , S
0
1
MR
Asynchronous Master Reset
3–State Output Enable Inputs
Parallel Data Inputs or 3–State Parallel Outputs
Serial Outputs
OE , OE
1
2
I/O –I/O
0
7
Q , Q
0
7
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
May, 2001 – Rev. 5
MC74AC299/D
MC74AC299, MC74ACT299
DS
Q
7
7
S
0
DS
0
DS
7
S
1
D
C
Q
Q
Q
Q
Q
Q
Q
Q
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Q
7
7
6
5
4
3
2
1
0
CP
OE
D
MR
Q
I/O I/O I/O I/O I/O I/O I/O I/O
0 0 1 2 3 4 5 6 7
CP
D
C
Figure 2. Logic Symbol
D
CP
D
C
D
CP
D
C
D
CP
D
C
D
CP
D
C
D
CP
D
C
D
CP
D
C
D
S
S
0
1
OE
OE
2
1
DS
CP
Q
MR
0
0
NOTE: That this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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2
MC74AC299, MC74ACT299
FUNCTIONAL DESCRIPTION
A HIGH signal on either OE or OE disables the 3 state
1 2 -
The MC74AC299/74ACT299 contains eight edge–triggered
D–type flip–flops and the interstage logic necessary to
perform synchronous shift left, shift right, parallel load and
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, hold, load and reset operations can
still occur. The 3–state buffers are also disabled by HIGH
hold operations. The type of operation is determined by S
signals on both S and S in preparation for a parallel load
operation.
0
0 1
and S , as shown in the Truth Table. All flip–flop outputs are
1
brought out through 3–state buffers to separate I/O pins that
TRUTH TABLE
Inputs
also serve as data inputs in the parallel load mode. Q and Q
0
7
are also brought out on other pins for expansion in serial
Response
shifting of longer words.
MR
S
S
CP
X
1
0
A LOW signal on MR overrides the Select and CP inputs
and resets the flip–flops. All other state changes are initiated
by the rising edge of the clock. Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times, relative to the rising edge of CP, are
observed.
L
X
X
Asynchronous Reset; Q –Q = LOW
0
n
7
H
H
H
H
H
L
H
L
H
H
L
Parallel Load; I/O → Q
n
Shift Rights; DS → Q , Q → Q , etc.
0
0
0
1
Shift Left; DS → Q , Q → Q , etc.
7
7
7
6
L
X
Hold
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
MAXIMUM RATINGS*
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
V
V
V
V
–0.5 to +7.0
CC
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
–0.5 to V
+0.5
V
IN
CC
–0.5 to V
+0.5
V
OUT
CC
I
I
I
±20
mA
mA
mA
°C
IN
DC Output Sink/Source Current, per Pin
±50
±50
OUT
CC
DC V
or GND Current per Output Pin
Storage Temperature
CC
T
stg
–65 to +150
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
4.5
0
Typ
5.0
5.0
–
Max
6.0
Unit
′AC
V
V
Supply Voltage
V
V
CC
′ACT
5.5
, V
IN OUT
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
–
150
40
25
10
8.0
–
–
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
–
–
–
–
–
ns/V
t , t
r f
–
–
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
t , t
r f
ns/V
–
T
J
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current – High
–
140
85
°C
°C
T
A
–40
–
25
–
I
–24
24
mA
mA
OH
OL
I
Output Current – Low
–
–
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
CC
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
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3
MC74AC299, MC74ACT299
DC CHARACTERISTICS
Symbol
74AC
74AC
T
A
=
V
(V)
CC
T
= +25°C
–40°C to
+85°C
Parameter
Unit
Conditions
A
Typ
Guaranteed Limits
V
V
V
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
= 0.1 V
– 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V
CC
= 0.1 V
OUT
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
Maximum Low Level
Input Voltage
IL
or V
– 0.1 V
CC
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
= –50 µA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IN IL IH
3.0
4.5
5.5
–
–
–
2.56
3.86
4.86
2.46
3.76
4.76
–12 mA
–24 mA
–24 mA
V
V
V
I
OH
V
OL
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I = 50 µA
OUT
Maximum Low Level
Output Voltage
*V = V or V
IN IL
IH
3.0
4.5
5.5
–
–
–
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
I
24 mA
24 mA
OL
I
IN
Maximum Input
Leakage Current
5.5
5.5
–
–
±0.1
±0.6
±1.0
±6.0
µA
µA
V = V , GND
CC
I
I
Maximum 3–State
Current
V (OE) = V , V
OZT
I
IL IH
V = V , GND
I
V
CC
= V , GND
CC
O
I
I
I
5.5
5.5
–
–
–
–
75
mA
mA
V
= 1.65 V Max
†Minimum Dynamic
Output Current
OLD
OHD
CC
OLD
OHD
–75
V
V
= 3.85 V Min
Maximum Quiescent
Supply Current
5.5
–
8.0
80
µA
= V or GND
CC
IN
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE:
I
IN
and I
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
.
CC
CC
AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
74AC
T
= –40°C
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
L
CC
to +85°C
C
Symbol
Parameter
Unit
= 50 pF
L
Min
Typ
Max
Min
Max
Maximum Input
Frequency
3.3
5.0
90
130
–
–
–
–
80
105
–
–
f
t
t
MHz
ns
3–3
3–6
3–6
max
Propagation Delay
3.3
5.0
8.5
5.5
–
–
20.5
14
7.0
4.5
22
15
PLH
PHL
CP to Q
0 or
Q
7
Propagation Delay
CP to Q
3.3
5.0
8.5
5.5
–
–
21.5
14.5
7.0
5.0
23
16
ns
Q
0 or
7
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
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4
MC74AC299, MC74ACT299
AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
74AC
T
= –40°C
A
V
(V)
*
T
C
= +25°C
Fig.
No.
CC
A
L
to +85°C
C
Symbol
Parameter
Unit
= 50 pF
Typ
= 50 pF
L
Min
Max
Min
Max
Propagation Delay
CP to I/O
3.3
5.0
9.0
6.0
–
–
20.5
14.5
7.5
5.0
22.5
16
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
3–6
3–6
3–6
3–6
3–7
3–8
3–7
3–8
PLH
n
Propagation Delay
CP to I/O
3.3
5.0
10
6.5
–
–
23
16
8.5
6.0
24.5
17.5
PHL
PHL
PHL
PZH
PZL
PHZ
PLZ
n
Propagation Delay
MR to Q or Q
3.3
5.0
9.0
5.5
–
–
22.5
15.5
7.5
5.0
25.0
17.0
0
7
Propagation Delay
MR to I/O
3.3
5.0
9.0
5.5
–
–
21.5
15.0
7.5
5.0
24.0
16.5
n
Output Enable Time
OE to I/O
3.3
5.0
7.0
4.5
–
–
18
12.5
6.0
4.0
19.5
13.5
n
Output Enable Time
OE to I/O
3.3
5.0
7.0
5.0
–
–
18
12.5
6.0
4.0
20.5
14
n
Output Disable Time
OE to I/O
3.3
5.0
6.5
3.5
–
–
18.5
14
5.5
3.0
19.5
15
n
Output Disable Time
OE to I/O
3.3
5.0
5.5
3.5
–
–
17
12.5
4.5
2.0
19
13.5
n
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC OPERATING REQUIREMENTS
74AC
74AC
T
= –40°C
A
T
C
= +25°C
= 50 pF
V
CC
(V)
*
Fig.
No.
A
L
to +85°C
= 50 pF
Symbol
Parameter
Unit
C
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
or S to CP
3.3
5.0
–
–
8.0
5.0
8.5
5.5
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
3–9
3–9
3–9
3–9
3–6
3–6
3–6
3–9
3–9
s
h
s
h
s
h
S
0
1
Hold Time, HIGH or LOW
or S to CP
3.3
5.0
–
–
0.5
1.0
0.5
1.0
S
0
1
Setup Time, HIGH or LOW
I/O to CP
n
3.3
5.0
–
–
5.5
3.5
6.0
4.0
Hold Time, HIGH or LOW
I/O to CP
n
3.3
5.0
–
–
0
1.0
0
1.0
Setup Time, HIGH or LOW
3.3
5.0
–
–
6.5
4.0
7.0
4.5
DS or DS to CP
0
7
Hold Time, HIGH or LOW
DS or DS to CP
3.3
5.0
–
–
0
1.0
0.5
1.0
0
7
3.3
5.0
–
–
4.5
3.5
5.0
3.5
CP Pulse Width, LOW
MR Pulse Width, LOW
w
3.3
5.0
–
–
4.5
3.5
5.0
3.5
w
Recovery TIme
MR to CP
3.3
5.0
–
–
1.5
1.5
1.5
1.5
rec
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
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5
MC74AC299, MC74ACT299
DC CHARACTERISTICS
Symbol
74ACT
74ACT
T
A
=
V
(V)
CC
T
= +25°C
–40°C to
+85°C
Parameter
Unit
Conditions
A
Typ
Guaranteed Limits
V
V
V
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
= 0.1 V
– 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V
CC
= 0.1 V
OUT
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
Maximum Low Level
Input Voltage
IL
or V
– 0.1 V
CC
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
= –50 µA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IN IL IH
4.5
5.5
–
–
3.86
4.86
3.76
4.76
V
V
V
–24 mA
–24 mA
I
OH
V
OL
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
I = 50 µA
OUT
Maximum Low Level
Output Voltage
*V = V or V
IN IL
IH
4.5
5.5
–
–
0.36
0.36
0.44
0.44
24 mA
24 mA
I
OL
I
IN
Maximum Input
Leakage Current
5.5
5.5
–
–
±0.1
±0.6
±1.0
±6.0
µA
µA
V = V , GND
CC
I
I
Maximum 3-State
Current
V (OE) = V , V
OZT
I
IL IH
V = V , GND
I
V
CC
= V , GND
CC
O
∆I
Additional Max. I /Input
CC
5.5
5.5
5.5
0.6
–
–
–
–
1.5
75
mA
mA
mA
V = V
– 2.1 V
CC
CCT
I
I
V
= 1.65 V Max
= 3.85 V Min
OHD
†Minimum Dynamic
Output Current
OLD
OLD
I
–
–75
V
V
OHD
CC
I
Maximum Quiescent
Supply Current
5.5
–
8.0
80
µA
= V or GND
CC
IN
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
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6
MC74AC299, MC74ACT299
AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT
74ACT
T
= –40°C
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
L
CC
to +85°C
C
Symbol
Parameter
Unit
= 50 pF
L
Min
Typ
Max
Min
Max
Maximum Input
Frequency
f
t
t
t
t
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
120
–
–
110
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3–3
3–6
3–6
3–6
3–6
3–6
3–6
3–7
3–8
3–7
3–8
max
Propagation Delay
4.0
4.0
4.5
5.0
4.0
4.0
2.5
2.0
2.0
2.5
–
–
–
–
–
–
–
–
–
–
12.5
13.5
12.5
15
3.0
3.5
4.5
4.5
4.0
3.5
1.5
1.5
2.0
2.0
14
PLH
PHL
PLH
PHL
PHL
PHL
PZH
PZL
PHZ
PLZ
CP to Q
0 or
Q
7
Propagation Delay
CP to Q
15
Q
0 or
Propagation Delay
CP to I/O
7
13.5
16.5
18
n
Propagation Delay
CP to I/O
n
Propagation Delay
MR to Q
15
Q
0 or
Propagation Delay
MR to I/O
7
14.5
12
17.5
13
n
Output Enable Time
OE to I/O
n
Output Enable Time
OE to I/O
12
13.5
13.5
12.5
n
Output Disable Time
OE to I/O
12.5
11.5
n
Output Disable Time
OE to I/O
n
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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7
MC74AC299, MC74ACT299
AC OPERATING REQUIREMENTS
74ACT
74ACT
= –40°C
T
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
to +85°C
= 50 pF
Symbol
Parameter
Unit
L
C
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
or S to CP
t
t
t
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
–
5.0
1.0
4.0
1.0
4.5
1.0
4.0
3.5
1.5
5.5
1.0
4.5
1.0
5.0
1.0
4.5
3.5
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
3–9
3–9
3–9
3–9
3–6
3–6
3–9
3–9
3–9
s
h
s
h
s
h
S
0
1
Hold Time, HIGH or LOW
or S to CP
–
–
–
–
–
–
–
–
S
0
1
Setup Time, HIGH or LOW
I/O to CP
n
Hold Time, HIGH or LOW
I/O to CP
n
Setup Time, HIGH or LOW
DS or DS to CP
0
7
Hold Time, HIGH or LOW
DS or DS to CP
0
7
CP Pulse Width
HIGH or LOW
w
MR Pulse Width, LOW
w
Recovery Time
MR to CP
rec
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Value
Typ
Parameter
Unit
Test Conditions
C
C
Input Capacitance
Power Dissipation Capacitance
4.5
pF
pF
V
V
= 5.0 V
= 5.0 V
IN
CC
170
PD
CC
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8
MC74AC299, MC74ACT299
MARKING DIAGRAMS
SO–20
PDIP–20
TSSOP–20
AC299
AWLYYWW
MC74AC299N
AWLYYWW
AC
299
ALYW
ACT299
AWLYYWW
MC74ACT299N
AWLYYWW
ACT
299
ALYW
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
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9
MC74AC299, MC74ACT299
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
20 PIN PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
20
1
11
10
B
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
L
C
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
–T–
SEATING
PLANE
K
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
N
E
G
J
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
K
L
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
M
M
T B
0.25 (0.010)
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
_
_
_
M
M
0.25 (0.010)
T A
SO–20
DW SUFFIX
20 PIN PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
B
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
A
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
L
SEATING
PLANE
q
_
_
18X e
A1
C
T
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10
MC74AC299, MC74ACT299
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
ąă2. CONTROLLING DIMENSION: MILLIMETER.
ąă3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
ąă4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
ąă5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
ąă6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
ąă7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
0.15 (0.006) T U
M
A
–V–
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
---
6.60 0.252
4.50 0.169
N
C
1.20
---
D
0.05
0.50
0.15 0.002
0.75 0.020
F
F
G
H
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
–W–
J1
K
C
K1
L
6.40 BSC
0.252 BSC
0
G
D
M
0
8
8
_
_
_
_
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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11
MC74AC299, MC74ACT299
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
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