MC74AC652DWG [ONSEMI]
Octal Transceiver/Register with 3-State Outputs;
| 型号： | MC74AC652DWG |
| 厂家： | 
ONSEMI |
| 描述： | Octal Transceiver/Register with 3-State Outputs |
| 文件： | 总10页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74AC652, MC74ACT652
Octal Transceiver/Register
with 3-State Outputs
(Non-Inverting)
The MC74AC/ACT652 consists of registered bus transceiver
circuits, with outputs, D−type flip−flops and control circuitry
providing multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B bus will be
loaded into the respective registers on the LOW−to−HIGH transition
of the appropriate clock pin (CAB or CBA). The four fundamental
data handling functions available are illustrated in Figures 1 to 4.
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MARKING DIAGRAMS
AC652
AWLYYWWG
24
1
Features
SO−24
DW SUFFIX
CASE 751E
ACT652
AWLYYWWG
• Independent Registers for A and B Buses
• Multiplexed Real−Time and Stored Data Transfers
• Choice of True and Inverting Data Paths
• 3−State Outputs
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
• 300 mil Slim Dual−in−Line Package
• Outputs Source/Sink 24 mA
G
= Pb−Free Package
• ′ACT652 Has TTL Compatible Inputs
• These are Pb−Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
REAL TIME TRANSFER
A‐BUS TO B‐BUS
REAL TIME TRANSFER
B‐BUS TO A‐BUS
A‐BUS
A‐BUS
REG
REG
REG
REG
B‐BUS
B‐BUS
Figure 1.
STORAGE
Figure 2.
TRANSFER
FROM BUS TO REGISTER
FROM REGISTER TO BUS
A‐BUS
A‐BUS
REG
REG
REG
REG
B‐BUS
B‐BUS
Figure 3.
Figure 4.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
March, 2015 − Rev. 7
MC74AC652/D
MC74AC652, MC74ACT652
V
CBA SBA GBA
23 22 21
B
B
B
B
B
B
B
B
7
CC
0
1
2
3
4
5
6
PIN ASSIGNMENT
24
20
19
18
16
14
17
15
13
PIN
A −A
FUNCTION
Data Register A Inputs
Data Register A Outputs
0
7
7
B −B
0
Data Register B Inputs
Data Register B Outputs
CAB, CBA
SAB, SBA
GAB, GBA
Clock Pulse Inputs
1
2
3
4
5
6
7
9
11
8
10
12
Transmit/Receive Inputs
Output Enable Inputs
CAB SAB GAB
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
GND
Figure 5. Pinout: 24−Lead Plastic Package
(Top View)
B
B
B
B
A
B
B
A
B
A
B
A
CAB
SAB
GAB
CBA
SBA
GBA
0
1
2
3
4
5
6
7
A
0
A
1
A
2
A
4
3
5
6
7
Figure 6. Logic Symbol
GBA
GAB
CBA
SBA
CAB
SAB
1 OF 8 CHANNELS
D
0
0
C
B
0
A
0
D
0
C
0
TO 7 OTHER CHANNELS
NOTE: This diagram is provided only for the understanding of
logic operations and should not be used to estimate
propagation delays.
Figure 7. Logic Diagram
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2
MC74AC652, MC74ACT652
FUNCTION TABLE
Inputs
CAB
Data I/O*
Operation or Function
GAB
GBA
CBA
SAB
SBA
A − A
0
B − B
7
0
7
L
L
H
H
H or L
⇑
H or L
⇑
X
X
X
X
Isolation
Store A and B Data
Input
Input
X
H
H
H
⇑
⇑
H or L
⇑
X
X**
X
X
Input
Input
Unspecified* Store A, Hold B
Output
Store A in Both Registers
L
L
X
L
H or L
⇑
⇑
⇑
X
X
X
X**
Unspecified*
Output
Input
Input
Hold A, Store B
Store B in Both Registers
L
L
L
L
X
X
X
X
X
L
H
Real-Time B Data to A Bus
Stored B Data to A Bus
Output
Input
Input
Output
Output
H or L
H
H
H
H
X
X
X
L
H
X
X
Real-Time A Data to B Bus
Stored A Data to B Bus
H or L
Stored A Data to B Bus and
Stored B Data to A Bus
H
L
H or L
H or L
H
H
Output
*The data output functions may be enabled or disabled by various signals at the GBA and GAB inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
**Select control = L: clocks can occur simultaneously.
H = HIGH Voltage Level; L = LOW Voltage Level; X = Immaterial; ⇑ = LOW-to-HIGH Transition
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3
MC74AC652, MC74ACT652
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND) (Note 1)
DC Input Diode Current
−0.5 to V +0.5
V
IN
CC
V
OUT
−0.5 to V +0.5
V
CC
I
IK
20
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
I
DC Output Diode Current
50
OK
I
DC Output Sink/Source Current
DC Supply Current, per Output Pin
DC Ground Current, per Output Pin
Storage Temperature Range
50
OUT
I
50
CC
I
100
GND
T
STG
*65 to )150
T
Lead temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
260
L
T
140
59.8
J
q
JA
MSL
Moisture Sensitivity
Level 1
F
R
Flammability Rating
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
> 2000
> 200
V
Charged Device Model (Note 5)
> 1000
I
Latchup Performance
Above V and Below GND at 85_C (Note 6)
100
mA
Latchup
CC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
absolute maximum rating must be observed.
OUT
2. The package thermal impedance is calculated in accordance with JESD 51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
4.5
0
Typ
5.0
5.0
−
Min
6.0
5.5
Unit
′AC
V
Supply Voltage
V
V
CC
′ACT
V , V
in out
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
−
150
40
25
10
8.0
25
−
−
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
−
−
−
−
−
ns/V
ns/V
t , t
r
f
−
−
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
t , t
r
f
−
T
A
Operating Ambient Temperature Range
Output Current — HIGH
−40
−
85
−24
24
°C
I
I
mA
mA
OH
OL
Output Current — LOW
−
−
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
in
CC
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
in
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4
MC74AC652, MC74ACT652
DC CHARACTERISTICS
Symbol
74AC
74AC
T
A
=
V
(V)
CC
−40°C to
+85°C
T
= +25°C
Parameter
Unit
Conditions
A
Typ
Guaranteed Limits
V
V
V
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
= 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V − 0.1 V
CC
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
OUT
= 0.1 V
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
= − 50 μA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IN
IL
IH
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
− 12 mA
− 24 mA
− 24 mA
V
V
V
I
OH
V
OL
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 μA
OUT
Minimum Low Level
Output Voltage
*V = V or V
IN
IL
IH
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
24 mA
24 mA
I
OL
I
Maximum Input
Leakage Current
V = V , GND
I CC
IN
5.5
5.5
−
−
0.1
0.6
1.0
6.0
μA
μA
I
V (OE) = V , V
I IL IH
Maximum
3-State
OZT
V = V , GND
I
CC
Current
V = V , GND
O
CC
I
I
I
5.5
5.5
−
−
−
−
75
mA
mA
V
V
V
= 1.65 V Max
= 3.85 V Min
†Minimum Dynamic
Output Current
OLD
OHD
CC
OLD
−75
OHD
Maximum Quiescent
Supply Current
= V or GND
CC
IN
5.5
−
8.0
80
μA
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one input loaded at a time.
NOTE:
I
IN
and I @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V.
CC
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5
MC74AC652, MC74ACT652
AC CHARACTERISTICS
Symbol
74AC
74AC
T
A
= −40°C
T
A
= +25°C
C = 50 pF
L
V
(V)
*
CC
to +85°C
C = 50 pF
Parameter
Unit
L
Min
Max
Min
Max
3.0
5.0
4.0
2.5
17.0
12.0
3.0
2.0
19.0
14.0
Propagation Delay
CPBA or CPAB to A or B
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
n
n
3.0
5.0
3.0
2.0
14.5
10.5
2.5
1.5
16.5
12.0
Propagation Delay
CPBA or CPAB to A or B
n
n
3.0
5.0
3.0
2.0
14.0
9.5
2.5
1.5
16.0
11.0
Propagation Delay
A or B to B or A
n
n
3.0
5.0
2.5
1.5
13.0
9.0
2.0
1.0
15.0
10.5
Propagation Delay
A or B to B or A
n
n
3.0
5.0
3.0
2.5
14.0
10.0
2.5
2.0
16.0
11.5
Propagation Delay
SBA or SAB to A or B
n
n
3.0
5.0
2.5
2.0
13.5
10.0
2.0
1.5
15.5
11.5
Propagation Delay
SBA or SAB to A or B
n
n
3.0
5.0
2.5
1.5
12.0
9.0
2.0
1.0
13.5
10.0
Output Enable Time
OEBA to A
n
3.0
5.0
2.5
1.5
12.0
9.0
2.0
1.0
14.0
10.5
Output Enable Time
OEBA to A
n
3.0
5.0
3.0
2.0
13.0
11.0
2.5
1.5
14.0
12.0
Output Disable Time
OEBA to A
n
3.0
5.0
2.5
2.0
12.5
10.5
2.0
1.5
14.0
12.0
Output Disable Time
OEBA to A
n
*Voltage Range 3.3 V is 3.3 V 0.3 V.
Voltage Range 5.0 V is 5.0 V 0.5 V.
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6
MC74AC652, MC74ACT652
DC CHARACTERISTICS
Symbol
74ACT
74ACT
T
A
=
V
(V)
CC
−40°C to
+85°C
T
= +25°C
Parameter
Unit
Conditions
A
Typ
Guaranteed Limits
V
V
V
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
= 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V − 0.1 V
CC
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
OUT
= 0.1 V
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
= − 50 μA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IN
IL
IH
4.5
5.5
−
−
3.86
4.86
3.76
4.76
V
− 24 mA
− 24 mA
I
I
OH
V
OL
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
= − 50 μA
OUT
Minimum Low Level
Output Voltage
V
V
*V = V or V
IH
IN
IL
4.5
5.5
−
−
0.36
0.36
0.44
0.44
− 24 mA
− 24 mA
I
OH
I
Maximum Input
Leakage Current
V = V , GND
I CC
IN
5.5
5.5
−
0.1
−
1.0
1.5
μA
ΔI
Additional Max. I /Input
0.6
mA
V = V − 2.1 V
I CC
CCT
CC
I
V (OE) = V , V
I IL IH
Maximum
3-State
OZT
μA
5.5
−
0.6
6.0
V = V , GND
I
CC
Current
V
V
V
= V , GND
CC
O
I
I
I
5.5
5.5
−
−
−
−
75
mA
mA
= 1.65 V Max
= 3.85 V Min
†Minimum Dynamic
Output Current
OLD
OLD
OHD
−75
OHD
CC
Maximum Quiescent
Supply Current
V = V or GND
IN CC
5.5
−
8.0
80
μA
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one input loaded at a time.
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7
MC74AC652, MC74ACT652
AC CHARACTERISTICS
Symbol
74ACT
74ACT
T
= −40°C
A
T
= +25°C
V
(V)
*
A
CC
to +85°C
C = 50 pF
Parameter
Unit
C = 50 pF
L
L
Min
Max
Min
Max
Propagation Delay
CPBA or CPAB to A or B
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.0
14.5
3.5
16.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
s
n
n
Propagation Delay
3.5
2.5
2.5
2.5
3.0
2.0
2.5
3.0
2.5
2.5
2.5
3.5
3.0
7.0
2.5
6.0
14.5
11.5
11.5
12.0
12.0
11.5
11.5
13.0
12.5
12.0
12.0
13.5
13.5
−
3.0
2.0
2.0
2.0
2.5
1.5
2.0
2.5
2.0
2.0
2.0
3.0
2.5
8.0
2.5
7.0
16.5
13.0
13.0
13.5
13.5
13.0
13.0
14.0
14.0
13.5
13.5
14.5
15.0
−
CPBA or CPAB to A or B
n
n
Propagation Delay
A or B to B or A
n
n
Propagation Delay
A or B to B or A
n
n
Propagation Delay
SBA or SAB to A or B
n
n
Propagation Delay
SBA or SAB to A or B
n
n
Output Enable Time
OEBA to A
n
Output Enable Time
OEBA to A
n
Output Disable Time
OEBA to A
n
Output Disable Time
OEBA to A
n
Output Enable time
OEAB to B
n
Output Enable Time
OEAB to B
n
Output Enable Time
OEAB to B
n
Output Enable Time
OEAB to B
n
Setup Time, HIGH or LOW
A or B to CPBA or CPAB
n
n
Hold Time, HIGH or LOW
A or B to CPBA or CPAB
−
−
h
n
n
CPAB, CPBA Pulse Width
HIGH or LOW
−
−
w
*Voltage Range 3.3 V is 3.3 V 0.3 V.
Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Symbol
74ACT
Typ
Parameter
Unit
Test Conditions
C
C
C
Input Capacitance
4.5
15
pF
pF
pF
V
CC
V
CC
V
CC
= 5.0 V
= 5.0 V
= 5.0 V
IN
Input/Output Capacitance
I/O
PD
Power Dissipation Capacitance
60.0
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8
MC74AC652, MC74ACT652
ORDERING INFORMATION
Device
†
Package
Shipping
MC74AC652DWG
30 Units / Rail
1000 / Tape & Reel
30 Units / Rail
MC74AC652DWR2G
MC74ACT652DWG
MC74ACT652DWR2G
SOIC−24
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
MC74AC652, MC74ACT652
PACKAGE DIMENSIONS
SOIC−24 WB
DW SUFFIX
CASE 751E−04
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
H
D
A
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b AND c APPLY TO THE FLAT SEC-
TION OF THE LEAD AND ARE MEASURED BE-
TWEEN 0.10 AND 0.25 FROM THE LEAD TIP.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 mm PER SIDE. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED
0.25 PER SIDE. DIMENSIONS D AND E1 ARE
DETERMINED AT DATUM H.
B
0.25
C
24
1
13
12
E
E1
L
C
DETAIL A
5. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
24X
b
PIN 1
INDICATOR
M
S
S
B
0.25
C A
MILLIMETERS
DIM MIN
MAX
2.65
0.29
0.49
0.32
15.54
TOP VIEW
NOTE 3
A
A1
b
2.35
0.13
0.35
h
x 45
_
A
M
c
0.23
D
E
15.25
10.30 BSC
E1
e
h
L
M
7.40
1.27 BSC
7.60
c
SEATING
PLANE
e
A1
NOTE 5
DETAIL A
C
NOTE 3
0.25
0.41
0
0.75
0.90
8
END VIEW
SIDE VIEW
_
_
RECOMMENDED
SOLDERING FOOTPRINT*
24X
1.62
24X
0.52
11.00
1
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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MC74AC652/D
相关型号：
MC74AC74DC
D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, PLASTIC, SOIC-14
MOTOROLA
MC74AC74DCR1
AC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SOIC-14
MOTOROLA
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