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MC74ACT109 [ONSEMI]

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP; 双JK正边沿触发触发器
MC74ACT109
型号： MC74ACT109
厂家： ONSEMI    ONSEMI
描述：

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
双JK正边沿触发触发器

触发器
文件： 总6页 (文件大小：201K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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DUAL JK POSITIVE  
EDGE-TRIGGERED  
FLIP-FLOP  
The MC74AC109/74ACT109 consists of two high-speed completely independent  
transition clocked JK flip-flops. The clocking operation is independent of rise and fall  
times of the clock waveform. The JK design allows operation as a D flip-flop (refer to  
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.  
Asynchronous Inputs:  
LOW input to S (Set) sets Q to HIGH level  
D
LOW input to C (Clear) sets Q to LOW level  
D
Clear and Set are independent of clock  
Simultaneous LOW on C and S makes both Q and Q HIGH  
D
D
N SUFFIX  
CASE 648-08  
PLASTIC  
• Outputs Source/Sink 24 mA  
• ′ACT109 Has TTL Compatible Inputs  
V
C
J
K
CP  
S
Q
Q
2
CC  
D2  
2
2
2
D2  
2
16  
15  
14  
13  
12  
11  
10  
9
C
D
J
K
CP  
S
D
Q
Q
D SUFFIX  
CASE 751B-05  
PLASTIC  
PIN NAMES  
C
D1  
1
J , J , K , K  
Data Inputs  
J
K
1
CP  
S
Q
1
Q
1
1
2
1
2
2
1
D1  
CP , CP  
Clock Pulse Inputs  
Direct Clear Inputs  
Direct Set Inputs  
Outputs  
1
C
S
, C  
, S  
D1 D2  
1
2
4
5
6
7
8
3
D1 D2  
Q , Q , Q , Q  
2
C
J
K
1
CP  
S
Q
Q
1
GND  
1
2
1
D1  
1
1
D1  
1
LOGIC SYMBOL  
TRUTH TABLE  
Inputs  
Outputs  
Q
J
Q
K
S
C
CP  
J
K
Q
Q
D
D
S
C
D
D
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
L
H
L
X
X
X
L
H
L
H
H
H
CP  
CP  
L
H
L
L
Toggle  
H
H
X
Q
Q -  
0
0
Q
J
Q
K
H
X
H
L
Q -  
0
S
C
D
D
L
Q
0
H = HIGH Voltage Level  
L = LOW Voltage Level  
= LOW-to-HIGH Clock Transition  
X = Immaterial  
Q (Q ) = Previous Q (Q ) before  
0
0
0
0
LOW-to-HIGH Transition of Clock  
FACT DATA  
5-1  
MC74AC109 MC74ACT109  
LOGIC DIAGRAM (one half shown)  
S
D
K
Q
Q
CP  
J
C
D
Please note that this diagram is provided only for the understanding of logic  
operations and should not be used to estimate propagation delays.  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
Unit  
V
V
V
DC Supply Voltage (Referenced to GND)  
–0.5 to +7.0  
CC  
DC Input Voltage (Referenced to GND)  
DC Output Voltage (Referenced to GND)  
DC Input Current, per Pin  
–0.5 to V  
+0.5  
V
in  
CC  
V
out  
–0.5 to V  
+0.5  
V
CC  
I
I
I
±20  
mA  
mA  
mA  
°C  
in  
DC Output Sink/Source Current, per Pin  
±50  
±50  
out  
CC  
DC V  
or GND Current per Output Pin  
Storage Temperature  
CC  
T
stg  
–65 to +150  
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended  
Operating Conditions.  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Min  
2.0  
4.5  
0
Typ  
5.0  
5.0  
Max  
6.0  
Unit  
V
′AC  
V
Supply Voltage  
CC  
′ACT  
5.5  
V , V  
in out  
DC Input Voltage, Output Voltage (Ref. to GND)  
V
CC  
V
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
@ 3.0 V  
@ 4.5 V  
@ 5.5 V  
@ 4.5 V  
@ 5.5 V  
150  
40  
Input Rise and Fall Time (Note 1)  
′AC Devices except Schmitt Inputs  
ns/V  
t , t  
r f  
25  
10  
Input Rise and Fall Time (Note 2)  
′ACT Devices except Schmitt Inputs  
t , t  
r f  
ns/V  
8.0  
T
Junction Temperature (PDIP)  
Operating Ambient Temperature Range  
Output Current — High  
140  
85  
°C  
°C  
J
T
A
–40  
25  
I
I
–24  
24  
mA  
mA  
OH  
Output Current — Low  
OL  
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.  
in  
CC  
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.  
in  
FACT DATA  
5-2  
MC74AC109 MC74ACT109  
DC CHARACTERISTICS  
Symbol  
74AC  
= +25°C  
74AC  
T
A
=
V
(V)  
CC  
Parameter  
Unit  
Conditions  
T
A
–40°C to +85°C  
Typ  
Guaranteed Limits  
V
V
V
3.0  
4.5  
5.5  
1.5  
2.25  
2.75  
2.1  
3.15  
3.85  
2.1  
3.15  
3.85  
V
= 0.1 V  
– 0.1 V  
Minimum High Level  
Input Voltage  
IH  
OUT  
V
V
V
or V  
CC  
= 0.1 V  
OUT  
3.0  
4.5  
5.5  
1.5  
2.25  
2.75  
0.9  
1.35  
1.65  
0.9  
1.35  
1.65  
V
Maximum Low Level  
Input Voltage  
IL  
or V  
– 0.1 V  
CC  
3.0  
4.5  
5.5  
2.99  
4.49  
5.49  
2.9  
4.4  
5.4  
2.9  
4.4  
5.4  
I
= –50 µA  
Minimum High Level  
Output Voltage  
OH  
OUT  
*V = V or V  
IN IL IH  
3.0  
4.5  
5.5  
2.56  
3.86  
4.86  
2.46  
3.76  
4.76  
–12 mA  
–24 mA  
–24 mA  
V
V
I
OH  
V
OL  
3.0  
4.5  
5.5  
0.002  
0.001  
0.001  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
I = 50 µA  
OUT  
Maximum Low Level  
Output Voltage  
*V = V or V  
IN IL  
IH  
3.0  
4.5  
5.5  
0.36  
0.36  
0.36  
0.44  
0.44  
0.44  
12 mA  
V
I
24 mA  
24 mA  
OL  
I
IN  
Maximum Input  
Leakage Current  
5.5  
±0.1  
±1.0  
µA  
V = V , GND  
I
CC  
I
I
I
5.5  
5.5  
75  
mA  
mA  
V
V
= 1.65 V Max  
†Minimum Dynamic  
Output Current  
OLD  
OHD  
CC  
OLD  
–75  
= 3.85 V Min  
OHD  
Maximum Quiescent  
Supply Current  
5.5  
4.0  
40  
µA  
V
IN  
= V  
CC  
or GND  
* All outputs loaded; thresholds on input associated with output under test.  
†Maximum test duration 2.0 ms, one output loaded at a time.  
Note: I and I  
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V .  
IN CC  
CC  
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)  
74AC  
74AC  
T
= –40°C  
A
T
C
= +25°C  
= 50 pF  
V
(V)  
*
Fig.  
No.  
A
L
CC  
Symbol  
Parameter  
to +85°C  
= 50 pF  
Unit  
C
L
Min  
Typ  
Max  
Min  
Max  
3.3  
5.0  
125  
150  
100  
125  
Maximum Clock  
Frequency  
f
t
t
t
t
MHz  
ns  
3-3  
3-6  
3-6  
3-6  
3-6  
max  
3.3  
5.0  
4.0  
2.5  
13.5  
10.0  
3.5  
2.0  
16.0  
10.5  
Propagation Delay  
CP to Q or Q  
PLH  
PHL  
PLH  
PHL  
n
n
n
3.3  
5.0  
3.0  
2.0  
14.0  
10.0  
3.0  
1.5  
14.5  
10.5  
Propagation Delay  
CP to Q or Q  
ns  
n
n
n
3.3  
5.0  
3.0  
2.5  
12.0  
9.0  
2.5  
2.0  
13.0  
10.0  
Propagation Delay  
or S to Q or Q  
ns  
C
Dn  
Dn  
Propagation Delay  
CD or S to Q or Q  
n
n
3.3  
5.0  
3.0  
2.0  
12.0  
9.5  
3.0  
2.0  
13.5  
10.5  
ns  
n
Dn  
n
n
* Voltage Range 3.3 V is 3.3 V ±0.3 V.  
Voltage Range 5.0 V is 5.0 V ±0.5 V.  
FACT DATA  
5-3  
MC74AC109 MC74ACT109  
AC OPERATING REQUIREMENTS  
74AC  
74AC  
T
= –40°C  
A
T
C
= +25°C  
= 50 pF  
V
(V)  
*
Fig.  
No.  
A
L
CC  
Symbol  
Parameter  
to +85°C  
= 50 pF  
Unit  
C
L
Typ  
Guaranteed Minimum  
Set-up Time, HIGH or LOW  
or K to CP  
3.3  
5.0  
6.5  
4.5  
7.5  
5.0  
t
t
t
t
ns  
ns  
ns  
ns  
3-9  
3-9  
3-6  
3-9  
s
J
n
n
n
Hold Time, HIGH or LOW  
3.3  
5.0  
0
0.5  
0
0.5  
h
w
J
or K to CP  
n
n
n
Pulse Width  
CP  
3.3  
5.0  
4.0  
3.5  
4.5  
3.5  
C
or S  
n or Dn  
Dn  
Recovery TIme  
or S to CP  
3.3  
5.0  
0
0
0
0
rec  
C
Dn  
Dn  
* Voltage Range 3.3 V is 3.3 V ±0.3 V.  
Voltage Range 5.0 V is 5.0 V ±0.5 V.  
DC CHARACTERISTICS  
74ACT  
= +25°C  
74ACT  
T
A
=
V
(V)  
CC  
Symbol  
Parameter  
Unit  
Conditions  
T
A
–40°C to +85°C  
Typ  
Guaranteed Limits  
V
V
V
4.5  
5.5  
1.5  
1.5  
2.0  
2.0  
2.0  
2.0  
V
= 0.1 V  
– 0.1 V  
Minimum High Level  
Input Voltage  
IH  
OUT  
V
V
V
or V  
CC  
= 0.1 V  
OUT  
4.5  
5.5  
1.5  
1.5  
0.8  
0.8  
0.8  
0.8  
V
Maximum Low Level  
Input Voltage  
IL  
or V  
– 0.1 V  
CC  
4.5  
5.5  
4.49  
5.49  
4.4  
5.4  
4.4  
5.4  
I
= –50 µA  
Minimum High Level  
Output Voltage  
OH  
OUT  
*V = V or V  
IN IL IH  
4.5  
5.5  
3.86  
4.86  
3.76  
4.76  
V
V
–24 mA  
–24 mA  
I
OH  
V
OL  
4.5  
5.5  
0.001  
0.001  
0.1  
0.1  
0.1  
0.1  
I = 50 µA  
OUT  
Maximum Low Level  
Output Voltage  
*V = V or V  
IN IL  
IH  
4.5  
5.5  
0.36  
0.36  
0.44  
0.44  
V
24 mA  
I
OL  
24 mA  
I
IN  
Maximum Input  
Leakage Current  
5.5  
±0.1  
±1.0  
µA  
V = V , GND  
I
CC  
∆I  
Additional Max. I /Input  
CC  
5.5  
5.5  
5.5  
0.6  
1.5  
75  
mA  
mA  
mA  
V = V  
I
– 2.1 V  
CCT  
CC  
I
V
= 1.65 V Max  
= 3.85 V Min  
OHD  
†Minimum Dynamic  
Output Current  
OLD  
OLD  
I
–75  
V
V
OHD  
CC  
I
Maximum Quiescent  
Supply Current  
5.5  
4.0  
40  
µA  
= V or GND  
CC  
IN  
* All outputs loaded; thresholds on input associated with output under test.  
†Maximum test duration 2.0 ms, one output loaded at a time.  
FACT DATA  
5-4  
MC74AC109 MC74ACT109  
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)  
74ACT  
74ACT  
= –40°C  
T
A
T
C
= +25°C  
= 50 pF  
V
(V)  
*
Fig.  
No.  
A
CC  
Symbol  
Parameter  
to +85°C  
Unit  
L
C
= 50 pF  
L
Min  
Typ  
Max  
Min  
Max  
Maximum Clock  
Frequency  
f
t
t
t
t
5.0  
5.0  
5.0  
5.0  
5.0  
145  
125  
MHz  
ns  
3-3  
3-6  
3-6  
3-6  
3-6  
max  
Propagation Delay  
4.0  
3.0  
2.5  
2.5  
11.0  
10.0  
9.5  
3.5  
2.5  
2.0  
2.0  
13.0  
11.5  
10.5  
11.5  
PLH  
PHL  
PLH  
PHL  
CP to Q or Q  
n
n
n
Propagation Delay  
CP to Q or Q  
ns  
n
n
n
Propagation Delay  
or S to Q or Q  
ns  
C
Dn  
Dn  
Propagation Delay  
or S to Q or Q  
n
n
10.0  
ns  
C
Dn  
Dn  
n
n
* Voltage Range 5.0 V is 5.0 V ±0.5 V.  
AC OPERATING REQUIREMENTS  
74ACT  
74ACT  
= –40°C  
T
A
T
C
= +25°C  
= 50 pF  
V
CC  
(V)  
*
Fig.  
No.  
A
Symbol  
Parameter  
to +85°C  
= 50 pF  
Unit  
L
C
L
Typ  
Guaranteed Minimum  
Set-up Time, HIGH or LOW  
or K to CP  
t
t
t
t
5.0  
5.0  
5.0  
5.0  
2.0  
2.0  
5.0  
0
2.5  
2.0  
6.0  
0
ns  
ns  
ns  
ns  
3-9  
3-9  
3-6  
3-9  
s
J
n
n
n
Hold Time, HIGH or LOW  
h
w
J
or K to CP  
n
n
n
Pulse Width  
CP  
C
or S  
n or Dn  
Dn  
Recovery TIme  
or S to CP  
rec  
C
Dn  
Dn  
* Voltage Range 5.0 V is 5.0 V ±0.5 V.  
CAPACITANCE  
Symbol  
Value  
Typ  
Parameter  
Unit  
Test Conditions  
C
C
Input Capacitance  
Power Dissipation Capacitance  
4.5  
35  
pF  
pF  
V
V
= 5.0 V  
= 5.0 V  
IN  
CC  
PD  
CC  
FACT DATA  
5-5  
MC74AC109 MC74ACT109  
OUTLINE DIMENSIONS  
N SUFFIX  
PLASTIC DIP PACKAGE  
NOTES:  
CASE 648–08  
ISSUE R  
–A–  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION L TO CENTER OF LEADS WHEN  
FORMED PARALLEL.  
16  
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.  
5. ROUNDED CORNERS OPTIONAL.  
INCHES  
MILLIMETERS  
DIM  
A
B
C
D
F
MIN  
MAX  
0.770  
0.270  
0.175  
0.021  
0.70  
MIN  
18.80  
6.35  
3.69  
0.39  
1.02  
MAX  
19.55  
6.85  
4.44  
0.53  
1.77  
F
0.740  
0.250  
0.145  
0.015  
0.040  
C
L
SEATING  
PLANE  
–T–  
G
H
J
K
L
0.100 BSC  
0.050 BSC  
2.54 BSC  
1.27 BSC  
K
M
0.008  
0.015  
0.130  
0.305  
10  
0.21  
0.38  
3.30  
7.74  
10  
H
J
0.110  
0.295  
0
2.80  
7.50  
0
G
D 16 PL  
M
S
0.020  
0.040  
0.51  
1.01  
M
M
0.25 (0.010)  
T
A
D SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751B–05  
ISSUE J  
–A–  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
16  
1
9
8
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.127 (0.005) TOTAL  
IN EXCESS OF THE D DIMENSION AT  
MAXIMUM MATERIAL CONDITION.  
–B–  
P 8 PL  
M
S
0.25 (0.010)  
B
G
MILLIMETERS  
INCHES  
DIM  
A
B
C
D
MIN  
9.80  
3.80  
1.35  
0.35  
0.40  
MAX  
10.00  
4.00  
1.75  
0.49  
1.25  
MIN  
MAX  
0.393  
0.157  
0.068  
0.019  
0.049  
F
0.386  
0.150  
0.054  
0.014  
0.016  
R X 45  
K
C
F
G
J
K
M
P
R
1.27 BSC  
0.050 BSC  
–T–  
SEATING  
PLANE  
0.19  
0.10  
0
0.25  
0.25  
7
0.008  
0.004  
0
0.009  
0.009  
7
J
M
D
16 PL  
5.80  
0.25  
6.20  
0.50  
0.229  
0.010  
0.244  
0.019  
M
S
S
0.25 (0.010)  
T
B
A
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JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,  
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447  
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315  
MFAX: RMFAX0@email.sps.mot.com –TOUCHTONE (602) 244–6609  
INTERNET: http://Design–NET.com  
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,  
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298  
MC74AC109/D  
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相关型号：

MC74ACT109D

 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
MOTOROLA

MC74ACT109D

 Dual JK Positive Edge−Triggered Flip−Flop
ONSEMI

MC74ACT109DC

 ACT SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOIC-16
MOTOROLA

MC74ACT109DCR1

 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, PLASTIC, SOIC-16
MOTOROLA

MC74ACT109DR2

 Dual JK Positive Edge−Triggered Flip−Flop
ONSEMI

MC74ACT109DT

 Dual JK Positive Edge−Triggered Flip−Flop
ONSEMI

MC74ACT109DT

 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16
ROCHESTER

MC74ACT109DTR2

 Dual JK Positive Edge−Triggered Flip−Flop
ONSEMI

MC74ACT109DTR2

 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16
ROCHESTER

MC74ACT109M

 Dual JK Positive Edge−Triggered Flip−Flop
ONSEMI

MC74ACT109M

 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, EIAJ, SO-16
ROCHESTER

MC74ACT109MEL

 Dual JK Positive Edge−Triggered Flip−Flop
ONSEMI
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