MC74ACT273MEL [ONSEMI]
OCTAL D FLIP-FLOP; 八路D触发器
| 型号： | MC74ACT273MEL |
| 厂家： | 
ONSEMI |
| 描述： | OCTAL D FLIP-FLOP |
| 文件： | 总12页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74AC273, MC74ACT273
Octal D Flip-Flop
The MC74AC273/74ACT273 has eight edge-triggered D–type
flip–flops with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip–flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the LOW–to–HIGH clock transition, is transferred
to the corresponding flip–flop’s Q output.
All outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input. The device is useful
for applications where the true output only is required and the Clock
and Master Reset are common to all storage elements.
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PDIP–20
N SUFFIX
CASE 738
20
1
SO–20
• Ideal Buffer for MOS Microprocessor or Memory
• Eight Edge-Triggered D Flip–Flops
• Buffered Common Clock
• Buffered, Asynchronous Master Reset
• See MC74AC377 for Clock Enable Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• Outputs Source/Sink 24 mA
DW SUFFIX
CASE 751
20
1
TSSOP–20
DT SUFFIX
CASE 948E
20
1
EIAJ–20
M SUFFIX
CASE 967
20
• ′ACT273 Has TTL Compatible Inputs
1
V
Q
D
D
Q
Q
D
D
Q
4
CP
11
CC
7
7
6
6
5
5
4
ORDERING INFORMATION
20
19
18
17
16
15
14
12
13
Device
Package
PDIP–20
PDIP–20
SOIC–20
Shipping
MC74AC273N
18 Units/Rail
18 Units/Rail
38 Units/Rail
MC74ACT273N
MC74AC273DW
MC74AC273DWR2
MC74ACT273DW
1
2
3
4
5
6
7
9
SOIC–20 1000 Tape & Reel
SOIC–20 38 Units/Rail
8
10
MR
Q
0
D
0
D
1
Q
1
Q
2
D
2
D
3
Q
3
GND
Figure 1. Pinout: 20–Lead Packages Conductors
MC74ACT273DWR2 SOIC–20 1000 Tape & Reel
(Top View)
MC74AC273DT
MC74AC273DTR2
MC74ACT273DT
TSSOP–20
TSSOP–20 2500 Tape & Reel
TSSOP–20 75 Units/Rail
75 Units/Rail
PIN ASSIGNMENT
PIN
D0–D
MR
FUNCTION
MC74ACT273DTR2 TSSOP–20 2500 Tape & Reel
Data Inputs
7
MC74AC273M
EIAJ–20
EIAJ–20 2000 Tape & Reel
EIAJ–20 40 Units/Rail
EIAJ–20 2000 Tape & Reel
40 Units/Rail
Master Reset
Clock Pulse Input
Data Outputs
CP
MC74AC273MEL
MC74ACT273M
MC74ACT273MEL
Q –Q
0
7
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
May, 2001 – Rev. 5
MC74AC273/D
MC74AC273, MC74ACT273
MODE SELECT-FUNCTION TABLE
Inputs
CP
Outputs
D
D
Q
D
Q
D
Q
D
Q
D
D
Q
D
Q
0
1
2
3
4
5
6
7
Operating Mode
CP
MR
L
D
Q
n
n
MR
Q
Reset (Clear)
X
X
L
Q
5
0
1
2
3
4
6
7
Load ′1′
Load ′0′
H
H
L
H
L
H
Figure 2. Logic Symbol
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
R
CP
R
CP
R
CP
CP
R
CP
R
CP
CP
R
D
R
D
R
D
D
D
D
D
D
MR
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
NOTE: That this diagram is provided only for the understanding of logic operations
and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
MAXIMUM RATINGS*
Symbol
Parameter
Value
–0.5 to +7.0
Unit
V
V
V
V
DC Supply Voltage (Referenced to GND)
CC
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
–0.5 to V
–0.5 to V
+0.5
+0.5
V
IN
CC
V
OUT
CC
I
I
I
±20
mA
mA
mA
°C
IN
DC Output Sink/Source Current, per Pin
±50
±50
OUT
CC
DC V
or GND Current per Output Pin
Storage Temperature
CC
T
stg
–65 to +150
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
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2
MC74AC273, MC74ACT273
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
5.0
5.0
–
Max
6.0
Unit
′AC
2.0
4.5
0
V
Supply Voltage
V
V
CC
′ACT
5.5
V , V
in out
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
–
150
40
25
10
8.0
–
–
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
–
–
–
–
–
ns/V
t , t
r f
–
–
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
t , t
r f
ns/V
–
T
J
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current – High
–
140
85
°C
°C
T
A
–40
–
25
–
I
–24
24
mA
mA
OH
OL
I
Output Current – Low
–
–
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
CC
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
DC CHARACTERISTICS
74AC
74AC
T
=
A
V
(V)
CC
T
A
= +25°C
–40°C to
+85°C
Symbol
Parameter
Unit
Conditions
Typ
Guaranteed Limits
V
V
V
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
or V
= 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
– 0.1 V
CC
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
OUT
= 0.1 V
Maximum Low Level
Input Voltage
IL
or V
– 0.1 V
CC
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
= –50 µA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IN IL IH
3.0
4.5
5.5
–
–
–
2.56
3.86
4.86
2.46
3.76
4.76
–12 mA
–24 mA
–24 mA
V
V
I
OH
V
OL
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I = 50 µA
OUT
Maximum Low Level
Output Voltage
*V = V or V
IN IL
IH
3.0
4.5
5.5
–
–
–
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
V
I
24 mA
24 mA
OL
I
IN
Maximum Input
Leakage Current
5.5
–
±0.1
±1.0
µA
V = V , GND
I
CC
I
I
I
5.5
5.5
–
–
–
–
75
mA
mA
V
V
= 1.65 V Max
†Minimum Dynamic
Output Current
OLD
OHD
CC
OLD
–75
= 3.85 V Min
OHD
Maximum Quiescent
Supply Current
5.5
–
8.0
80
µA
V
IN
= V or GND
CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: Note: I and I
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
.
CC
IN CC
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3
MC74AC273, MC74ACT273
AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
74AC
T
= –40°C
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
L
CC
to +85°C
C
Symbol
Parameter
Unit
= 50 pF
L
Min
Typ
Max
Min
Max
Maximum Clock
Frequency
3.3
5.0
90
140
125
175
–
–
75
125
–
–
f
t
t
t
Mhz
ns
3–3
3–6
3–6
3–6
max
Propagation Delay
Clock to Output
3.3
5.0
4.0
3.0
7.0
5.5
12.5
9.0
3.0
2.5
14.0
10.0
PLH
PHL
PHL
Propagation Delay
Clock to Output
3.3
5.0
4.0
3.0
7.0
5.0
13.0
10.0
3.5
2.5
14.5
11.0
ns
Propagation Delay
MR to Output
3.3
5.0
4.0
3.0
7.0
5.0
13.0
10.0
3.5
2.5
14.0
10.5
ns
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC OPERATING REQUIREMENTS
74AC
74AC
T
= –40°C
A
T
C
= +25°C
= 50 pF
V
CC
(V)
*
Fig.
No.
A
L
to +85°C
= 50 pF
Symbol
Parameter
Unit
C
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
Data to CP
3.3
5.0
3.5
2.5
5.5
4.0
6.0
4.5
t
t
t
t
t
ns
ns
ns
ns
ns
3–9
3–9
3–6
3–6
3–9
s
Hold Time, HIGH or LOW
Data to CP
3.3
5.0
–2.0
–1.0
0
1.0
0
1.0
h
Clock Pulse Width
HIGH or LOW
3.3
5.0
3.5
2.5
5.5
4.0
6.0
4.5
w
MR Pulse Width
HIGH or LOW
3.3
5.0
2.0
1.5
5.5
4.0
6.0
4.5
w
Recovery Time
MR to CP
3.3
5.0
1.5
1.0
3.5
2.0
4.5
3.0
rec
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
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4
MC74AC273, MC74ACT273
DC CHARACTERISTICS
Symbol
74ACT
74ACT
T
A
=
V
(V)
CC
T
= +25°C
–40°C to
+85°C
Parameter
Unit
Conditions
A
Typ
Guaranteed Limits
V
V
V
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
= 0.1 V
– 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V
CC
= 0.1 V
OUT
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
Maximum Low Level
Input Voltage
IL
or V
– 0.1 V
CC
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
= –50 µA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IN IL IH
4.5
5.5
–
–
3.86
4.86
3.76
4.76
V
V
–24 mA
–24 mA
I
OH
V
OL
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
I = 50 µA
OUT
Maximum Low Level
Output Voltage
*V = V or V
IN IL
IH
4.5
5.5
–
–
0.36
0.36
0.44
0.44
V
24 mA
I
OL
24 mA
I
IN
Maximum Input
Leakage Current
5.5
–
±0.1
±1.0
µA
V = V , GND
I
CC
∆I
Additional Max. I /Input
CC
5.5
5.5
5.5
0.6
–
–
–
–
1.5
75
mA
mA
mA
V = V
I
– 2.1 V
CCT
CC
I
V
= 1.65 V Max
= 3.85 V Min
OHD
†Minimum Dynamic
Output Current
OLD
OLD
I
–
–75
V
V
OHD
CC
I
Maximum Quiescent
Supply Current
5.5
–
8.0
80
µA
= V or GND
CC
IN
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT
74ACT
T
= –40°C
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
L
CC
to +85°C
C
Symbol
Parameter
Unit
= 50 pF
L
Min
Typ
Max
Min
Max
Maximum Clock
Frequency
f
t
t
t
5.0
5.0
5.0
5.0
125
200
–
125
–
MHz
ns
3–3
3–6
3–6
3–6
max
Propagation Delay
Clock to Output
3.0
3.0
3.0
6.0
6.5
7.0
10
11
11
2.5
2.5
2.5
11.0
12.0
11.5
PHL
PLH
PHL
Propagation Delay
Clock to Output
ns
Propagation Delay
MR to Output
ns
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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5
MC74AC273, MC74ACT273
AC OPERATING REQUIREMENTS
74ACT
74ACT
= –40°C
T
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
to +85°C
= 50 pF
Symbol
Parameter
Unit
L
C
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
Data to CP
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
3.0
4.5
2.0
4.0
4.0
2.0
5.0
2.0
4.5
4.5
3.0
ns
ns
ns
ns
ns
3–9
3–9
3–6
3–6
3–6
s
Hold Time, HIGH or LOW
Data to CP
–2.5
2.5
h
Clock Pulse Width
HIGH or LOW
w
MR Pulse Width
HIGH or LOW
2.5
w
Recovery Time
MR to CP
–1.0
rec
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Value
Typ
Parameter
Unit
Test Conditions
C
C
Input Capacitance
Power Dissipation Capacitance
4.5
50
pF
pF
V
V
= 5.0 V
= 5.0 V
IN
CC
PD
CC
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6
MC74AC273, MC74ACT273
MARKING DIAGRAMS
PDIP–20
SO–20
TSSOP–20
EIAJ–20
AC273
AWLYYWW
MC74AC273N
AWLYYWW
74AC273
AWLYWW
AC
273
ALYW
ACT273
AWLYYWW
MC74ACT273N
AWLYYWW
74ACT273
AWLYWW
ACT
273
ALYW
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
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7
MC74AC273, MC74ACT273
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
20 PIN PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
20
1
11
10
B
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
L
C
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
–T–
SEATING
PLANE
K
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
N
E
G
J
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
K
L
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
M
M
B
0.25 (0.010)
T
M
N
0
0.020
15
_
0.040
0
_
0.51
15
_
1.01
_
M
M
0.25 (0.010)
T
A
SO–20
DW SUFFIX
20 PIN PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
B
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
A
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
L
SEATING
PLANE
q
_
_
18X e
A1
C
T
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8
MC74AC273, MC74ACT273
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T
U
S
U
0.15 (0.006) T
ąă2. CONTROLLING DIMENSION: MILLIMETER.
ąă3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
ąă4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
ąă5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
ąă6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
ąă7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
0.15 (0.006) T
U
M
A
–V–
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
---
6.60 0.252
4.50 0.169
N
C
1.20
---
D
0.05
0.50
0.15 0.002
0.75 0.020
F
F
G
H
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
–W–
J1
K
C
K1
L
6.40 BSC
0.252 BSC
0
G
D
M
0
8
8
_
_
_
_
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
EIAJ–20
M SUFFIX
20 PIN PLASTIC EIAJ PACKAGE
CASE 967–01
ISSUE O
NOTES:
ąă1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ąă2. CONTROLLING DIMENSION: MILLIMETER.
ąă3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
20
11
Q
1
ąă4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ąă5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN
---
e
A
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.504
0.215
c
A
---
0.05
0.35
0.18
12.35
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
1
b
c
D
E
e
12.80 0.486
5.45 0.201
A
b
1
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
0
10
0.90 0.028
10
_
0.035
0.032
0
_
_
_
Q
0.70
---
1
Z
0.81
---
http://onsemi.com
9
MC74AC273, MC74ACT273
Notes
http://onsemi.com
10
MC74AC273, MC74ACT273
Notes
http://onsemi.com
11
MC74AC273, MC74ACT273
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MC74AC273/D
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