MC74HC00ADG [ONSEMI]
Quad 2-Input NAND Gate; 四路2输入与非门
| 型号： | MC74HC00ADG |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2-Input NAND Gate |
| 文件： | 总6页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC00A
Quad 2−Input NAND Gate
High−Performance Silicon−Gate CMOS
The MC74HC00A is identical in pinout to the LS00. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
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Features
MARKING
DIAGRAMS
14
• Pb−Free Packages are Available*
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2 to 6 V
PDIP−14
N SUFFIX
CASE 646
MC74HC00AN
AWLYYWW
• Low Input Current: 1 mA
1
14
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7 A Requirements
• Chip Complexity: 32 FETs or 8 Equivalent Gates
SOIC−14
D SUFFIX
CASE 751A
HC00A
AWLYWW
1
14
LOGIC DIAGRAM
HC
00A
ALYW
TSSOP−14
DT SUFFIX
CASE 948G
1
A1
3
Y1
2
B1
4
1
A2
6
A
= Assembly Location
Y2
5
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
B2
Y = AB
9
A3
8
Y3
10
B3
12
FUNCTION TABLE
A4
11
Inputs
Output
Y4
13
B4
A
B
Y
PIN 14 = V
CC
PIN 7 = GND
L
L
L
H
L
H
H
H
L
H
H
Pinout: 14−Lead Packages (Top View)
H
V
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
CC
14
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2 GND
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
December, 2004 − Rev. 9
MC74HC00A/D
MC74HC00A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
± 20
± 25
± 50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
L
260
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
_C
ns
t , t
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
r
f
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC00AN
PDIP−14
2000 Units / Box
2000 Units / Box
MC74HC00ANG
PDIP−14
(Pb−Free)
MC74HC00AD
SOIC−14
55 Units / Rail
55 Units / Rail
MC74HC00ADG
SOIC−14
(Pb−Free)
MC74HC00ADR2
MC74HC00ADR2G
SOIC−14
2500 Units / Reel
2500 Units / Reel
SOIC−14
(Pb−Free)
MC74HC00ADT
TSSOP−14*
TSSOP−14*
96 Units / Rail
MC74HC00ADTR2
2500 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HC00A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
Symbol
Parameter
Condition
−55 to 25°C ≤85°C ≤125°C
Unit
V
V
IH
Minimum High−Level Input
Voltage
V
= 0.1V or V −0.1V
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
out
CC
|I | ≤ 20mA
out
V
Maximum Low−Level Input
Voltage
V
= 0.1V or V − 0.1V
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
IL
out
CC
|I | ≤ 20mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V or V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
IH
IL
IL
IL
IL
|I | ≤ 20mA
out
V
in
=V or V
IH
|I | ≤ 2.4mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
out
|I | ≤ 4.0mA
out
|I | ≤ 5.2mA
out
V
OL
Maximum Low−Level Output
Voltage
V
in
= V or V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IH
|I | ≤ 20mA
out
V
in
= V or V
|I | ≤ 2.4mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
IH
out
|I | ≤ 4.0mA
out
|I | ≤ 5.2mA
out
I
Maximum Input Leakage
Current
V
V
= V or GND
6.0
±0.1
±1.0
±1.0
mA
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
6.0
1.0
10
40
CC
in
CC
I
= 0mA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
V
CC
Symbol
Parameter
−55 to 25°C
≤85°C
≤125°C
Unit
V
t
t
,
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
ns
PLH
PHL
19
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
ns
TLH
THL
19
C
Maximum Input Capacitance
10
10
10
pF
in
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V, V = 0 V
CC
EE
22
C
Power Dissipation Capacitance (Per Buffer)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
. For load considerations, see Chapter 2 of the
D
PD CC
CC CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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3
MC74HC00A
t
f
t
r
V
CC
90%
50%
10%
INPUT
A OR B
GND
t
t
PLH
PHL
90%
50%
10%
OUTPUT Y
t
t
THL
TLH
Figure 1. Switching Waveforms
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 2. Test Circuit
A
B
Y
Figure 3. Expanded Logic Diagram
(1/4 of the Device)
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4
MC74HC00A
PACKAGE DIMENSIONS
PDIP−14
N SUFFIX
CASE 646−06
ISSUE N
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
14
1
8
7
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
B
5. ROUNDED CORNERS OPTIONAL.
A
F
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
18.80
6.60
4.69
0.53
1.78
L
0.715
0.240
0.145
0.015
0.040
N
C
−T−
SEATING
PLANE
G
H
J
K
L
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
J
K
D 14 PL
H
G
M
M
N
_
_
M
0.13 (0.005)
0.015
0.039
1.01
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
14
8
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
P 7 PL
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
M
B
0.25 (0.010)
7
1
G
F
R X 45
_
C
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
D 14 PL
M
S
S
0.25 (0.010)
T
B
A
1.27 BSC
0.19
0.10
0
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
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5
MC74HC00A
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
14X K REF
M
S
S
0.10 (0.004)
T U
V
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
B
−U−
L
N
PIN 1
IDENT.
F
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
7
1
DETAIL E
S
K
0.15 (0.006) T U
MILLIMETERS
INCHES
MIN
A
DIM MIN
MAX
5.10
4.50
1.20
0.15
0.75
MAX
0.200
0.177
0.047
0.006
0.030
K1
−V−
A
B
4.90
4.30
−−−
0.193
0.169
−−−
C
J J1
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
SECTION N−N
0.50
0.09
0.09
0.19
0.19
0.60
0.20
0.16
0.30
0.25
0.020
0.004
0.004
0.007
0.007
0.024
0.008
0.006
0.012
0.010
J
J1
K
−W−
C
K1
L
6.40 BSC
0.252 BSC
0
0.10 (0.004)
M
0
8
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
MC74HC00A/D
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