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MC74HC273ADWR2 [ONSEMI]

OCTAL D FLIP FLOP WITH COMMON CLOCK AND RESET; 带公共时钟和复位八路D触发器
MC74HC273ADWR2
型号： MC74HC273ADWR2
厂家： ONSEMI    ONSEMI
描述：

OCTAL D FLIP FLOP WITH COMMON CLOCK AND RESET
带公共时钟和复位八路D触发器

触发器 逻辑集成电路 光电二极管 时钟
文件： 总8页 (文件大小：199K)
中文：  中文翻译
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High–Performance Silicon–Gate CMOS  
The MC74HC273A is identical in pinout to the LS273. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
http://onsemi.com  
This device consists of eight D flip–flops with common Clock and  
Reset inputs. Each flip–flop is loaded with a low–to–high transition of  
the Clock input. Reset is asynchronous and active low.  
MARKING  
DIAGRAMS  
20  
PDIP–20  
N SUFFIX  
CASE 738  
MC74HC273AN  
AWLYYWW  
• Output Drive Capability: 10 LSTTL Loads  
• Outputs Directly Interface to CMOS, NMOS and TTL  
• Operating Voltage Range: 2.0 to 6.0 V  
• Low Input Current: 1.0 µA  
• High Noise Immunity Characteristic of CMOS Devices  
• In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
20  
1
1
20  
SOIC WIDE–20  
DW SUFFIX  
CASE 751D  
HC273A  
AWLYYWW  
20  
1
1
20  
• Chip Complexity: 264 FETs or 66 Equivalent Gates  
HC  
273A  
ALYW  
TSSOP–20  
DT SUFFIX  
CASE 948E  
LOGIC DIAGRAM  
20  
1
2
3
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
1
5
6
4
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
7
8
9
DATA  
INPUTS  
NONINVERTING  
OUTPUTS  
WW = Work Week  
13  
14  
17  
18  
12  
15  
16  
19  
PIN ASSIGNMENT  
RESET  
Q0  
1
2
3
4
5
6
7
8
9
20  
V
CC  
19 Q7  
18 D7  
17 D6  
16 Q6  
15 Q5  
14 D5  
13 D4  
12 Q4  
11  
CLOCK  
D0  
PIN 20 = V  
CC  
PIN 10 = GND  
D1  
1
RESET  
Q1  
FUNCTION TABLE  
Q2  
Inputs  
Reset Clock  
Output  
D2  
D
Q
D3  
L
X
X
H
L
X
X
L
H
L
Q3  
H
H
H
H
GND 10  
11 CLOCK  
L
No Change  
No Change  
ORDERING INFORMATION  
Design Criteria  
Internal Gate Count*  
Value  
66  
Units  
ea  
Device  
Package  
PDIP–20  
Shipping  
1440 / Box  
38 / Rail  
MC74HC273AN  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
Speed Power Product  
1.5  
ns  
MC74HC273ADW  
MC74HC273ADWR2  
MC74HC273ADT  
MC74HC273ADTR2  
SOIC–WIDE  
5.0  
µW  
pJ  
SOIC–WIDE 1000 / Reel  
TSSOP–20 75 / Rail  
.0075  
TSSOP–20 2500 / Reel  
*Equivalent to a two–input NAND gate.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
May, 2000 – Rev. 9  
MC74HC273A/D  
MC74HC273A  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
Unit  
V
This device contains protection  
circuitry to guard against damage  
due to high static voltages or electric  
fields. However, precautions must  
be taken to avoid applications of any  
voltage higher than maximum rated  
voltages to this high–impedance cir-  
V
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)  
DC Output Voltage (Referenced to GND)  
DC Input Current, per Pin  
– 0.5 to + 7.0  
CC  
V
– 0.5 to V  
+ 0.5  
V
in  
CC  
CC  
V
out  
– 0.5 to V  
+ 0.5  
V
I
± 20  
mA  
mA  
mA  
mW  
in  
cuit. For proper operation, V and  
in  
I
I
DC Output Current, per Pin  
± 25  
± 50  
out  
V
should be constrained to the  
out  
range GND (V or V  
)
V
CC  
.
DC Supply Current, V  
and GND Pins  
CC  
in out  
CC  
Unused inputs must always be  
tied to an appropriate logic voltage  
P
D
Power Dissipation in Still Air,  
Plastic DIP†  
SOIC Package†  
TSSOP Package†  
750  
500  
450  
level (e.g., either GND or V ).  
CC  
Unused outputs must be left open.  
T
Storage Temperature  
– 65 to + 150  
C
C
stg  
T
Lead Temperature, 1 mm from Case for 10 Seconds  
Plastic DIP, SOIC or TSSOP Package  
L
260  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C  
SOIC Package: – 7 mW/ C from 65 to 125 C  
TSSOP Package: – 6.1 mW/ C from 65 to 125 C  
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Min  
2.0  
0
Max  
Unit  
V
V
CC  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage, Output Voltage (Referenced to GND)  
Operating Temperature, All Package Types  
6.0  
V , V  
in out  
V
CC  
V
T
A
– 55 + 125  
C
t , t  
r f  
Input Rise and Fall Time  
(Figure 1)  
V
CC  
V
CC  
V
CC  
= 2.0 V  
= 4.5 V  
= 6.0 V  
0
0
0
1000  
500  
400  
ns  
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)  
Guaranteed Limit  
– 55 to  
V
CC  
V
25 C  
Symbol  
Parameter  
Test Conditions  
= V – 0.1 V  
85 C  
125 C  
Unit  
V
IH  
Minimum High–Level Input  
Voltage  
V
2.0  
3.0  
4.5  
6.0  
1.5  
2.1  
3.15  
4.2  
1.5  
2.1  
3.15  
4.2  
1.5  
2.1  
3.15  
4.2  
V
out  
CC  
20 µA  
|I  
|
out  
V
Maximum Low–Level Input  
Voltage  
V
= 0.1 V  
2.0  
3.0  
4.5  
6.0  
0.5  
0.9  
1.35  
1.8  
0.5  
0.9  
1.35  
1.8  
0.5  
0.9  
1.35  
1.8  
V
V
IL  
out  
|I  
|
20 µA  
out  
V
OH  
Minimum High–Level Output  
Voltage  
V
= V  
2.0  
4.5  
6.0  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
in  
IH  
20 µA  
|I  
|
out  
V
in  
= V  
|I  
|I  
|I  
|
|
|
2.4 mA  
6.0 mA  
7.8 mA  
3.0  
4.5  
6.0  
2.48  
3.98  
5.48  
2.34  
3.84  
5.34  
2.2  
3.7  
5.2  
IH  
out  
out  
out  
V
OL  
Maximum Low–Level Output  
Voltage  
V
= V  
|
2.0  
4.5  
6.0  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
V
in  
IL  
20 µA  
|I  
out  
V
in  
= V  
|I  
|I  
|I  
|
|
|
2.4 mA  
6.0 mA  
7.8 mA  
3.0  
4.5  
6.0  
0.26  
0.26  
0.26  
0.33  
0.33  
0.33  
0.4  
0.4  
0.4  
IL  
out  
out  
out  
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2
MC74HC273A  
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)  
Guaranteed Limit  
– 55 to  
V
CC  
V
25 C  
Symbol  
Parameter  
Test Conditions  
= V or GND  
CC  
85 C  
125 C  
Unit  
I
in  
Maximum Input Leakage  
Current  
V
6.0  
6.0  
± 0.1  
± 1.0  
± 1.0  
µA  
in  
I
Maximum Three–State  
Leakage Current  
Output in High–Impedance State  
± 0.5  
± 5.0  
± 10  
µA  
µA  
OZ  
V
V
= V or V  
in  
IL  
= V  
IH  
or GND  
out  
CC  
or GND  
I
Maximum Quiescent Supply  
Current (per Package)  
V
= V  
CC  
= 0 µA  
6.0  
4.0  
40  
160  
CC  
in  
I
out  
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book  
(DL129/D).  
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)  
L
r
f
Guaranteed Limit  
– 55 to  
V
CC  
V
25 C  
Symbol  
Parameter  
Unit  
85 C  
125 C  
f
Maximum Clock Frequency (50% Duty Cycle)  
(Figures 1 and 4)  
2.0  
3.0  
4.5  
6.0  
6.0  
15  
30  
35  
5.0  
10  
24  
28  
4.0  
8.0  
20  
MHz  
max  
24  
t
t
Maximum Propagation Delay, Clock to Q  
(Figures 1 and 4)  
2.0  
3.0  
4.5  
6.0  
145  
90  
29  
180  
120  
36  
220  
140  
44  
ns  
ns  
ns  
pF  
PLH  
PHL  
25  
31  
38  
t
Maximum Propagation Delay, Reset to Q  
(Figures 2 and 4)  
2.0  
3.0  
4.5  
6.0  
145  
90  
29  
180  
120  
36  
220  
140  
44  
PHL  
25  
31  
38  
t
t
Maximum Output Transition Time, Any Output  
(Figures 1 and 4)  
2.0  
3.0  
4.5  
6.0  
75  
27  
15  
13  
95  
32  
19  
16  
110  
36  
22  
TLH  
THL  
19  
C
Maximum Input Capacitance  
10  
10  
10  
in  
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON  
Semiconductor High–Speed CMOS Data Book (DL129/D).  
Typical @ 25°C, V  
= 5.0 V  
CC  
C
Power Dissipation Capacitance (Per Enabled Output)*  
pF  
48  
PD  
2
* Used to determine the no–load dynamic power consumption: P = C  
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).  
V
f + I  
V
. For load considerations, see Chapter 2 of the  
PD CC  
CC CC  
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3
MC74HC273A  
TIMING REQUIREMENTS (C = 50 pF, Input t = t = 6.0 ns)  
L
r
f
Guaranteed Limit  
85 C  
– 55 to 25 C  
125 C  
Max  
V
Volts  
CC  
Symbol  
Parameter  
Fig.  
Unit  
Min  
Max  
Min  
Max  
Min  
t
su  
Minimum Setup Time, Data to Clock  
3
2.0  
3.0  
4.5  
6.0  
60  
23  
12  
10  
75  
27  
15  
13  
90  
32  
18  
15  
ns  
t
Minimum Hold Time, Clock to Data  
3
2
1
2
1
2.0  
3.0  
4.5  
6.0  
3.0  
3.0  
3.0  
3.0  
3.0  
3.0  
3.0  
3.0  
3.0  
3.0  
3.0  
3.0  
ns  
ns  
ns  
ns  
ns  
h
t
Minimum Recovery Time, Reset Inactive to  
Clock  
2.0  
3.0  
4.5  
6.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
rec  
t
Minimum Pulse Width, Clock  
Minimum Pulse Width, Reset  
Maximum Input Rise and Fall Times  
2.0  
3.0  
4.5  
6.0  
60  
23  
12  
10  
75  
27  
15  
13  
90  
32  
18  
15  
w
w
t
2.0  
3.0  
4.5  
6.0  
60  
23  
12  
10  
75  
27  
15  
13  
90  
32  
18  
15  
t , t  
r
2.0  
3.0  
4.5  
6.0  
1000  
800  
500  
400  
1000  
800  
500  
400  
1000  
800  
500  
400  
f
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4
MC74HC273A  
SWITCHING WAVEFORMS  
t
w
t
t
r
f
V
CC  
V
CC  
90%  
50%  
50%  
RESET  
Q
CLOCK  
GND  
GND  
10%  
t
t
PHL  
w
1/f  
max  
50%  
t
t
PHL  
PLH  
t
90%  
50%  
rec  
Q
V
CC  
10%  
CLOCK  
50%  
GND  
t
t
THL  
TLH  
Figure 1.  
Figure 2.  
VALID  
V
CC  
DATA  
50%  
GND  
t
su  
t
h
V
CC  
CLOCK  
50%  
EXPANDED LOGIC DIAGRAM  
GND  
Figure 3.  
C
2
Q
Q
Q
Q
Q
Q
Q
Q
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
3
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D
R
C
5
4
D
R
C
6
7
D
R
TEST POINT  
OUTPUT  
C
9
8
D
R
NONINVERTING  
OUTPUTS  
DEVICE  
UNDER  
TEST  
DATA  
INPUTS  
C
C *  
L
12  
15  
16  
19  
13  
14  
17  
D
R
C
D
R
*Includes all probe and jig capacitance  
C
Figure 4. Test Circuit  
D
R
C
18  
11  
1
D
R
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5
MC74HC273A  
PACKAGE DIMENSIONS  
PDIP–20  
N SUFFIX  
PLASTIC DIP PACKAGE  
CASE 738–03  
ISSUE E  
–A–  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
20  
1
11  
10  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION L TO CENTER OF LEAD WHEN  
FORMED PARALLEL.  
4. DIMENSION B DOES NOT INCLUDE MOLD  
FLASH.  
B
L
C
INCHES  
DIM MIN MAX  
1.070 25.66 27.17  
MILLIMETERS  
MIN MAX  
A
B
C
D
E
F
1.010  
0.240  
0.150  
0.015  
0.050 BSC  
0.050  
0.260  
0.180  
0.022  
6.10  
3.81  
0.39  
1.27 BSC  
1.27  
6.60  
4.57  
0.55  
–T–  
SEATING  
PLANE  
K
M
0.070  
1.77  
N
E
G
0.100 BSC  
2.54 BSC  
J
0.008  
0.110  
0.300 BSC  
0.015  
0.140  
0.21  
2.80  
7.62 BSC  
0
0.51  
0.38  
3.55  
G
F
K
L
M
N
J 20 PL  
D 20 PL  
M
M
0.25 (0.010)  
T B  
0
15  
0.040  
15  
1.01  
0.020  
M
M
0.25 (0.010)  
T A  
SO–20  
DW SUFFIX  
CASE 751D–05  
ISSUE F  
D
A
NOTES:  
1. DIMENSIONS ARE IN MILLIMETERS.  
2. INTERPRET DIMENSIONS AND TOLERANCES  
PER ASME Y14.5M, 1994.  
20  
11  
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD  
PROTRUSION.  
E
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.  
5. DIMENSION B DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE PROTRUSION SHALL  
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT  
MAXIMUM MATERIAL CONDITION.  
1
10  
MILLIMETERS  
DIM MIN  
MAX  
2.65  
0.25  
0.49  
0.32  
B
20X B  
A
A1  
B
C
D
E
e
H
h
2.35  
0.10  
0.35  
0.23  
12.65 12.95  
7.40 7.60  
1.27 BSC  
10.05 10.55  
M
S
S
T
0.25  
A
B
A
0.25  
0.50  
0
0.75  
0.90  
7
L
SEATING  
PLANE  
18X e  
A1  
C
T
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6
MC74HC273A  
PACKAGE DIMENSIONS  
TSSOP–20  
DT SUFFIX  
CASE 948E–02  
ISSUE A  
20X K REF  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
M
S
S
0.10 (0.004)  
T U  
V
S
Y14.5M, 1982.  
0.15 (0.006) T U  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION A DOES NOT INCLUDE MOLD  
FLASH, PROTRUSIONS OR GATE BURRS. MOLD  
FLASH OR GATE BURRS SHALL NOT EXCEED  
0.15 (0.006) PER SIDE.  
4. DIMENSION B DOES NOT INCLUDE  
INTERLEAD FLASH OR PROTRUSION.  
INTERLEAD FLASH OR PROTRUSION SHALL NOT  
EXCEED 0.25 (0.010) PER SIDE.  
5. DIMENSION K DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN  
EXCESS OF THE K DIMENSION AT MAXIMUM  
MATERIAL CONDITION.  
K
K1  
20  
11  
2X L/2  
J J1  
B
L
–U–  
PIN 1  
IDENT  
SECTION N–N  
1
10  
0.25 (0.010)  
6. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
N
S
7. DIMENSION A AND B ARE TO BE  
DETERMINED AT DATUM PLANE –W–.  
0.15 (0.006) T U  
M
A
–V–  
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN  
MAX  
0.260  
0.177  
0.047  
0.006  
0.030  
A
B
C
6.40  
4.30  
–––  
6.60 0.252  
4.50 0.169  
1.20  
N
–––  
D
F
0.05  
0.50  
0.15 0.002  
0.75 0.020  
F
G
H
J
J1  
K
K1  
L
0.65 BSC  
0.026 BSC  
DETAIL E  
0.27  
0.09  
0.09  
0.19  
0.19  
0.37  
0.011  
0.015  
0.008  
0.006  
0.012  
0.010  
0.20 0.004  
0.16 0.004  
0.30 0.007  
0.25 0.007  
–W–  
C
6.40 BSC  
0.252 BSC  
G
D
M
0
8
0
8
H
DETAIL E  
0.100 (0.004)  
–T– SEATING  
PLANE  
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7
MC74HC273A  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes  
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular  
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or  
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be  
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.  
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intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or  
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold  
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable  
attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim  
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.  
PUBLICATION ORDERING INFORMATION  
NORTH AMERICA Literature Fulfillment:  
CENTRAL/SOUTH AMERICA:  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
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Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada  
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada  
Email: ONlit@hibbertco.com  
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Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)  
Toll Free from Hong Kong & Singapore:  
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada  
001–800–4422–3781  
N. American Technical Support: 800–282–9855 Toll Free USA/Canada  
Email: ONlit–asia@hibbertco.com  
EUROPE: LDC for ON Semiconductor – European Support  
German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)  
Email: ONlit–german@hibbertco.com  
JAPAN: ON Semiconductor, Japan Customer Focus Center  
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Phone: 81–3–5740–2745  
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)  
Email: ONlit–french@hibbertco.com  
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)  
Email: ONlit@hibbertco.com  
Email: r14525@onsemi.com  
ON Semiconductor Website: http://onsemi.com  
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781  
For additional information, please contact your local  
Sales Representative.  
*Available from Germany, France, Italy, England, Ireland  
MC74HC273A/D  

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