概述
规格参数
数据手册
替代型号MC74HC30ADR2G 概述
8-Input NAND Gate 逻辑芯片 栅极
MC74HC30ADR2G 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | SOIC |
| 包装说明： | SOP, SOP14,.25 | 针数： | 14 |
| Reach Compliance Code： | compliant | HTS代码： | 8542.39.00.01 |
| Factory Lead Time： | 51 weeks | 风险等级： | 5.75 |
| 系列： | HC/UH | JESD-30 代码： | R-PDSO-G14 |
| JESD-609代码： | e3 | 长度： | 8.65 mm |
| 负载电容（CL）： | 50 pF | 逻辑集成电路类型： | NAND GATE |
| 最大I（ol）： | 0.004 A | 湿度敏感等级： | 1 |
| 功能数量： | 1 | 输入次数： | 8 |
| 端子数量： | 14 | 最高工作温度： | 125 °C |
| 最低工作温度： | -55 °C | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装等效代码： | SOP14,.25 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 包装方法： | TAPE AND REEL | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 电源： | 2/6 V | Prop。Delay @ Nom-Sup： | 53 ns |
| 传播延迟（tpd）： | 265 ns | 认证状态： | Not Qualified |
| 施密特触发器： | NO | 座面最大高度： | 1.75 mm |
| 子类别： | Gates | 最大供电电压 (Vsup)： | 6 V |
| 最小供电电压 (Vsup)： | 2 V | 标称供电电压 (Vsup)： | 4.5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | MILITARY | 端子面层： | Tin (Sn) |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 3.9 mm |
MC74HC30ADR2G 数据手册
通过下载MC74HC30ADR2G数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载MC74HC30A
8-Input NAND Gate
High−Performance Silicon−Gate CMOS
The MC74HC30 is identical in pinout to the LS30. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
http://onsemi.com
Features
MARKING
DIAGRAMS
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
14
SOIC−14
D SUFFIX
CASE 751A
HC30AG
AWLYWW
14
14
• High Noise Immunity Characteristic of CMOS Devices
• These are Pb−Free Devices
1
1
1
A
2
14
1
B
3
TSSOP−14
DT SUFFIX
CASE 948G
HC
C
4
30A
D
E
F
8
5
Y
Y = ABCDEFGH
ALYW
ꢀ
1
6
ꢀ
11
12
G
H
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
PINS 9, 10, 13 = NO CONNECTION
PIN 14 = V
CC
PIN 7 = GND
WW, W = Work Week
G or = Pb−Free Package
ꢀ
Figure 1. Logic Diagram
(Note: Microdot may be in either location)
PIN ASSIGNMENT
A
B
1
2
14
V
CC
13 NC
C
D
3
4
12
11
H
G
E
F
5
6
7
10 NC
9
8
NC
Y
GND
NC = NO CONNECTION
FUNCTION TABLE
Output
Y
Inputs A through H
All inputs H
One or more inputs L
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
June, 2013 − Rev. 1
MC74HC30A/D
MC74HC30A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
−0.5 to +7.0
CC
V
−1.5 to V + 1.5
V
in
CC
V
out
−0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
SOIC Package
TSSOP Package
500
TBD
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
−55
+125
°C
ns
t , t
Input Rise and Fall Time
(Figure 2)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
r
f
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
− 55 to
25°C
V
V
CC
v 85°C
1.5
3.15
4.2
v 125°C
1.5
3.15
4.2
Symbol
Parameter
Test Conditions
= 0.1 V or V − 0.1 V
|I | v 20 mA
Unit
V
IH
Minimum High−Level Input
V
2.0
4.5
6.0
1.5
3.15
4.2
V
out
CC
Voltage
out
V
Maximum Low−Level Input
Voltage
V
= 0.1 V or V − 0.1 V
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
IL
out
CC
|I | v 20 mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
IH
|I | v 20 mA
out
V
in
= V or V
|I | v 4.0 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
IH
IL
out
|I | v 5.2 mA
out
V
OL
Maximum Low−Level Output
Voltage
V
= V or V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
IL
|I | v 20 mA
out
V
= V or V
|I | v 4.0 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
in
in
IH
IL
out
|I | v 5.2 mA
out
I
Maximum Input Leakage Current
V
V
= V or GND
6.0
6.0
0.1
2
1.0
20
1.0
40
mA
mA
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
CC
in
CC
I
= 0 mA
out
http://onsemi.com
2
MC74HC30A
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
− 55 to
V
V
CC
25°C
v 85°C
v 125°C
Symbol
Parameter
Unit
t
t
,
Maximum Propagation Delay, Any Input to Output Y
(Figures 2 and 3)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
PLH
PHL
t
t
,
Maximum Output Transition Time, Any Output
(Figures 2 and 3)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
TLH
THL
C
Maximum Input Capacitance
−
10
10
10
pF
in
Typical @ 25°C, V = 5.0 V
CC
27
C
Power Dissipation Capacitance (Per Gate)
pF
PD
t
r
t
f
TEST POINT
V
CC
90%
50%
10%
ANY INPUT
OUTPUT Y
OUTPUT
DEVICE
GND
t
t
PLH
PHL
UNDER
TEST
C *
L
90%
50%
10%
t
t
TLH
THL
*Includes all probe and jig capacitance
Figure 2. Switching Waveforms
Figure 3. Test Circuit
1
A
2
B
3
C
4
D
8
Y
5
E
6
F
11
G
12
H
Figure 4. Expanded Logic Diagram
Package
ORDERING INFORMATION
Device
†
Shipping
MC74HC30ADG
SOIC−14
(Pb−Free)
55 Units/Rail
2500/Tape & Reel
96 Units / Tube
2500/Tape & Reel
MC74HC30ADR2G
MC74HC30ADTG
MC74HC30ADTR2G
SOIC−14
(Pb−Free)
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
DATE 03 FEB 2016
SCALE 1:1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
0.10
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
1.27
PITCH
WW
G
= Work Week
= Pb−Free Package
14X
0.58
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
STYLE 2:
CANCELLED
STYLE 3:
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
STYLE 6:
STYLE 7:
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70246A
TSSOP−14 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
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MC74HC30ADR2G CAD模型
引脚图
封装焊盘图
MC74HC30ADR2G 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| MC74HC30ADG | ONSEMI | 8-Input NAND Gate | 完全替代 |
|
| CD74HC30M | TI | High Speed CMOS Logic 8-Input NAND Gate | 类似代替 |
|
MC74HC30ADR2G 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| MC74HC30ADTG | ONSEMI | 8-Input NAND Gate | 获取价格 |
|
| MC74HC30ADTR2G | ONSEMI | 8-Input NAND Gate | 获取价格 |
|
| MC74HC30D | MOTOROLA | 8-Input NAND Gate | 获取价格 |
|
| MC74HC30DS | ROCHESTER | NAND Gate | 获取价格 |
|
| MC74HC30J | ROCHESTER | NAND Gate | 获取价格 |
|
| MC74HC30JD | ROCHESTER | NAND Gate | 获取价格 |
|
| MC74HC30N | MOTOROLA | 8-Input NAND Gate | 获取价格 |
|
| MC74HC30NDS | MOTOROLA | NAND Gate, CMOS, PDIP14 | 获取价格 |
|
| MC74HC30NS | ROCHESTER | NAND Gate | 获取价格 |
|
| MC74HC32A | MOTOROLA | Quad 2-Input OR Gate | 获取价格 |
|
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