MC74HC365ADR2G [ONSEMI]
Hex 3-State Noninverting Buffer with Common Enables; 六角三态同相缓冲与普通启用
| 型号： | MC74HC365ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | Hex 3-State Noninverting Buffer with Common Enables |
| 文件： | 总8页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC365A
Hex 3-State Noninverting
Buffer with Common
Enables
High−Performance Silicon−Gate CMOS
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MARKING
The MC74HC365A is identical in pinout to the LS365. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
DIAGRAMS
This device is a high−speed hex buffer with 3−state outputs and two
common active−low Output Enables. When either of the enables is
high, the buffer outputs are placed into high−impedance states. The
HC365A has noninverting outputs.
16
PDIP−16
N SUFFIX
CASE 648
MC74HC365AN
AWLYYWWG
16
16
1
1
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
16
SOIC−16
D SUFFIX
CASE 751B
HC365AG
AWLYWW
• Low Input Current: 1.0 mA
1
1
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
16
No. 7A
TSSOP−16
DT SUFFIX
CASE 948F
HC
365A
ALYWG
G
• Chip Complexity: 90 FETs or 22.5 Equivalent Gates
• These are Pb−Free Devices*
16
1
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
December, 2009 − Rev. 2
MC74HC365A/D
MC74HC365A
OUTPUT
ENABLE 1
2
3
5
7
1
2
3
4
5
6
7
8
16
15
V
CC
A0
A1
A2
A3
A4
A5
Y0
Y1
Y2
Y3
Y4
Y5
OUTPUT
ENABLE 2
A0
4
Y0
14 A5
13 Y5
12 A4
11 Y4
10 A3
A1
6
Y1
A2
10
12
14
9
Y2
GND
9
Y3
11
13
Figure 1. Pin Assignment
1
OUTPUT ENABLE 1
PIN 16 = V
CC
PIN 8 = GND
FUNCTION TABLE
15
OUTPUT ENABLE 2
Inputs
Output
Enable Enable
Figure 2. Logic Diagram
1
2
A
Y
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
X = don’t care
Z = high impedance
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC365ANG
PDIP−16
500 Units / Rail
48 Units / Rail
(Pb−Free)
MC74HC365ADG
SOIC−16
(Pb−Free)
MC74HC365ADR2G
MC74HC365ADTR2G
SOIC−16
(Pb−Free)
2500 Units / Reel
2500 Units / Reel
TSSOP−16*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HC365A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
L
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
_C
ns
t , t
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
V
CC
= 2.0 V
= 3.0 V
= 4.5 V
= 6.0 V
0
0
0
0
1000
600
500
400
r
f
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
1.5
2.1
3.15
4.2
V
v 85_C v 125_C
Symbol
Parameter
Test Conditions
= V – 0.1 V
|I | v 20 μA
Unit
V
IH
Minimum High−Level Input
V
2.0
3.0
4.5
6.0
1.5
2.1
1.5
2.1
V
out
CC
Voltage
out
3.15
4.2
3.15
4.2
V
Maximum Low−Level Input
Voltage
V
= 0.1 V
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
IL
out
|I | v 20 μA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
|I | v 20 μA
out
V
in
= V
|I | v 3.6 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
IH
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
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3
MC74HC365A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
0.1
0.1
0.1
v 85_C
0.1
0.1
0.1
v 125_C
V
Symbol
Parameter
Test Conditions
Unit
V
OL
Maximum Low−Level Output
V
= V
IL
|I | v 20 μA
2.0
4.5
6.0
0.1
0.1
0.1
V
in
Voltage
out
V
= V
|I | v 3.6 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
in
in
IL
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
I
Maximum Input Leakage Current
V
= V or GND
6.0
6.0
0.1
0.5
1.0
5.0
1.0
10
μA
μA
in
CC
I
Maximum Three−State
Output in High−Impedance State
V = V or V
in
OZ
Leakage Current
IL
IH
V
out
= V or GND
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V or GND
= 0 μA
6.0
4
40
160
μA
CC
in
CC
I
out
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
25_C
120
60
24
20
V
v 85_C v 125_C
Symbol
Parameter
Unit
t
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
2.0
3.0
4.5
6.0
150
75
180
90
ns
PLH
t
PHL
30
36
26
31
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
220
110
44
275
140
55
330
170
66
ns
ns
ns
PLZ
t
PHZ
37
47
56
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
220
110
44
275
140
55
330
170
66
PZL
t
PZH
37
47
56
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
TLH
t
THL
C
Maximum Input Capacitance
—
—
10
15
10
15
10
15
pF
pF
in
C
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
out
Typical @ 25°C, V = 5.0 V
CC
60
C
Power Dissipation Capacitance (Per Buffer)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
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4
MC74HC365A
SWITCHING WAVEFORMS
V
CC
50%
t
r
t
f
OUTPUT ENABLE
GND
V
CC
90%
50%
10%
t
t
PLZ
PZL
INPUT A
HIGH
GND
IMPEDANCE
50%
t
t
PHL
PLH
OUTPUT Y
OUTPUT Y
10%
90%
V
V
OL
90%
50%
10%
t
t
PHZ
PZH
OUTPUT Y
OH
50%
HIGH
t
t
THL
TLH
IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kΩ
CONNECT TO V WHEN
CC
OUTPUT
TESTING t AND t
PLZ
.
PZL
DEVICE
UNDER
TEST
DEVICE
CONNECT TO GND WHEN
TESTING t AND t
UNDER
TEST
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
LOGIC DETAIL
TO OTHER
FIVE BUFFERS
ONE OF 6
BUFFERS
V
CC
Y
INPUT A
OUTPUT ENABLE 1
OUTPUT ENABLE 2
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5
MC74HC365A
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
C
L
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
M
S
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
J
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
G
0.21
0.38
3.30
7.74
10
D 16 PL
2.80
7.50
0
M
M
0.25 (0.010)
T
A
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
M
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
0.25 (0.010)
T
B
A
SOLDERING FOOTPRINT
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
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6
MC74HC365A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE B
NOTES:
16X KREF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
U
0.15 (0.006) T
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T
U
A
M
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
1.20
−−− 0.047
F
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
D
G
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
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7
MC74HC365A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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MC74HC365A/D
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