MC74HC373ADTG [ONSEMI]
Octal 3−State Non−Inverting Transparent Latch High−Performance Silicon−Gate CMOS; 八路三态非反相透明锁存器高性能硅栅CMOS
| 型号： | MC74HC373ADTG |
| 厂家： | 
ONSEMI |
| 描述： | Octal 3−State Non−Inverting Transparent Latch High−Performance Silicon−Gate CMOS |
| 文件： | 总10页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC373A
Octal 3−State Non−Inverting
Transparent Latch
High−Performance Silicon−Gate CMOS
The MC74HC373A is identical in pinout to the LS373. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
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MARKING
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high−impedance state. Thus, data may be latched even when the
outputs are not enabled.
DIAGRAMS
20
20
PDIP−20
N SUFFIX
CASE 738
MC74HC373AN
AWLYYWWG
1
1
The HC373A is identical in function to the HC573A which has the
data inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
20
SOIC−20
20
74HC373A
AWLYYWWG
DW SUFFIX
CASE 751D
The HC373A is the non−inverting version of the HC533A.
1
Features
1
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
20
HC
373A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
20
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 186 FETs or 46.5 Equivalent Gates
• Pb−Free Packages are Available*
1
1
20
SOEIAJ−20
F SUFFIX
CASE 967
20
74HC373A
AWLYWWG
1
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G
= Pb−Free Package
= Pb−Free Package
G
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
July, 2005 − Rev. 12
MC74HC373A/D
MC74HC373A
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LOGIC DIAGRAM
D0
D1
Q1
Q2
D2
D3
Q3
2
5
3
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
6
7
8
9
DATA
NONINVERTING
OUTPUTS
INPUTS
13
12
15
16
19
LATCH
ENABLE
GND 10
14
17
18
D5
D6
D7
FUNCTION TABLE
11
1
PIN 20 = V
CC
PIN 10 = GND
Inputs
Output
LATCH ENABLE
Output Latch
Enable Enable
OUTPUT ENABLE
D
Q
L
L
L
H
H
L
H
L
X
X
H
L
No Change
Z
H
X
X = Don’t Care
Z = High Impedance
Design Criteria
Internal Gate Count*
Value
46.5
1.5
Units
ea
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
ns
5.0
mW
pJ
0.0075
*Equivalent to a two−input NAND gate.
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2
MC74HC373A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
V
V
CC
V
– 0.5 to V + 0.5
CC
in
V
– 0.5 to V + 0.5
V
out
CC
I
20
35
75
mA
mA
mA
mW
in
cuit. For proper operation, V and
I
DC Output Current, per Pin
in
out
CC
V
out
should be constrained to the
I
DC Supply Current, V and GND Pins
CC
range GND v (V or V ) v V
.
CC
in
out
P
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
Unused inputs must always be
tied to an appropriate logic voltage
D
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
L
260
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
CC
V , V
in out
V
V
CC
T
A
– 55
+ 125
_C
ns
t , t
r
Input Rise and Fall Time
(Figure 1)
V
V
V
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
f
CC
CC
CC
ORDERING INFORMATION
†
Device
MC74HC373AN
Package
Shipping
PDIP−20
18 Units / Box
18 Units / Box
MC74HC373ANG
PDIP−20
(Pb−Free)
MC74HC373ADW
MC74HC373ADWG
SOIC−20 WIDE
38 Units / Rail
38 Units / Rail
SOIC−20 WIDE
(Pb−Free)
MC74HC373ADWR2
MC74HC373ADWR2G
SOIC−20 WIDE
1000 Units / Reel
1000 Units / Reel
SOIC−20 WIDE
(Pb−Free)
MC74HC373ADT
MC74HC373ADTG
MC74HC373ADTR2
MC74HC373ADTR2G
MC74HC373AF
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
SOEIAJ−20
75 Units / Rail
75 Units / Rail
2500 Units / Reel
2500 Units / Reel
40 Units / Rail
40 Units / Rail
MC74HC373AFG
SOEIAJ−20
(Pb−Free)
MC74HC373AFEL
MC74HC373AFELG
SOEIAJ−20
2000 Units / Reel
2000 Units / Reel
SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
MC74HC373A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
Symbol
Parameter
Test Conditions
= V – 0.1 V
|I | v 20 mA
– 55 to 25_C v 85_C v 125_C
Unit
V
Minimum High−Level Input
Voltage
V
2.0
3.0
4.5
6.0
1.5
2.1
1.5
2.1
1.5
2.1
V
IH
out
CC
out
3.15
4.2
3.15
4.2
3.15
4.2
V
Maximum Low−Level Input
Voltage
V
= 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
|I | v 20 mA
out
V
Minimum High−Level Output
Voltage
V
in
= V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
OH
IH
|I | v 20 mA
out
V
= V
|I | v 2.4 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
in
IH
IL
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
V
Maximum Low−Level Output
Voltage
V
V
in
= V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
|I | v 20 mA
out
V
= V
|I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
in
IL
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
I
Maximum Input Leakage Current
V
in
= V or GND
6.0
6.0
0.1
0.5
1.0
5.0
1.0
10
mA
mA
in
CC
I
Maximum Three−State
Leakage Current
Output in High−Impedance State
= V or V
OZ
V
in
IL
IH
V
out
= V or GND
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V or GND
= 0 mA
6.0
4.0
40
160
mA
CC
in
CC
I
out
NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
V
CC
– 55 to 25_C v 85_C v 125_C
V
Symbol
Parameter
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
Unit
ns
t
t
2.0
3.0
4.5
6.0
125
80
155
110
31
190
130
38
PLH
PHL
25
21
26
32
t
t
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
2.0
3.0
4.5
6.0
140
90
28
175
120
35
210
140
42
ns
ns
ns
ns
PLH
PHL
24
30
36
t
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
190
125
38
225
150
45
PLZ
t
t
PHZ
26
33
38
t
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
190
125
38
225
150
45
PZL
PZH
26
33
38
t
t
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
TLH
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
out
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
36
f + I V . For load considerations, see Chapter 2 of the
CC CC
C
Power Dissipation Capacitance (Per Enabled Output)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
V
D
PD CC
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4
MC74HC373A
TIMING REQUIREMENTS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to 25_C
v 85_C
v 125_C
V
Volts
CC
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Figure
Unit
t
Minimum Setup Time, Input D to Latch Enable
Minimum Hold Time, Latch Enable to Input D
Minimum Pulse Width, Latch Enable
4
2.0
3.0
4.5
6.0
25
20
5.0
5.0
30
25
6.0
6.0
40
30
8.0
7.0
ns
su
t
4
2
1
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5 0
5.0
5.0
5.0
5.0
5.0
ns
ns
ns
h
t
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
w
t , t
r
Maximum Input Rise and Fall Times
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
f
SWITCHING WAVEFORMS
t
r
t
f
t
w
V
V
CC
CC
90%
50%
10%
LATCH ENABLE
50%
INPUT D
GND
GND
t
t
PHL
PLH
t
t
PHL
PLH
90%
50%
10%
Q
Q
50%
t
t
THL
TLH
Figure 1.
Figure 2.
V
CC
OUTPUT
ENABLE
50%
GND
VALID
t
t
PLZ
PZL
V
CC
HIGH
INPUT D
50%
IMPEDANCE
50%
GND
Q
Q
t
su
t
10%
90%
h
V
V
OL
t
t
V
PZH
PHZ
CC
LATCH ENABLE
50%
OH
GND
1.3 V
HIGH
IMPEDANCE
Figure 3.
Figure 4.
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5
MC74HC373A
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kW
CONNECT TO V WHEN
CC
OUTPUT
TESTING t AND t
.
PLZ PZL
CONNECT TO GND WHEN
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
TESTING t
AND t
.
PZH
C *
L
PHZ
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5.
Figure 6.
D0
D1
D2
D3
D4
13
D5
14
D6
17
D7
18
3
4
7
8
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE
LE
LE
LE
LE
LE
LE
LE
11
1
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
Q0
Q1
Q2
Q3
Figure 7. EXPANDED LOGIC DIAGRAM
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6
MC74HC373A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
INCHES
DIM MIN MAX
MILLIMETERS
L
C
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
1.070
0.260
0.180
0.022
0.050 BSC
1.27 BSC
−T−
SEATING
PLANE
K
0.050
0.070
1.27
1.77
G
J
0.100 BSC
2.54 BSC
M
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
N
E
K
L
0.300 BSC
7.62 BSC
G
F
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
J 20 PL
_
_
_
D 20 PL
M
M
B
0.25 (0.010)
T
M
M
A
0.25 (0.010)
T
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
B
20X B
M
S
S
B
0.25
T A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
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7
MC74HC373A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING
20X K REF
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T
U
S
U
0.15 (0.006) T
K
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
K1
20
11
2X L/2
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
0.25 (0.010)
N
S
0.15 (0.006) T
U
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
−W−
F
C
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
J
G
D
J1
K
H
DETAIL E
0.100 (0.004)
−T− SEATING
K1
L
6.40 BSC
0.252 BSC
0
M
0
8
8
_
_
_
_
PLANE
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8
MC74HC373A
PACKAGE DIMENSIONS
SOEIAJ−20
F SUFFIX
CASE 967−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
20
11
E
Q
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
1
H
E
E
_
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
1
10
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
A
−−−
0.05
2.05
A
1
A
b
1
0.20 0.002
0.50 0.014
0.27 0.007
12.80 0.486
5.45 0.201
0.008
0.020
0.011
0.504
0.215
b
c
0.35
0.18
M
0.10 (0.004)
0.13 (0.005)
D
E
e
12.35
5.10
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
0
10
0.035
_
_
_
_
0.70
−−−
1
Z
0.81
−−− 0.032
http://onsemi.com
9
MC74HC373A
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