MC74HC390 [ONSEMI]
Dual 4-Stage Binary Ripple Counter with ±2 and ±5 Sections; 双4级二进制纹波计数器与÷ 2 ÷和5节
| 型号： | MC74HC390 |
| 厂家： | 
ONSEMI |
| 描述： | Dual 4-Stage Binary Ripple Counter with ±2 and ±5 Sections |
| 文件： | 总8页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
÷
÷
High–Performance Silicon–Gate CMOS
The MC74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4–bit counters, each
composed of a divide–by–two and a divide–by–five section. The
divide–by–two and divide–by–five counters have separate clock
inputs, and can be cascaded to implement various combinations of ÷ 2
and/or ÷ 5 up to a ÷ 100 counter.
Flip–flops internal to the counters are triggered by high–to–low
transitions of the clock input. A separate, asynchronous reset is
provided for each 4–bit counter. State changes of the Q outputs do not
occur simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390A.
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MARKING
DIAGRAMS
16
PDIP–16
N SUFFIX
CASE 648
MC74HC390AN
AWLYYWW
16
16
1
1
16
SO–16
D SUFFIX
CASE 751B
HC390A
AWLYWW
1
1
16
HC
390A
ALYW
TSSOP–16
DT SUFFIX
CASE 948F
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
16
1
1
• Low Input Current: 1 µA
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No 7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates
PIN ASSIGNMENT
LOGIC DIAGRAM
CLOCK A
1
2
3
4
5
6
7
8
16
15
V
a
CC
CLOCK A
RESET a
b
÷ 2
COUNTER
3, 13
1, 15
Q
A
CLOCK A
Q
Aa
14 RESET b
13
12 CLOCK B
CLOCK B
Q
Ab
a
Q
Ba
b
5, 11
Q
Ca
11
10
9
Q
Bb
Q
B
Q
C
Q
D
÷ 5
COUNTER
6, 10
7, 9
4, 12
2, 14
Q
Da
Q
Cb
CLOCK B
RESET
GND
Q
Db
PIN 16 = V
PIN 8 = GND
CC
FUNCTION TABLE
ORDERING INFORMATION
Clock
Device
Package
PDIP–16
SOIC–16
SOIC–16
TSSOP–16
Shipping
2000 / Box
48 / Rail
A
B
Reset
Action
MC74HC390AN
X
X
H
Reset
÷ 2 and ÷ 5
MC74HC390AD
X
L
L
Increment
MC74HC390ADR2
MC74HC390ADT
MC74HC390ADTR2
2500 / Reel
96 / Rail
÷ 2
X
Increment
÷ 5
TSSOP–16 2500 / Reel
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 2
MC74HC390A/D
MC74HC390A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
CC
V
out
– 0.5 to V
+ 0.5
V
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
and GND Pins
CC
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
L
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
V
CC
= 2.0 V
= 3.0 V
= 4.5 V
= 6.0 V
0
0
0
0
1000
600
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
IL
20 µA
|I
|
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
IL out
out
out
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IH
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IL
20 µA
|I
|
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
IL out
out
out
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2
MC74HC390A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
85 C
125 C
Unit
I
Maximum Input Leakage
Current
V
V
= V
= V
or GND
6.0
± 0.1
± 1.0
± 1.0
µA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
or GND
6.0
4
40
160
µA
CC
in
CC
I
= 0 µA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
f
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
85 C
125 C
Unit
f
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
2.0
3.0
4.5
6.0
10
15
30
50
9
8
MHz
max
14
28
45
12
25
40
t
t
t
t
t
,
Maximum Propagation Delay, Clock A to QA
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
24
20
80
45
30
26
90
50
36
31
ns
ns
ns
ns
ns
ns
ns
pF
PLH
t
PHL
,
Maximum Propagation Delay, Clock A to QC
(QA connected to Clock B)
(Figures 1 and 3)
2.0
3.0
4.5
6.0
200
160
58
250
185
65
300
210
70
PLH
t
PHL
49
62
68
,
Maximum Propagation Delay, Clock B to QB
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
26
22
80
45
33
28
90
50
39
33
PLH
t
PHL
,
Maximum Propagation Delay, Clock B to QC
(Figures 1 and 3)
2.0
3.0
4.5
6.0
90
56
37
31
105
70
46
180
100
56
PLH
t
PHL
39
48
,
Maximum Propagation Delay, Clock B to QD
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
26
22
80
45
33
28
90
50
39
33
PLH
t
PHL
t
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
3.0
4.5
6.0
80
48
30
26
95
65
38
33
110
75
44
PHL
39
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
TLH
THL
19
C
Maximum Input Capacitance
—
10
10
10
in
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Informationon typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Counter)*
pF
35
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
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3
MC74HC390A
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
t
Minimum Recovery Time, Reset Inactive to Clock A or Clock B
(Figure 2)
2.0
3.0
4.5
6.0
25
15
10
9
30
20
13
11
40
30
15
13
ns
rec
t
Minimum Pulse Width, Clock A, Clock B
(Figure 1)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
ns
ns
ns
w
w
19
t
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
75
27
20
18
95
32
24
22
110
36
30
28
t , t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
f
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
PIN DESCRIPTIONS
INPUTS
OUTPUTS
Q (Pins 3, 13)
A
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
Clock A is the clock input to the ÷ 2 counter; Clock B is
the clock input to the ÷ 5 counter. The internal flip–flops are
toggled by high–to–low transitions of the clock input.
Output of the ÷ 2 counter.
Q , Q , Q (Pins 5, 6, 7, 9, 10, 11)
B
C
D
Outputs of the ÷ 5 counter. Q is the most significant bit.
D
CONTROL INPUTS
Reset (Pins 2, 14)
Q
is the least significant bit when the counter is connected
for BCD output as in Figure 4. Q is the least significant bit
A
B
Asynchronous reset. A high at the Reset input prevents
when the counter is operating in the bi–quinary mode as in
Figure 5.
counting, resets the internal flip–flops, and forces Q
through Q low.
D
A
SWITCHING WAVEFORMS
t
t
r
f
t
w
V
90%
50%
CC
V
CC
CLOCK
10%
50%
RESET
10%
GND
GND
t
w
t
PHL
1/f
max
50%
Q
t
t
PHL
PLH
90%
50%
10%
t
Q
rec
V
CC
50%
CLOCK
t
t
THL
TLH
GND
Figure 1.
Figure 2.
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4
MC74HC390A
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 3.
EXPANDED LOGIC DIAGRAM
1, 15
4, 12
Q
C
CLOCK A
CLOCK B
3, 13
5, 11
D
D
Q
Q
A
R
R
Q
Q
C
Q
B
Q
Q
C
6, 10
Q
C
D
R
C
7, 9
Q
D
D
Q
R
2, 14
RESET
TIMING DIAGRAM
(Q Connected to Clock B)
A
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
CLOCK A
RESET
Q
A
Q
B
Q
C
Q
D
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5
MC74HC390A
APPLICATIONS INFORMATION
Each half of the MC54/74HC390A has independent ÷ 2
and ÷ 5 sections (except for the Reset function). The ÷ 2 and
÷ 5 counters can be connected to give BCD or bi–quinary
To obtain a bi–quinary count sequence, the input signals
connected to the Clock B input, and output Q is connected
D
to the Clock A input (Figure 5). Q provides a 50% duty
A
(2–5) count sequences. If Output Q is connected to the
cycle output. The bi–quinary count sequence function table
is given in Table 2.
A
Clock B input (Figure 4), a decade divider with BCD output
is obtained. The function table for the BCD count sequence
is given in Table 1.
Table 1. BCD Count Sequence*
Output
Table 2. Bi–Quinary Count Sequence**
Output
Count
Count
Q
Q
Q
Q
Q
Q
Q
Q
B
D
C
B
A
A
D
C
0
1
2
3
4
5
6
7
8
9
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
0
1
2
3
4
8
9
10
11
12
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
H
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
H
H
L
L
L
L
H
L
L
L
L
H
L
H
H
L
L
L
H
H
L
L
H
H
H
H
L
L
H
H
L
L
L
*Q connected to Clock B input.
A
**Q connected to Clock A input.
D
CONNECTION DIAGRAMS
1, 15
3, 13
1, 15
3, 13
Q
A
Q
A
÷ 2
COUNTER
÷ 2
COUNTER
CLOCK A
CLOCK A
5, 11
6, 10
7, 9
5, 11
6, 10
7, 9
Q
Q
4, 12
2, 14
B
4, 12
2, 14
B
÷ 5
COUNTER
CLOCK B
RESET
CLOCK B
RESET
÷ 5
COUNTER
Q
C
Q
D
Q
C
Q
D
Figure 4. BCD Count
Figure 5. Bi-Quinary Count
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6
MC74HC390A
PACKAGE DIMENSIONS
PDIP–16
N SUFFIX
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
C
L
0.250 0.270
0.145 0.175
0.015 0.021
0.040 0.070
0.100 BSC
6.35
3.69
0.39
1.02
6.85
4.44
0.53
S
1.77
SEATING
PLANE
–T
–
G
H
J
K
L
M
S
2.54 BSC
1.27 BSC
0.38
3.30
7.74
0.050 BSC
M
K
0.008 0.015
0.110 0.130
0.295 0.305
0.21
2.80
7.50
0°
H
J
G
D 16 PL
0°
10°
10°
M
M
0.25 (0.010)
T
A
0.020 0.040
0.51
1.01
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN MAX
DIM MIN
MAX
A
B
C
D
F
G
J
K
M
P
9.80 10.00
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
F
K
R X 45°
3.80
1.35
0.35
0.40
4.00
1.75
0.49
1.25
C
1.27 BSC
–T
0.19
0.10
0°
0.25
0.25
7°
0.008 0.009
0.004 0.009
J
SEAT–ING
M
PLANE
D 16 PL
0°
7°
5.80
0.25
6.20
0.50
0.229 0.244
0.010 0.019
M
S
S
0.25 (0.010)
T
B
A
R
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7
MC74HC390A
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T U
V
NOTES:
S
0.15 (0.006) T U
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
B
–U–
SECTION N–N
L
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
S
0.15 (0.006) T U
A
M
MILLIMETERS
DIM MIN MAX
INCHES
–V–
MIN
MAX
0.200
0.177
0.047
0.006
0.030
N
A
B
C
4.90
4.30
–––
5.10 0.193
4.50 0.169
1.20
F
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.011
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
DETAIL E
H
SEATING
PLANE
–T–
D
G
ON Semiconductor and
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