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MC74HC4046B [ONSEMI]

Phase-Locked Loop;
MC74HC4046B
型号： MC74HC4046B
厂家： ONSEMI    ONSEMI
描述：

Phase-Locked Loop
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MC74HC4046B  
Phase-Locked Loop  
High−Performance Silicon−Gate CMOS  
The MC74HC4046B is similar in function to the MC14046 Metal  
gate CMOS device. The device inputs are compatible with standard  
CMOS outputs; with pullup resistors, they are compatible with  
LSTTL outputs.  
www.onsemi.com  
The HC4046B phase−locked loop contains three phase  
comparators, a voltage−controlled oscillator (VCO) and unity gain  
op−amp DEM  
. The comparators have two common signal inputs,  
OUT  
COMP , and SIG . Input SIG and COMP can be used directly  
IN  
IN  
IN  
IN  
SOIC−16  
D SUFFIX  
CASE 751B  
TSSOP−16  
DT SUFFIX  
CASE 948F  
coupled to large voltage signals, or indirectly coupled (with a series  
capacitor to small voltage signals). The self−bias circuit adjusts small  
voltage signals in the linear region of the amplifier. Phase comparator  
1 (an exclusive OR gate) provides a digital error signal PC1  
and  
OUT  
PIN ASSIGNMENT  
maintains 90 degrees phase shift at the center frequency between  
SIG and COMP signals (both at 50% duty cycle). Phase  
IN  
IN  
PCP  
PC1  
1
2
16  
V
CC  
out  
comparator 2 (with leading−edge sensing logic) provides digital error  
signals PC2 and PCP and maintains a 0 degree phase shift  
15 PC3  
14 SIG  
out  
out  
OUT  
OUT  
COMP  
VCO  
3
4
between SIG and COMP signals (duty cycle is immaterial). The  
in  
in  
IN  
IN  
linear VCO produces an output signal VCO  
whose frequency is  
13 PC2  
12 R2  
11 R1  
OUT  
out  
INH  
C1A  
out  
determined by the voltage of input VCO signal and the capacitor  
IN  
5
6
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain  
op−amp output DEM  
with an external resistor is used where the  
OUT  
C1B  
7
8
10 DEM  
VCO signal is needed but no loading can be tolerated. The inhibit  
out  
IN  
input, when high, disables the VCO and all op−amps to minimize  
standby power consumption.  
GND  
9
VCO  
in  
Applications include FM and FSK modulation and demodulation,  
frequency synthesis and multiplication, frequency discrimination,  
tone decoding, data synchronization and conditioning, voltage−to−  
frequency conversion and motor speed control.  
MARKING DIAGRAMS  
16  
HC4046BG  
AWLYWW  
Features  
• Output Drive Capability: 10 LSTTL Loads  
1
SOIC−16  
• Low Power Consumption Characteristic of CMOS Devices  
• Operating Speeds Similar to LSTTL  
16  
HC40  
46B  
• Wide Operating Voltage Range for VCO: 3.0 to 6.0 V  
• Low Input Current: 1.0 ꢀ A Maximum (except SIG and COMP )  
• In Compliance with the Requirements Defined by JEDEC Standard  
No. 7 A  
ALYWG  
IN  
IN  
G
1
TSSOP−16  
• Low Quiescent Current: 80 ꢀ A Maximum (VCO disabled)  
• High Noise Immunity Characteristic of CMOS Devices  
• Diode Protection on All Inputs  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
W, WW = Work Week  
G or G  
= Pb−Free Package  
• Chip Complexity: 279 FETs or 70 Equivalent Gates  
(Note: Microdot may be in either location)  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 11 of  
this data sheet.  
© Semiconductor Components Industries, LLC, 2018  
1
Publication Order Number:  
May, 2018 − Rev. 1  
MC74HC4046B/D  
MC74HC4046B  
Pin No.  
Symbol  
Name and Function  
1
2
3
PCP  
PC1  
COMP  
Phase Comparator Pulse Output  
Phase Comparator 1 Output  
Comparator Input  
OUT  
OUT  
IN  
4
VCO  
VCO Output  
OUT  
5
INH  
Inhibit Input  
6
7
8
9
C1A  
C1B  
GND  
Capacitor C1 Connection A  
Capacitor C1 Connection B  
Ground (0 V) V  
VCO Input  
SS  
VCO  
IN  
10  
11  
12  
13  
14  
15  
16  
DEM  
Demodulator Output  
OUT  
R1  
R2  
PC2  
Resistor R1 Connection  
Resistor R2 Connection  
Phase Comparator 2 Output  
Signal Input  
Phase Comparator 3 Output  
Positive Supply Voltage  
OUT  
SIG  
IN  
PC3  
OUT  
V
CC  
MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
Unit  
V
This device contains protection  
circuitry to guard against damage  
due to high static voltages or electric  
fields. However, precautions must  
be taken to avoid applications of any  
voltage higher than maximum rated  
voltages to this high−impedance cir-  
V
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)  
DC Output Voltage (Referenced to GND)  
DC Input Current, per Pin  
–0.5 to +7.0  
CC  
V
–1.5 to V + 1.5  
V
in  
CC  
V
out  
–0.5 to V + 0.5  
V
CC  
I
20  
25  
mA  
mA  
mA  
mW  
°C  
in  
cuit. For proper operation, V and  
in  
I
I
DC Output Current, per Pin  
out  
V
out  
should be constrained to the  
range GND v (V or V ) v V  
.
DC Supply Current, V and GND Pins  
50  
in  
out  
CC  
CC  
CC  
Unused inputs must always be  
tied to an appropriate logic voltage  
P
Power Dissipation in Still Air  
Storage Temperature  
SOIC Package†  
500  
D
level (e.g., either GND or V ).  
T
stg  
–65 to +150  
CC  
Unused outputs must be left open.  
T
L
Lead Temperature, 1 mm from Case for 10 Seconds  
SOIC Package†  
°C  
260  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of  
these limits are exceeded, device functionality should not be assumed, damage may occur and  
reliability may be affected.  
†Derating: SOIC Package: –7 mW/°C from 65° to 125°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
DC Supply Voltage (Referenced to GND)  
Min  
3.0  
2.0  
0
Max  
6.0  
Unit  
V
V
CC  
V
CC  
DC Supply Voltage (Referenced to GND) NON−VCO  
DC Input Voltage, Output Voltage (Referenced to GND)  
Operating Temperature, All Package Types  
6.0  
V
V , V  
in out  
V
CC  
V
T
A
–55  
+125  
°C  
ns  
t , t  
Input Rise and Fall Time  
(Pin 5)  
V
CC  
V
CC  
V
CC  
= 2.0 V  
= 4.5 V  
= 6.0 V  
0
0
0
1000  
500  
400  
r
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond  
the Recommended Operating Ranges limits may affect device reliability.  
www.onsemi.com  
2
MC74HC4046B  
[Phase Comparator Section]  
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)  
Guaranteed Limit  
V
V
CC  
≤ 85°C  
–55 to 25°C  
≤ 125°C  
Symbol  
Parameter  
Test Conditions  
= 0.1 V or V − 0.1 V  
Unit  
V
IH  
Minimum High−Level Input  
Voltage DC Coupled  
V
out  
2.0  
4.5  
6.0  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
V
out  
CC  
|I | ≤ 20 ꢀ A  
SIG , COMP  
IN  
IN  
V
Maximum Low−Level Input  
Voltage DC Coupled  
V
out  
= 0.1 V or V − 0.1 V  
2.0  
4.5  
6.0  
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
V
V
IL  
out  
CC  
|I | ≤ 20 ꢀ A  
SIG , COMP  
IN  
IN  
V
OH  
Minimum High−Level  
Output Voltage  
V
in  
= V or V  
2.0  
4.5  
6.0  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
IH  
IL  
|I | ≤ 20 ꢀ A  
out  
PCP  
, PCn  
OUT  
OUT  
V
out  
|I | ≤ 5.2 mA  
out  
= V or V  
IH  
in  
IL  
|I | ≤ 4.0 mA  
4.5  
6.0  
3.98  
5.48  
3.84  
5.34  
3.7  
5.2  
V
OL  
Maximum Low−Level  
Output Voltage Qa−Qh  
V
out  
= 0.1 V or V − 0.1 V  
2.0  
4.5  
6.0  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
V
out  
CC  
|I | ≤ 20 ꢀ A  
PCP  
, PCn  
OUT  
OUT  
V
out  
|I | ≤ 5.2 mA  
out  
= V or V  
IH IL  
in  
|I | ≤ 4.0 mA  
4.5  
6.0  
0.26  
0.3  
0.33  
0.34  
0.4  
0.4  
I
in  
Maximum Input Leakage Current  
SIG , COMP  
V
in  
= V or GND  
2.0  
3.0  
4.5  
6.0  
3.0  
8.5  
24  
4.0  
9.0  
24  
5.0  
11.0  
27.0  
108  
ꢀ
A
CC  
IN  
IN  
108  
108  
I
Maximum Three−State  
Leakage Current  
Output in High−Impedance State  
= V or V  
6.0  
0.5  
5.0  
10  
ꢀ A  
ꢀ A  
OZ  
V
in  
IH  
IL  
V
= V or GND  
out  
CC  
PC2  
OUT  
I
Maximum Quiescent Supply Current  
(per Package) (VCO disabled)  
V
out  
= V or GND  
6.0  
160  
160  
160  
CC  
in  
CC  
|I | = 0 ꢀ A  
Pins 3, 5 and 14 at V  
CC  
Pin 9 at GND; Input Leakage at  
Pins 3 and 14 to be excluded  
[Phase Comparator Section]  
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)  
L
r
f
Guaranteed Limit  
V
CC  
–55 to 25°C  
≤ 85°C  
≤ 125°C  
V
Symbol  
Parameter  
Unit  
t
t
t
t
,
Maximum Propagation Delay, SIG /COMP to PC1  
(Figure 1)  
2.0  
4.5  
6.0  
175  
35  
30  
220  
44  
37  
265  
53  
45  
ns  
PLH  
t
IN  
IN  
OUT  
PHL  
,
Maximum Propagation Delay, SIG /COMP to PCP  
2.0  
4.5  
6.0  
340  
68  
58  
425  
85  
72  
510  
102  
87  
ns  
ns  
ns  
ns  
ns  
PLH  
t
IN  
IN  
OUT  
(Figure 1)  
PHL  
,
Maximum Propagation Delay, SIG /COMP to PC3  
2.0  
4.5  
6.0  
270  
54  
46  
340  
68  
58  
405  
81  
69  
PLH  
t
IN  
IN  
OUT  
(Figure 1)  
PHL  
,
Maximum Propagation Delay, SIG /COMP Output  
2.0  
4.5  
6.0  
200  
40  
34  
250  
50  
43  
300  
60  
51  
PLZ  
IN  
IN  
t
Disable Time to PC2  
(Figures 2 and 3)  
PHZ  
OUT  
t
,
Maximum Propagation Delay, SIG /COMP Output  
2.0  
4.5  
6.0  
230  
46  
39  
290  
58  
49  
345  
69  
59  
PZH  
IN  
IN  
t
Enable Time to PC2  
(Figures 2 and 3)  
PZL  
OUT  
t
,
Maximum Output Transition Time  
(Figure 1)  
2.0  
4.5  
6.0  
75  
15  
13  
95  
19  
16  
110  
22  
19  
TLH  
t
THL  
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3
MC74HC4046B  
[VCO Section]  
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)  
Guaranteed Limit  
V
V
CC  
≤ 85°C  
–55 to 25°C  
≤ 125°C  
Symbol  
Parameter  
Test Conditions  
= 0.1 V or V − 0.1 V  
|I | ≤ 20 ꢀ A  
Unit  
V
IH  
Minimum High−Level  
Input Voltage  
INH  
V
3.0  
4.5  
6.0  
2.1  
3.15  
4.2  
2.1  
3.15  
4.2  
2.1  
3.15  
4.2  
V
out  
CC  
out  
V
Maximum Low−Level  
Input Voltage  
INH  
V
= 0.1 V or V − 0.1 V  
3.0  
4.5  
6.0  
0.90  
1.35  
1.8  
0.9  
1.35  
1.8  
0.9  
1.35  
1.8  
V
V
IL  
out  
CC  
|I | ≤ 20 ꢀ A  
out  
V
OH  
Minimum High−Level  
Output Voltage  
V
in  
= V or V  
3.0  
4.5  
6.0  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
IH  
IL  
|I | ≤ 20 ꢀ A  
out  
VCO  
OUT  
V
in  
= V or V  
IH  
IL  
|I | ≤ 4.0 mA  
|I | ≤ 5.2 mA  
out  
4.5  
6.0  
3.98  
5.48  
3.84  
5.34  
3.7  
5.2  
out  
V
OL  
Maximum Low−Level  
Output Voltage  
V
= 0.1 V or V − 0.1 V  
3.0  
4.5  
6.0  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
V
out  
CC  
|I | ≤ 20 ꢀ A  
out  
VCO  
OUT  
V
in  
= V or V  
IH IL  
|I | ≤ 4.0 mA  
|I | ≤ 5.2 mA  
out  
4.5  
6.0  
0.26  
0.3  
0.33  
0.34  
0.4  
0.4  
out  
I
in  
Maximum Input Leakage  
Current INH, VCO  
V
in  
= V or GND  
6.0  
0.1  
1.0  
1.0  
ꢀ
A
CC  
IN  
Min Max Min Max Min Max  
Operating Voltage Range at  
INH = V  
3.0  
4.5  
6.0  
0.1  
0.1  
0.1  
1.0  
2.5  
4.0  
0.1  
0.1  
0.1  
1.0  
2.5  
4.0  
0.1  
0.1  
0.1  
1.0  
2.5  
4.0  
V
IL  
V
VCO  
IN  
VCO over the range  
IN  
specified for R1; For linearity  
see Fig. 13A, Parallel value of  
R1 and R2 should be > 2.7 kꢁ  
R1  
R2  
C1  
Resistor Range  
Capacitor Range  
3.0  
4.5  
6.0  
3.0  
3.0  
3.0  
300  
300  
300  
3.0  
3.0  
3.0  
300  
300  
300  
3.0  
3.0  
3.0  
300  
300  
300  
kꢁ  
3.0  
4.5  
6.0  
3.0  
3.0  
3.0  
300  
300  
300  
3.0  
3.0  
3.0  
300  
300  
300  
3.0  
3.0  
3.0  
300  
300  
300  
3.0  
4.5  
6.0  
40  
40  
40  
No  
Limit  
pF  
[VCO Section]  
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)  
L
r
f
Guaranteed Limit  
≤ 85°C  
–55 to 25°C  
≤ 125°C  
V
CC  
Min Max Min Max Min Max  
V
Symbol  
Parameter  
Unit  
ꢂ
f
/
T
Frequency Stability with  
Temperature Changes  
(Figures 11A, B, C)  
3.0  
4.5  
6.0  
%/K  
fo  
VCO Center Frequency  
(Duty Factor = 50%, R1 = 3 kꢁ, C1 = 39 pF, R2 = infinity)  
(See Figures 12A, B, C, D for other conditions)  
3.0  
4.5  
6.0  
3
11  
13  
MHz  
%
ꢂ
f
V
C
O
V
C
O
F
r
e
q
u
e
n
c
y
L
i
n
e
a
r
i
t
y
3.0  
4.5  
6.0  
See Figures 13A, B  
Typical 50%  
∂ VCO Duty Factor at VCO  
3.0  
4.5  
6.0  
%
OUT  
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4
MC74HC4046B  
[Demodulator Section]  
DC ELECTRICAL CHARACTERISTICS  
Guaranteed Limit  
≤ 85°C  
–55 to 25°C  
≤ 125°C  
V
CC  
V
Min Max Min Max Min Max  
Symbol  
Parameter  
Resistor Range  
Test Conditions  
Unit  
RS  
At RS > 300 kꢁ the  
Leakage Current can  
3.0  
4.5  
6.0  
50  
50  
50  
300  
300  
300  
kꢁ  
Influence VDEM  
OUT  
V
OFF  
Offset Voltage  
Vi = VVCO = 1/2 V ;  
CC  
Values taken over RS  
Range.  
3.0  
4.5  
6.0  
See Figure 10  
mV  
IN  
VCO to VDEM  
IN  
OUT  
RD  
Dynamic Output  
Resistance at DEM  
VDEM  
= 1/2 V  
3.0  
4.5  
6.0  
Typical 25 ꢁ  
ꢁ
OUT  
CC  
OUT  
SWITCHING WAVEFORMS  
V
CC  
SIG  
IN  
INPUT  
V
CC  
50%  
SIG , COMP  
IN  
INPUTS  
IN  
50%  
GND  
V
CC  
GND  
COMP  
INPUT  
t
t
IN  
PHL  
PLH  
50%  
GND  
90%  
50%  
PCP , PC1  
OUT  
PC3  
OUT  
OUTPUTS  
t
PHZ  
OUT  
t
PZH  
V
OH  
90%  
PC2  
OUT  
OUTPUT  
10%  
50%  
HIGH  
IMPEDANCE  
t
t
TLH  
THL  
Figure 1.  
Figure 2.  
V
CC  
SIG  
IN  
INPUT  
50%  
TEST POINT  
GND  
OUTPUT  
V
CC  
DEVICE  
UNDER  
TEST  
COMP  
INPUT  
IN  
C *  
L
50%  
PZL  
GND  
t
PLZ  
t
HIGH  
IMPEDANCE  
50%  
PC2  
OUT  
OUTPUT  
*INCLUDES ALL PROBE AND JIG CAPACITANCE  
10%  
V
OL  
Figure 3.  
Figure 4. Test Circuit  
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5
MC74HC4046B  
DETAILED CIRCUIT DESCRIPTION  
Voltage Controlled Oscillator/Demodulator Output  
capacitor which causes the mirror to charge the opposite side  
of the capacitor. The output from the internal logic is then  
taken to VCO output (Pin 4).  
The VCO requires two or three external components to  
operate. These are R1, R2, C1. Resistor R1 and Capacitor C1  
are selected to determine the center frequency of the VCO  
(see typical performance curves Figure 12). R2 can be used  
to set the offset frequency with 0 volts at VCO input. For  
example, if R2 is decreased, the offset frequency is  
increased. If R2 is omitted the VCO range is from 0 Hz. By  
increasing the value of R2 the lock range of the PLL is  
increased and the gain (volts/Hz) is decreased. Thus, for a  
narrow lock range, large swings on the VCO input will cause  
less frequency variation.  
The input to the VCO is a very high impedance CMOS  
input and thus will not load down the loop filter, easing the  
filter design. In order to make signals at the VCO input  
accessible without degrading the loop performance, the  
VCO input voltage is buffered through a unity gain Op−amp  
to Demod Output. This Op−amp can drive loads of 50K  
ohms or more and provides no loading effects to the VCO  
input voltage (see Figure 10).  
An inhibit input is provided to allow disabling of the VCO  
and all Op−amps (see Figure 5). This is useful if the internal  
VCO is not being used. A logic high on inhibit disables the  
VCO and all Op−amps, minimizing standby power  
consumption.  
Internally, the resistors set a current in a current mirror, as  
shown in Figure 5. The mirrored current drives one side of  
the capacitor. Once the voltage across the capacitor charges  
up to V of the comparators, the oscillator logic flips the  
ref  
V
REF  
I
1
+
_
12  
CURRENT  
MIRROR  
I + I = I  
R
2
1
2
3
4
VCO  
I
2
OUT  
VCO  
9
+
_
IN  
11  
I
3
R
1
+
_
DEMOD  
10  
OUT  
C
1
(EXTERNAL)  
7
6
V
ref  
+
+
INH  
5
Figure 5. Logic Diagram for VCO  
www.onsemi.com  
6
 
MC74HC4046B  
The output of the VCO is a standard high speed CMOS  
output with an equivalent LS−TTL fan out of 10. The VCO  
output is approximately a square wave. This output can  
network that enables AC coupling of input signals. If the  
signals are not AC coupled, standard 74HC input levels are  
required. Both input structures are shown in Figure 6. The  
outputs of these comparators are essentially standard 74HC  
outputs (comparator 2 is TRI−STATEABLE). In normal  
either directly feed the COMP of the phase comparators or  
IN  
feed external prescalers (counters) to enable frequency  
synthesis.  
operation V and ground voltage levels are fed to the loop  
CC  
filter. This differs from some phase detectors which supply  
a current to the loop filter and should be considered in the  
design. (The MC14046 also provides a voltage).  
Phase Comparators  
All three phase comparators have two inputs, SIG and  
IN  
COMP . The SIG and COMP have a special DC bias  
IN  
IN  
IN  
V
CC  
V
CC  
SIG  
IN  
14  
PC2  
OUT  
13  
V
CC  
COMP  
3
IN  
PCP  
1
OUT  
PC3  
15  
OUT  
PC1  
2
OUT  
Figure 6. Logic Diagram for Phase Comparators  
Phase Comparator 1  
between COMP and SIG will increase. At an input  
IN  
IN  
This comparator is a simple XOR gate similar to the  
74HC86. Its operation is similar to an overdriven balanced  
modulator. To maximize lock range the input frequencies  
must have a 50% duty cycle. Typical input and output  
waveforms are shown in Figure 7. The output of the phase  
detector feeds the loop filter which averages the output  
voltage. The frequency range upon which the PLL will lock  
onto if initially out of lock is defined as the capture range.  
The capture range for phase detector 1 is dependent on the  
loop filter design. The capture range can be as large as the  
lock range, which is equal to the VCO frequency range.  
To see how the detector operates, refer to Figure 7. When  
two square wave signals are applied to this comparator, an  
output waveform (whose duty cycle is dependent on the  
phase difference between the two signals) results. As the  
phase difference increases, the output duty cycle increases  
and the voltage after the loop filter increases. In order to  
achieve lock when the PLL input frequency increases, the  
VCO input voltage must increase and the phase difference  
frequency equal to f , the VCO input is at 0 V. This  
requires the phase detector output to be grounded; hence, the  
two input signals must be in phase. When the input  
min  
frequency is f , the VCO input must be V and the phase  
max  
CC  
detector inputs must be 180 degrees out of phase.  
SIG  
IN  
COMP  
IN  
PC1  
OUT  
V
CC  
VCO  
IN  
GND  
Figure 7. Typical Waveforms for PLL Using  
Phase Comparator 1  
The XOR is more susceptible to locking onto harmonics  
of the SIG than the digital phase detector 2. For instance,  
IN  
www.onsemi.com  
7
 
MC74HC4046B  
a signal 2 times the VCO frequency results in the same  
will see only VCO leading edges, so the comparator output  
will stay low, forcing the VCO to f  
output duty cycle as a signal equal to the VCO frequency.  
The difference is that the output frequency of the 2f example  
is twice that of the other example. The loop filter and VCO  
range should be designed to prevent locking on to  
harmonics.  
.
min  
Phase comparator 2 is more susceptible to noise, causing  
the PLL to unlock. If a noise pulse is seen on the SIG , the  
IN  
comparator treats it as another positive edge of the SIG  
IN  
and will cause the output to go high until the VCO leading  
edge is seen, potentially for an entire SIG period. This  
would cause the VCO to speed up during that time. When  
IN  
Phase Comparator 2  
This detector is a digital memory network. It consists of  
four flip−flops and some gating logic, a three state output  
and a phase pulse output as shown in Figure 6. This  
comparator acts only on the positive edges of the input  
signals and is independent of duty cycle.  
using PC , the output of that phase detector would be  
1
disturbed for only the short duration of the noise spike and  
would cause less upset.  
Phase Comparator 3  
Phase comparator 2 operates in such a way as to force the  
PLL into lock with 0 phase difference between the VCO  
output and the signal input positive waveform edges.  
Figure 8 shows some typical loop waveforms. First assume  
This is a positive edge−triggered sequential phase  
detector using an RS flip−flop as shown in Figure 6. When  
the PLL is using this comparator, the loop is controlled by  
positive signal transitions and the duty factors of SIG and  
IN  
that SIG is leading the COMP . This means that the  
COMP  
are not important. It has some similar  
IN  
IN  
IN  
VCO’s frequency must be increased to bring its leading edge  
into proper phase alignment. Thus the phase detector 2  
output is set high. This will cause the loop filter to charge up  
the VCO input, increasing the VCO frequency. Once the  
characteristics to the edge sensitive comparator. To see how  
this detector works, assume input pulses are applied to the  
SIG and COMP ’s as shown in Figure 9. When the  
IN  
IN  
SIG leads the COMP , the flop is set. This will charge the  
IN  
IN  
leading edge of the COMP is detected, the output goes  
loop filter and cause the VCO to speed up, bringing the  
IN  
TRI−STATE holding the VCO input at the loop filter  
comparator into phase with the SIG . The phase angle  
IN  
voltage. If the VCO still lags the SIG then the phase  
detector will again charge up the VCO input for the time  
between the leading edges of both waveforms.  
between SIG and COMP varies from 0° to 360° and is  
IN  
IN  
IN  
180° at f . The voltage swing for PC is greater than for PC  
o 3 2  
but consequently has more ripple in the signal to the VCO.  
When no SIG is present the VCO will be forced to f as  
If the VCO leads the SIG then when the leading edge of  
IN  
IN  
max  
the VCO is seen; the output of the phase comparator goes  
low. This discharges the loop filter until the leading edge of  
opposed to f when PC is used.  
min 2  
The operating characteristics of all three phase  
comparators should be compared to the requirements of the  
system design and the appropriate one should be used.  
the SIG is detected at which time the output disables itself  
IN  
again. This has the effect of slowing down the VCO to again  
make the rising edges of both waveforms coincidental.  
When the PLL is out of lock, the VCO will be running  
SIG  
IN  
either slower or faster than the SIG . If it is running slower  
IN  
the phase detector will see more SIG rising edges and so  
the output of the phase comparator will be high a majority  
of the time, raising the VCO’s frequency. Conversely, if the  
COMP  
PC2  
IN  
IN  
V
CC  
OUT  
GND  
HIGH IMPEDANCE OFF-STATE  
VCO is running faster than the SIG , the output of the  
IN  
VCO  
IN  
detector will be low most of the time and the VCO’s output  
frequency will be decreased.  
PCP  
OUT  
As one can see, when the PLL is locked, the output of  
phase comparator 2 will be disabled except for minor  
Figure 8. Typical Waveforms for PLL Using  
Phase Comparator 2  
corrections at the leading edge of the waveforms. When PC  
2
is TRI−STATED, the PCP output is high. This output can be  
used to determine when the PLL is in the locked condition.  
This detector has several interesting characteristics. Over  
the entire VCO frequency range there is no phase difference  
between the COMP and the SIG . The lock range of the  
SIG  
COMP  
IN  
IN  
PC3  
OUT  
VCO  
VCC  
GND  
IN  
IN  
IN  
PLL is the same as the capture range. Minimal power was  
consumed in the loop filter since in lock the detector output  
Figure 9. Typical Waveform for PLL Using  
Phase Comparator 3  
is a high impedance. When no SIG is present, the detector  
IN  
www.onsemi.com  
8
 
MC74HC4046B  
TYPICAL CHARACTERISTICS  
20  
15  
10  
6.0  
5.0  
4.0  
3.0  
2.0  
1.0  
0
V
R
= 6.0 V,  
= 50 kꢁ  
CC  
V
= 3.0 V, C1 = 100 pF;  
CC  
S
R2 = ∞; V  
= 1/3 V  
VCOin  
CC  
V
R
= 4.5 V,  
= 50 kꢁ  
CC  
V
= 6.0 V,  
CC  
= 300 kꢁ  
S
R
S
5
0
R1 = 300 kꢁ  
R1 = 100 kꢁ  
V
R
= 4.5 V,  
= 300 kꢁ  
CC  
V
R
= 3.0 V,  
= 50 kꢁ  
CC  
S
S
−5  
R1 = 3 kꢁ  
−10  
V
R
= 3.0 V,  
= 300 kꢁ  
CC  
S
−15  
−20  
−100  
−50  
0
50  
100  
150  
0.0  
1.0  
2.0  
3.0  
4.0  
5.0  
6.0  
X AXIS LABEL (UNIT)  
T , AMBIENT TEMPERATURE (°C)  
A
Figure 10. Offset Voltage at Demodulator  
Output as a Function of VCOIN and RS  
Figure 11A. Frequency Stability vs. Ambient  
Temperature: VCC = 3.0 V  
20  
20  
15  
10  
5
V
= 4.5 V, C1 = 100 pF;  
V
CC  
= 6.0 V, C1 = 100 pF;  
CC  
15  
10  
5
R2 = ∞; V  
= 1/2 V  
R2 = ∞; V = 1/2 V  
VCOin CC  
VCOin  
CC  
R1 = 300 kꢁ  
R1 = 100 kꢁ  
R1 = 300 kꢁ  
R1 = 100 kꢁ  
0
0
−5  
−10  
−5  
−10  
R1 = 3 kꢁ  
R1 = 3 kꢁ  
−15  
−20  
−15  
−20  
−100  
−50  
0
50  
100  
150  
−100  
−50  
0
50  
100  
150  
T , AMBIENT TEMPERATURE (°C)  
A
T , AMBIENT TEMPERATURE (°C)  
A
Figure 11B. Frequency Stability vs. Ambient  
Temperature: VCC = 4.5 V  
Figure 11C. Frequency Stability vs. Ambient  
Temperature: VCC = 6.0 V  
www.onsemi.com  
9
 
MC74HC4046B  
TYPICAL CHARACTERISTICS  
22  
20  
18  
16  
14  
70  
V
= 6.0 V  
CC  
V
CC  
= 4.5 V  
60  
50  
40  
30  
20  
V
CC  
= 4.5 V  
V
CC  
= 3.0 V  
V
CC  
= 6.0 V  
12  
10  
8
V
CC  
= 3.0 V  
6
4
R1 = 3.0 kꢁ  
C1 = 39 pF  
R1 = 3.0 kꢁ  
C1 = 0.1 ꢀ F  
10  
0
2
0
0
0
1
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.0  
300  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5 4.0  
V
(V)  
V
(V)  
VCOIN  
VCOIN  
Figure 12A. VCO Frequency (fVCO) as a  
Function of the VCO Input Voltage (VVCOIN  
Figure 12B. VCO Frequency (fVCO) as a  
Function of the VCO Input Voltage (VVCOIN  
)
)
1.4  
1.2  
1.0  
0.8  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
V = 6.0 V  
CC  
V
= 6.0 V  
CC  
V
= 4.5 V  
CC  
V
= 4.5 V  
CC  
V
= 3.0 V  
CC  
V
= 3.0 V  
CC  
0.6  
0.4  
R1 = 300 kꢁ  
C1 = 0.1 ꢀ F  
0.2  
0
R1 = 300 kꢁ  
0.1  
0
C1 = 39 pF  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
V
VCOIN  
(V)  
V
VCOIN  
(V)  
Figure 12C. VCO Frequency (fVCO) as a  
Function of the VCO Input Voltage (VVCOIN  
Figure 12D. VCO Frequency (fVCO) as a  
Function of the VCO Input Voltage (VVCOIN  
)
)
10  
8
ꢂ V = 0.5 V over the V Range: for VCO Linearity  
CC  
R2 = ∞  
ꢂ V = 0.5 V  
V
= 4.5 V  
C1 = 0.1 ꢀ F  
CC  
f ′ = (f + f ) / 2  
0
1
2
Linearity = (f ′ − f ) / (f ′) x 100%  
0
0
0
f
f
2
6
V
= 6.0 V  
C1 = 0.1 ꢀ F  
CC  
0
V
CC  
= 6.0 V  
C1 = 39 pF  
f ′  
0
V
= 3.0 V  
CC  
4
V
= 3.0 V  
C1 = 39 pF  
CC  
C1 = 0.1 ꢀ F  
f
1
2
0
V
CC  
= 4.5 Vꢃ C1 = 39 pF  
−2  
10  
100  
MIN  
1/2 Vcc  
MAX  
R1 (kꢁ)  
Figure 13B. Definition of VCO Frequency  
Linearity  
Figure 13A. Frequency Linearity vs.  
R1, C1 and VCC  
www.onsemi.com  
10  
 
MC74HC4046B  
ORDERING INFORMATION  
Device  
†
Package  
Shipping  
MC74HC4046BDG  
SOIC−16  
(Pb−Free)  
48 Units / Rail  
2500 Units / Reel  
2500 Units / Reel  
96 Units / Rail  
MC74HC4046BDR2G  
NLV74HC4046ADR2G*  
MC74HC4046BDTG  
MC74HC4046BDTR2G  
SOIC−16  
(Pb−Free)  
SOIC−16  
(Pb−Free)  
TSSOP−16  
(Pb−Free)  
TSSOP−16  
(Pb−Free)  
2500 Units / Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP  
Capable.  
www.onsemi.com  
11  
MC74HC4046B  
PACKAGE DIMENSIONS  
TSSOP−16  
CASE 948F  
ISSUE B  
16X KREF  
NOTES:  
M
S
S
0.10 (0.004)  
T U  
V
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
S
0.15 (0.006) T U  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION A DOES NOT INCLUDE MOLD  
FLASH. PROTRUSIONS OR GATE BURRS.  
MOLD FLASH OR GATE BURRS SHALL NOT  
EXCEED 0.15 (0.006) PER SIDE.  
4. DIMENSION B DOES NOT INCLUDE  
INTERLEAD FLASH OR PROTRUSION.  
INTERLEAD FLASH OR PROTRUSION SHALL  
NOT EXCEED 0.25 (0.010) PER SIDE.  
5. DIMENSION K DOES NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08  
(0.003) TOTAL IN EXCESS OF THE K  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
K
K1  
16  
9
2X L/2  
J1  
SECTION N−N  
B
−U−  
L
J
PIN 1  
IDENT.  
N
8
0.25 (0.010)  
1
6. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
7. DIMENSION A AND B ARE TO BE  
DETERMINED AT DATUM PLANE −W−.  
M
S
0.15 (0.006) T U  
A
−V−  
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN MAX  
N
A
B
C
4.90  
4.30  
−−−  
5.10 0.193 0.200  
4.50 0.169 0.177  
F
1.20  
−−− 0.047  
DETAIL E  
D
F
0.05  
0.50  
0.15 0.002 0.006  
0.75 0.020 0.030  
G
H
J
J1  
K
K1  
L
0.65 BSC  
0.026 BSC  
−W−  
0.18  
0.09  
0.09  
0.19  
0.19  
0.28 0.007 0.011  
C
0.20 0.004 0.008  
0.16 0.004 0.006  
0.30 0.007 0.012  
0.25 0.007 0.010  
0.10 (0.004)  
H
DETAIL E  
SEATING  
PLANE  
−T−  
6.40 BSC  
0.252 BSC  
D
G
M
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT*  
7.06  
1
0.65  
PITCH  
01.36X6  
16X  
1.26  
DIMENSIONS: MILLIMETERS  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
www.onsemi.com  
12  
MC74HC4046B  
PACKAGE DIMENSIONS  
SOIC−16  
CASE 751B−05  
ISSUE K  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
−A−  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD  
PROTRUSION.  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.  
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION  
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D  
DIMENSION AT MAXIMUM MATERIAL CONDITION.  
16  
9
8
−B−  
P 8 PL  
M
S
B
0.25 (0.010)  
1
MILLIMETERS  
INCHES  
MIN  
0.386  
DIM MIN  
MAX  
MAX  
0.393  
0.157  
0.068  
0.019  
0.049  
A
B
C
D
F
9.80  
3.80  
1.35  
0.35  
0.40  
10.00  
G
4.00 0.150  
1.75 0.054  
0.49 0.014  
1.25 0.016  
F
R X 45  
K
_
G
J
1.27 BSC  
0.050 BSC  
0.19  
0.10  
0
0.25 0.008  
0.25 0.004  
0.009  
0.009  
7
K
M
P
R
C
7
0
_
_
_
_
−T−  
SEATING  
PLANE  
5.80  
0.25  
6.20 0.229  
0.50 0.010  
0.244  
0.019  
J
M
D
16 PL  
M
S
S
A
0.25 (0.010)  
T B  
SOLDERING FOOTPRINT*  
8X  
6.40  
16X  
1.12  
1
16  
16X  
0.58  
1.27  
PITCH  
8
9
DIMENSIONS: MILLIMETERS  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
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◊
MC74HC4046B/D  

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