MC74HC540ADT [ONSEMI]
HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, TSSOP-20;
| 型号： | MC74HC540ADT |
| 厂家： | 
ONSEMI |
| 描述： | HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, TSSOP-20 驱动器 |
| 文件： | 总8页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High–Performance Silicon–Gate CMOS
The MC74HC540A is identical in pinout to the LS540. The device
inputs are compatible with Standard CMOS outputs. External pullup
resistors make them compatible with LSTTL outputs.
The HC540A is an octal inverting buffer/line driver/line receiver
designed to be used with 3–state memory address drivers, clock
drivers, and other bus–oriented systems. This device features inputs
and outputs on opposite sides of the package and two ANDed
active–low output enables.
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MARKING
DIAGRAMS
20
PDIP–20
N SUFFIX
CASE 738
MC74HC540AN
AWLYYWW
20
1
1
The HC540A is similar in function to the HC541A, which has
non–inverting outputs.
20
SOIC WIDE–20
DW SUFFIX
CASE 751D
HC540A
AWLYYWW
20
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2 to 6V
1
1
A
= Assembly Location
WL = Wafer Lot
YY = Year
• Low Input Current: 1µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 124 FETs or 31 Equivalent Gates
LOGIC DIAGRAM
WW = Work Week
ORDERING INFORMATION
Device
Package
PDIP–20
Shipping
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
MC74HC540AN
1440 / Box
38 / Rail
MC74HC540ADW
MC74HC540ADWR2
SOIC–WIDE
SOIC–WIDE 1000 / Reel
Data
Inputs
Inverting
Outputs
1
Output OE1
OE2
PIN 20 = V
CC
PIN 10 = GND
Pinout: 20–Lead Packages (Top View)
Enables
19
V
OE2 Y1
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
CC
FUNCTION TABLE
20
19
18
Inputs
OE1 OE2
Output Y
A
L
L
L
L
L
H
X
X
H
L
H
X
X
H
Z
Z
1
2
3
4
5
6
7
9
8
10
Z = High Impedance
X = Don’t Care
OE1 A1
A2
A3
A4
A5
A6
A7
A8 GND
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 7
MC74HC540A/D
MC74HC540A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
CC
V
out
– 0.5 to V
+ 0.5
V
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
and GND Pins
CC
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature Range
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise/Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
Symbol
Parameter
Condition
–55 to 25°C ≤85°C ≤125°C
Unit
V
IH
Minimum High–Level Input
Voltage
V
= 0.1V
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
out
|I | ≤ 20µA
out
V
Maximum Low–Level Input
Voltage
V
= V – 0.1V
CC
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
IL
out
|I | ≤ 20µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
|I | ≤ 20µA
out
V
in
= V
|I | ≤ 3.6mA
out
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
IL
|I | ≤ 6.0mA
out
|I | ≤ 7.8mA
out
V
OL
Maximum Low–Level Output
Voltage
V
= V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
|I | ≤ 20µA
out
V
= V
= V
|I | ≤ 3.6mA
out
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
in
in
IH
|I | ≤ 6.0mA
out
|I | ≤ 7.8mA
out
I
in
Maximum Input Leakage Current
V
or GND
6.0
±0.1
±1.0
±1.0
µA
CC
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2
MC74HC540A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
Symbol
Parameter
Condition
–55 to 25°C
≤85°C
±5.0
≤125°C
±10.0
Unit
I
Maximum Three–State Leakage
Current
Output in High Impedance State
6.0
±0.5
µA
OZ
V
= V or V
in
IL
IH
or GND
V
out
= V
CC
or GND
I
Maximum Quiescent Supply
Current (per Package)
V
= V
6.0
4
40
160
µA
CC
in
CC
= 0µA
I
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
V
CC
V
Symbol
Parameter
–55 to 25°C
≤85°C
≤125°C
Unit
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
120
55
28
ns
PLH
PHL
20
25
t
t
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
45
25
140
60
31
165
75
38
ns
ns
ns
PLZ
PHZ
21
26
31
t
t
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
45
25
140
60
31
165
75
38
PZL
PZH
21
26
31
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
TLH
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State Output Capacitance (Output in High
Impedance State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V, V
= 0 V
EE
CC
C
Power Dissipation Capacitance (Per Buffer)*
pF
35
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
SWITCHING WAVEFORMS
V
CC
t
f
t
r
OE1 or OE2
50%
50%
V
CC
90%
50%
10%
GND
INPUT A
t
t
PZL PLZ
HIGH
IMPEDANCE
GND
OUTPUT Y
OUTPUT Y
t
t
PLH
PHL
50%
10%
90%
90%
50%
10%
V
OL
t
t
PZH PHZ
OUTPUT Y
V
OH
50%
t
t
TLH
THL
HIGH
IMPEDANCE
Figure 1.
Figure 2.
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3
MC74HC540A
TEST CIRCUITS
TEST
TEST
POINT
POINT
CONNECT TO V WHEN
CC
1kΩ
OUTPUT
OUTPUT
TESTING t
CONNECT TO GND WHEN
TESTING t and t
AND t .
PZL
PLZ
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
.
PHZ PZH
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
PIN DESCRIPTIONS
INPUTS
outputs are enabled and the device functions as an inverter.
When a hgih voltage is applied to either input, the outputs
assume the high impedance state.
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,
9) — Data input pins. Data on these pins appear in inverted
form on the corresponding Y outputs, when the outputs are
enabled.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) — Device outputs. Depending upon the state of
the output enable pins, these outputs are either inverting
outputs or high–impedance outputs.
CONTROLS
OE1, OE2 (PINS 1, 19) — Output enables (active–low).
When a low voltage is applied to both of these pins, the
LOGIC DETAIL
To 7 Other
Inverters
V
CC
One of Eight
Inverters
INPUT A
OUTPUT Y
OE1
OE2
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4
MC74HC540A
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
DIM MIN MAX
1.070 25.66 27.17
MILLIMETERS
MIN MAX
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.260
0.180
0.022
6.10
3.81
0.39
1.27 BSC
1.27
6.60
4.57
0.55
–T–
SEATING
PLANE
K
M
0.070
1.77
N
E
G
0.100 BSC
2.54 BSC
J
0.008
0.110
0.300 BSC
0.015
0.140
0.21
2.80
7.62 BSC
0
0.51
0.38
3.55
G
F
K
L
M
N
J 20 PL
D 20 PL
M
M
0.25 (0.010)
T B
0
15
0.040
15
1.01
0.020
M
M
0.25 (0.010)
T A
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
B
20X B
A
A1
B
C
D
E
e
H
h
2.35
0.10
0.35
0.23
12.65 12.95
7.40 7.60
1.27 BSC
10.05 10.55
M
S
S
T
0.25
A
B
A
0.25
0.50
0
0.75
0.90
7
L
SEATING
PLANE
18X e
A1
C
T
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5
MC74HC540A
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
CASE 948E–02
ISSUE A
20X K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
M
S
S
0.10 (0.004)
T U
V
S
Y14.5M, 1982.
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
0.15 (0.006) T U
M
A
–V–
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
C
6.40
4.30
–––
6.60 0.252
4.50 0.169
1.20
N
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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6
MC74HC540A
Notes
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7
MC74HC540A
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MC74HC540A/D
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