MC74HC595ADTEL [ONSEMI]
IC,SHIFT REGISTER,HC-CMOS,TSSOP,16PIN,PLASTIC;
| 型号： | MC74HC595ADTEL |
| 厂家： | 
ONSEMI |
| 描述： | IC,SHIFT REGISTER,HC-CMOS,TSSOP,16PIN,PLASTIC |
| 文件： | 总12页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
http://onsemi.com
High–Performance Silicon–Gate CMOS
MARKING
DIAGRAMS
16
The MC74HC595A consists of an 8–bit shift register and an 8–bit
D–type latch with three–state parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register also
provides parallel data to the 8–bit latch. The shift register and latch
have independent clock inputs. This device also has an asynchronous
reset for the shift register.
PDIP–16
N SUFFIX
CASE 648
MC74HC595AN
AWLYYWW
16
16
1
1
The HC595A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
16
SO–16
D SUFFIX
CASE 751B
HC595A
AWLYWW
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
1
1
16
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
HC
595A
ALYW
TSSOP–16
DT SUFFIX
CASE 948F
16
1
1
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
PIN ASSIGNMENT
LOGIC DIAGRAM
Q
1
2
3
4
5
6
7
8
16
15
14
V
CC
B
SERIAL
DATA
INPUT
14
15
1
Q
C
Q
A
A
Q
A
Q
B
Q
D
A
2
3
4
5
6
7
Q
C
Q
E
13 OUTPUT ENABLE
12 LATCH CLOCK
11 SHIFT CLOCK
10 RESET
PARALLEL
DATA
OUTPUTS
Q
D
Q
E
Q
F
SHIFT
Q
G
LATCH
REGISTER
Q
F
Q
H
Q
G
GND
9
SQ
H
Q
H
SHIFT
CLOCK
11
10
12
13
SERIAL
DATA
OUTPUT
9
RESET
SQ
H
ORDERING INFORMATION
LATCH
CLOCK
Device
Package
PDIP–16
SOIC–16
SOIC–16
TSSOP–16
Shipping
V
= PIN 16
CC
GND = PIN 8
OUTPUT
ENABLE
MC74HC595AN
2000 / Box
48 / Rail
MC74HC595AD
MC74HC595ADR2
MC74HC595ADT
MC74HC595ADTR2
2500 / Reel
96 / Rail
TSSOP–16 2500 / Reel
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 8
MC74HC595A/D
MC74HC595A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
– 0.5 to V
+ 0.5
+ 0.5
V
in
CC
V
out
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
DC Supply Current, V
and GND Pins
CC
range GND (V or V
)
V
CC
.
CC
in out
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
L
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
6.0
V , V
in out
DC Input Voltage, Output Voltage
(Referenced to GND)
V
CC
V
T
A
Operating Temperature, All Package Types
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
Test Conditions
25 C
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
V
= V or V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
IL
20 µA
Voltage, Q – Q
|I
|
A
H
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
IL out
out
out
V
OL
Maximum Low–Level Output
Voltage, Q – Q
V
= V or V
IH
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IL
20 µA
|I
|
A
H
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
6.0 mA
7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
IL out
out
out
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2
MC74HC595A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
85 C
125 C
Unit
V
OH
Minimum High–Level Output
V
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
in
IH
20 µA
Voltage, SQ
II
out
I
H
V
in
= V or V
IH
|I
|
I
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
2.98
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
IL out
II
out
II
I
out
V
OL
Maximum Low–Level Output
Voltage, SQ
V
= V or V
IH
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IL
20 µA
II
out
I
H
V
V
= V or V
IH
|I
|
I
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
in
in
IL out
II
out
II
I
out
I
Maximum Input Leakage
Current
= V
or GND
CC
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
I
Maximum Three–State
Leakage
Output in High–Impedance State
6.0
± 0.5
± 5.0
± 10
OZ
V
= V or V
in
IL
= V
IH
or GND
Current, Q – Q
V
out
A
H
CC
or GND
I
Maximum Quiescent Supply
Current (per Package)
V
= V
CC
= 0 µA
6.0
4.0
40
160
µA
CC
in
l
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
25 C
Unit
85 C
125 C
f
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
MHz
max
24
t
t
,
Maximum Propagation Delay, Shift Clock to SQ
(Figures 1 and 7)
2.0
3.0
4.5
6.0
140
100
28
175
125
35
210
150
42
ns
ns
ns
ns
ns
ns
PLH
H
PHL
24
30
36
t
Maximum Propagation Delay, Reset to SQ
(Figures 2 and 7)
2.0
3.0
4.5
6.0
145
100
29
180
125
36
220
150
44
PHL
H
25
31
38
t
t
,
Maximum Propagation Delay, Latch Clock to Q – Q
A
(Figures 3 and 7)
2.0
3.0
4.5
6.0
140
100
28
175
125
35
210
150
42
PLH
H
t
PHL
24
30
36
,
Maximum Propagation Delay, Output Enable to Q – Q
A
(Figures 4 and 8)
2.0
3.0
4.5
6.0
150
100
30
190
125
38
225
150
45
PLZ
H
H
t
PHZ
26
33
38
t
t
,
Maximum Propagation Delay, Output Enable to Q – Q
A
(Figures 4 and 8)
2.0
3.0
4.5
6.0
135
90
27
170
110
34
205
130
41
PZL
PZH
23
29
35
t
t
,
Maximum Output Transition Time, Q – Q
A
(Figures 3 and 7)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
31
18
15
TLH
H
THL
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3
MC74HC595A
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
85 C
125 C
Unit
t
t
,
Maximum Output Transition Time, SQ
(Figures 1 and 7)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
ns
TLH
H
THL
19
C
Maximum Input Capacitance
—
—
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State Output Capacitance (Output in
High–Impedance State), Q – Q
out
A
H
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
300
C
Power Dissipation Capacitance (Per Package)*
pF
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
TIMING REQUIREMENTS (Input t = t = 6.0 ns)
r
f
Guaranteed Limit
25 C to
V
CC
V
– 55 C
Symbol
Parameter
Unit
85 C
125 C
t
su
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
t
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
2.0
3.0
4.5
6.0
75
60
15
13
95
70
19
16
110
80
22
ns
ns
ns
ns
ns
ns
ns
su
19
t
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
h
t
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
rec
t
t
t
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
60
45
12
10
75
60
15
13
90
70
18
15
w
w
w
Minimum Pulse Width, Shift Clock
(Figure 1)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
Minimum Pulse Width, Latch Clock
(Figure 6)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
t , t
r f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
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4
MC74HC595A
FUNCTION TABLE
Inputs
Resulting Function
Serial
Input
A
Shift
Register
Contents
Latch
Register
Contents
Serial
Output
Parallel
Outputs
Shift
Clock
Latch
Clock
Output
Enable
Operation
SQ
Q
– Q
Reset
H
A
H
Reset shift register
L
X
D
X
L, H, ↓
L, H, ↓
L
L
L
U
U
L
U
Shift data into shift
register
H
↑
D
SR ;
SR
N+1
SR
SR
H
U
A
G
SR
N
Shift register remains
unchanged
H
H
X
X
L, H, ↓
L, H, ↓
L, H, ↓
L
L
U
U
U
U
U
Transfer shift register
contents to latch
register
↑
U
*
SR
LR
SR
N
N
N
Latch register remains
unchanged
X
X
X
L, H, ↓
L
U
*
U
Enable parallel outputs
X
X
X
X
X
X
X
X
L
*
*
**
**
*
*
Enabled
Z
Force outputs into high
impedance state
H
SR = shift register contents
LR = latch register contents
D = data (L, H) logic level
U = remains unchanged
↑ = Low–to–High
↓ = High–to–Low
* = depends on Reset and Shift Clock inputs
** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTS
Output Enable (Pin 13)
A (Pin 14)
Active–low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
Serial Data Input. The data on this pin is shifted into the
8–bit serial shift register.
on this input forces the outputs (Q –Q ) into the
A
H
high–impedance state. The serial output is not affected by
this control unit.
CONTROL INPUTS
Shift Clock (Pin 11)
Shift Register Clock Input. A low– to–high transition on
this input causes the data at the Serial Input pin to be shifted
into the 8–bit shift register.
OUTPUTS
Q
– Q (Pins 15, 1, 2, 3, 4, 5, 6, 7)
A
H
Noninverted, 3–state, latch outputs.
Reset (Pin 10)
SQ (Pin 9)
H
Active–low, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8–bit latch is not affected.
Noninverted, Serial Data Output. This is the output of the
eighth stage of the 8–bit shift register. This output does not
have three–state capability.
Latch Clock (Pin 12)
Storage Latch Clock Input. A low–to–high transition on
this input latches the shift register data.
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5
MC74HC595A
SWITCHING WAVEFORMS
t
w
t
t
f
r
V
CC
V
CC
SHIFT
CLOCK
90%
50%
50%
RESET
GND
GND
10%
t
t
PHL
w
1/f
max
50%
OUTPUT
t
t
PHL
PLH
SQ
H
t
rec
90%
50%
OUTPUT
V
CC
SHIFT
CLOCK
SQ
H
10%
50%
GND
t
t
THL
TLH
Figure 1.
Figure 2.
V
CC
OUTPUT
ENABLE
V
50%
CC
LATCH
CLOCK
50%
GND
GND
t
t
PLZ
PZL
HIGH
IMPEDANCE
50%
t
t
t
PLH PHL
OUTPUT Q
OUTPUT Q
10%
90%
V
OL
t
90%
50%
10%
PZH
PHZ
Q –Q
OUTPUTS
A
H
V
OH
50%
HIGH
IMPEDANCE
t
t
THL
TLH
Figure 3.
Figure 4.
V
CC
SHIFT
CLOCK
50%
VALID
V
CC
GND
SERIAL
INPUT A
50%
t
su
GND
V
CC
LATCH
CLOCK
t
su
t
h
50%
V
CC
SWITCH
CLOCK
GND
50%
t
w
GND
Figure 5.
Figure 6.
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kΩ
CONNECT TO V WHEN
CC
OUTPUT
TESTING t
AND t .
PLZ
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PHZ PZH
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 7.
Figure 8.
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6
MC74HC595A
EXPANDED LOGIC DIAGRAM
OUTPUT
ENABLE
13
12
14
LATCH
CLOCK
SERIAL
DATA
15
1
D
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Q
A
INPUT A
SR
LR
A
A
R
D
Q
B
SR
B
LR
B
R
D
2
Q
C
SR
C
LR
C
R
D
3
Q
D
SR
D
LR
D
PARALLEL
DATA
OUTPUTS
R
D
4
Q
E
SR
E
LR
E
R
D
5
Q
F
SR
F
LR
F
R
D
6
Q
G
SR
G
LR
G
R
D
7
Q
H
SHIFT
CLOCK
11
10
SR
H
LR
H
R
SERIAL
DATA
OUTPUT SQ
9
RESET
H
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MC74HC595A
TIMING DIAGRAM
SHIFT
CLOCK
SERIAL DATA
INPUT A
RESET
LATCH
CLOCK
OUTPUT
ENABLE
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
SERIAL DATA
OUTPUT SQ
H
NOTE:
implies that the output is in a high–impedance
state.
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8
MC74HC595A
PACKAGE DIMENSIONS
PDIP–16
N SUFFIX
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
C
L
0.250 0.270
0.145 0.175
0.015 0.021
0.040 0.070
0.100 BSC
6.35
3.69
0.39
1.02
6.85
4.44
0.53
S
1.77
SEATING
PLANE
–T
–
G
H
J
K
L
M
S
2.54 BSC
1.27 BSC
0.38
3.30
7.74
0.050 BSC
M
K
0.008 0.015
0.110 0.130
0.295 0.305
0.21
2.80
7.50
0°
H
J
G
D 16 PL
0°
10°
10°
M
M
0.25 (0.010)
T
A
0.020 0.040
0.51
1.01
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN MAX
DIM MIN
MAX
A
B
C
D
F
G
J
K
M
P
9.80 10.00
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
F
K
R X 45°
3.80
1.35
0.35
0.40
4.00
1.75
0.49
1.25
C
1.27 BSC
–T
0.19
0.10
0°
0.25
0.25
7°
0.008 0.009
0.004 0.009
J
SEAT–ING
M
PLANE
D 16 PL
0°
7°
5.80
0.25
6.20
0.50
0.229 0.244
0.010 0.019
M
S
S
0.25 (0.010)
T
B
A
R
http://onsemi.com
9
MC74HC595A
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T U
V
NOTES:
S
0.15 (0.006) T U
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
B
–U–
SECTION N–N
L
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
S
0.15 (0.006) T U
A
M
MILLIMETERS
DIM MIN MAX
INCHES
–V–
MIN
MAX
0.200
0.177
0.047
0.006
0.030
N
A
B
C
4.90
4.30
–––
5.10 0.193
4.50 0.169
1.20
F
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.011
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
DETAIL E
H
SEATING
PLANE
–T–
D
G
http://onsemi.com
10
MC74HC595A
Notes
http://onsemi.com
11
MC74HC595A
ON Semiconductor and
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MC74HC595A/D
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