MC74HC86AN [ONSEMI]
Quad 2-Input Exclusive OR Gate; 四2输入异或门
| 型号： | MC74HC86AN |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2-Input Exclusive OR Gate |
| 文件： | 总8页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High–Performance Silicon–Gate CMOS
The MC74HC86A is identical in pinout to the LS86. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
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MARKING
DIAGRAMS
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
14
PDIP–14
N SUFFIX
CASE 646
MC74HC86AN
AWLYYWW
1
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
14
SOIC–14
D SUFFIX
CASE 751A
HC86A
AWLYWW
• Chip Complexity: 56 FETs or 14 Equivalent Gates
LOGIC DIAGRAM
1
14
1
A1
B1
3
Y1
Y2
Y3
Y4
2
HC
86A
ALYW
TSSOP–14
DT SUFFIX
CASE 948G
4
5
A2
B2
6
1
Y = A
B
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
= AB + AB
9
A3
B3
8
10
PIN 14 = V
CC
PIN 7 = GND
12
13
FUNCTION TABLE
A4
B4
11
Inputs
Output
A
B
Y
PIN ASSIGNMENT
L
L
H
H
L
H
L
L
H
H
L
A1
B1
1
2
14
13 B4
12
V
CC
H
Y1
A2
3
4
A4
11 Y4
10 B3
B2
Y2
5
6
7
9
8
A3
Y3
ORDERING INFORMATION
GND
Device
Package
PDIP–14
Shipping
MC74HC86AN
2000 / Box
55 / Rail
MC74HC86AD
SOIC–14
SOIC–14
TSSOP–14
TSSOP–14
MC74HC86ADR2
MC74HC86ADT
MC74HC86ADTR2
2500 / Reel
96 / Rail
2500 / Reel
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 2
MC74HC86A/D
MC74HC86A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
CC
V
out
– 0.5 to V
+ 0.5
V
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
and GND Pins
CC
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
L
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
IL
20 µA
|I
|
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
IL out
out
out
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2
MC74HC86A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
85 C
125 C
Unit
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IL
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
20 µA
|I
|
out
V
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
in
in
IL out
out
out
I
Maximum Input Leakage
Current
V
= V
= V
or GND
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
CC
CC
I
Maximum Quiescent Supply
Current (per Package)
V
or GND
6.0
1.0
10
40
CC
in
I
= 0 µA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t, = t = 6 ns)
L
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
,
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
100
80
20
125
90
25
150
110
31
ns
PLH
PHL
17
21
26
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
ns
TLH
THL
19
C
Maximum Input Capacitance
—
10
10
10
pF
in
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Informationon typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Gate)*
pF
33
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
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3
MC74HC86A
t
r
t
f
V
CC
90%
50%
10%
INPUT
A OR B
TEST POINT
OUTPUT
GND
t
t
PHL
PLH
DEVICE
UNDER
TEST
C *
L
90%
50%
10%
OUTPUT Y
t
t
THL
TLH
*Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of Device)
A
B
Y
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4
MC74HC86A
PACKAGE DIMENSIONS
PDIP–14
N SUFFIX
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
DIM MIN MAX
0.770 18.16
MILLIMETERS
A
F
MIN
MAX
19.56
6.60
4.69
0.53
1.78
A
B
C
D
F
0.715
0.240
0.145
0.015
0.040
0.260
0.185
0.021
0.070
6.10
3.69
0.38
1.02
L
C
G
H
J
K
L
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
0.300 BSC
7.62 BSC
SEATING
PLANE
K
M
N
0
10
0.039
0
0.39
10
1.01
0.015
H
G
D
M
SOIC–14
D SUFFIX
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–A–
14
1
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B–
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
0.25 (0.010)
B
7
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
G
F
R X 45
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
–T–
SEATING
PLANE
J
M
G
J
K
M
P
1.27 BSC
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
K
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T B
A
7
0
7
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
R
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5
MC74HC86A
PACKAGE DIMENSIONS
TSSOP–14
DT SUFFIX
CASE 948G–01
ISSUE O
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
0.10 (0.004)
T U
V
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
–U–
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
L
N
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
K
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
–V–
A
B
C
4.90
4.30
–––
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
––– 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N–N
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
0.19
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
SEATING
PLANE
–T–
H
G
DETAIL E
D
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6
MC74HC86A
Notes
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7
MC74HC86A
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MC74HC86A/D
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