MC74HCT259ADG [ONSEMI]
8-Bit Addressable Latch 1-of-8 Decoder;
| 型号： | MC74HCT259ADG |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Addressable Latch 1-of-8 Decoder 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT259A
8-Bit Addressable Latch
1-of-8 Decoder with LSTTL
Inputs
High−Performance Silicon−Gate CMOS
http://onsemi.com
The MC74HCT259A is identical in pinout to the LS259. The device
inputs are compatible with standard CMOS and LSTTL outputs.
The HCT259A has four modes of operation as shown in the mode
selection table. In the addressable latch mode, the data on Data In is
written into the addressed latch. The addressed latch follows the data
input with all non−addressed latches remaining in their previous
states. In the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs. In the one−of−eight
decoding or demultiplexing mode, the addressed output follows the
state of Data In with all other outputs in the LOW state. In the Reset
mode all outputs are LOW and unaffected by the address and data
inputs. When operating the HCT259A as an addressable latch,
changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the
memory mode.
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
1
HCT259AG
AWLYWW
16
1
16
HCT
259A
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
16
1
1
A
= Assembly Location
= Wafer Lot
WL, L
YY, Y
= Year
Features
WW, W = Work Week
G or G
= Pb−Free Package
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• These are Pb−Free Devices
(Note: Microdot may be in either location)
PIN ASSIGNMENT
A0
A1
A2
Q0
Q1
Q2
1
2
3
4
5
6
7
8
16
V
CC
15 RESET
14 ENABLE
13 DATA IN
12 Q7
11 Q6
10 Q5
Q3
GND
9
Q4
MODE SELECTION TABLE
Enable Reset
Mode
L
H
L
H
H
L
Addressable Latch
Memory
8−Line Demultiplexer
Reset
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
April, 2011 − Rev. 3
MC74HCT259A/D
MC74HCT259A
1
2
3
4
5
6
7
9
LATCH SELECTION TABLE
A0
A1
A2
Q0
Q1
Q2
Q3
Q4
ADDRESS
INPUTS
Address Inputs
B
C
A
Latch Addressed
NONINVERTING
OUTPUTS
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
13
10
11
DATA IN
Q5
Q6
L
L
12
H
H
H
H
Q7
15
14
RESET
PIN 16 = V
CC
PIN 8 = GND
ENABLE
Figure 1. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
−0.5 to +7.0
V
V
CC
V
−0.5 to V + 0.5
in
CC
V
out
−0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
SOIC Package
TSSOP Package
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
−65 to + 150
°C
V
ESD
ESD Withstand Voltage
V
Human Body Model (Note 1)
Machine Model (Note 2)
>2000
>200
I
Latchup Performance Above V and Below GND at
100
mA
Latchup
DD
125°C (Note 3)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
1. Tested to EIA / JESD22−A114−A.
2. Tested to EIA / JESD22−A115−A.
3. Tested to EIA / JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 2)
5.5
V , V
in out
V
CC
V
T
A
−55
0
+125
500
°C
ns
t , t
r
f
http://onsemi.com
2
MC74HCT259A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
− 55 to
V
V
CC
25°C
v 85°C
v 125°C
Symbol
Parameter
Test Conditions
= 0.1 V or V − 0.1 V
Unit
V
IH
Minimum High−Level Input
V
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
out
CC
Voltage
|I | v 20 mA
out
V
IL
Maximum Low−Level Input
V
out
= 0.1 V or V − 0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
CC
Voltage
|I | v 20 mA
out
V
OH
Minimum High−Level Output
V
in
= V or V
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
IH
IL
Voltage
|I | v 20 mA
out
V
in
= V or V
|I | v 5.2 mA
out
4.5
3.98
3.84
3.70
IH
IL
V
OL
Maximum Low−Level Output
V
in
= V or V
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
IH
IL
Voltage
|I | v 20 mA
out
V
in
= V or V
|I | v 5.2 mA
out
4.5
5.5
0.26
0.1
0.33
1.0
0.40
1.0
IH
IL
I
in
Maximum Input Leakage
Current
V
in
= V or GND
mA
mA
CC
I
Maximum Quiescent Supply
Current (per Package)
V
in
= V or GND
5.5
4
40
160
CC
CC
I
= 0 mA
out
DI
CC
Additional Quiescent Supply
Current
V
V
I
= 2.4V, Any One Input
in
in
≥ −55°C
25 to 125°C
2.4
= V or GND, Other Inputs
CC
2.9
= 0mA
mA
5.5
out
http://onsemi.com
3
MC74HCT259A
AC ELECTRICAL CHARACTERISTICS (V = 4.5 to 5.5 V, C = 50 pF, Input t = t = 6 ns)
CC
L
r
f
Guaranteed Limit
−55 to
25°C
v 85°C
v 125°C
Symbol
Parameter
Unit
t
t
t
,
Maximum Propagation Delay, Data to Output
(Figures 2 and 7)
32
32
32
22
15
10
32
42
45
45
32
22
10
ns
PLH
t
PHL
,
Maximum Propagation Delay, Address Select to Output
(Figures 3 and 7)
40
40
26
19
10
ns
ns
ns
ns
pF
PLH
t
PHL
,
Maximum Propagation Delay, Enable to Output
(Figures 4 and 7)
PLH
t
PHL
t
Maximum Propagation Delay, Reset to Output
(Figures 5 and 7)
PHL
t
,
Maximum Output Transition Time, Any Output
(Figures 2 and 7)
TLH
t
THL
C
Maximum Input Capacitance
in
Typical @ 25°C, V = 5.0 V
CC
30
C
Power Dissipation Capacitance (Per Package)
pF
PD
TIMING REQUIREMENTS (V = 4.5 to 5.5 V, Input t = t = 6 ns)
CC
r
f
Guaranteed Limit
−55 to
25°C
v 85°C
19
v 125°C
Symbol
Parameter
Unit
t
su
Minimum Setup Time, Address or Data to Enable
(Figure 6)
15
22
ns
t
Minimum Hold Time, Enable to Address or Data
(Figure 6)
1
1
1
ns
ns
h
t
w
Minimum Pulse Width, Reset or Enable
(Figure 4 or 5)
15
19
22
http://onsemi.com
4
MC74HCT259A
SWITCHING WAVEFORMS
3.0V
GND
DATA IN
3.0V
GND
3.0V
GND
1.3 V
1.3 V
t
t
f
r
ADDRESS
3.0 V
DATA IN
90%
1.3 V
10%
SELECT
GND
t
t
PHL
PLH
90%
1.3 V
10%
t
t
PLH
PHL
50%
OUTPUT Q
OUTPUT Q
50%
t
t
THL
TLH
Figure 2.
Figure 3.
3.0 V
GND
3.0V
GND
3.0V
GND
DATA IN
ENABLE
DATA IN
RESET
t
t
w
w
t
w
V
CC
1.3 V
1.3 V 1.3 V
1.3 V
GND
t
t
PHL
PLH
t
PHL
50%
50%
OUTPUT Q
OUTPUT Q
Figure 4.
Figure 5.
TEST POINT
OUTPUT
DATA IN
OR
3.0V
DEVICE
UNDER
TEST
1.3 V
ADDRESS
SELECT
GND
3.0V
GND
C *
L
t
t
h(H)
h(L)
t
su
t
su
ENABLE
1.3 V
*Includes all probe and jig capacitance
Figure 6.
Figure 7. Test Circuit
http://onsemi.com
5
MC74HCT259A
13
4
5
6
DATA INPUT
D
D
D
Q0
Q1
Q2
7
9
D
D
D
D
D
Q3
Q4
Q5
Q6
Q7
A0
ADDRESS
INPUTS
3 TO 8
A1
A2
DECODER
10
11
12
14
ENABLE
15
RESET
Figure 8. Expanded Logic Diagram
ORDERING INFORMATION
†
Device
Package
Shipping
MC74HCT259ADG
SOIC−16
(Pb−Free)
48 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
MC74HCT259ADR2G
MC74HCT259ADTR2G
SOIC−16
(Pb−Free)
TSSOP−16*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T B
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
SOLDERING FOOTPRINT
14. COLLECTOR
15. EMITTER
16. COLLECTOR
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
15. EMITTER, #4
16. COLLECTOR, #4
8X
6.40
16. CATHODE
16X
1.12
STYLE 5:
STYLE 6:
STYLE 7:
PIN 1. SOURCE N‐CH
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
1
16
16X
0.58
9. SOURCE P‐CH
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
8
0.25 (0.010)
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
−V−
N
A
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
B
F
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
XXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
= Year
= Work Week
0.65
PITCH
G or G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70247A
TSSOP−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com
ONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales
相关型号：
©2020 ICPDF网 联系我们和版权申明