MC74HCT32ADR2G [ONSEMI]
Quad 2-Input OR Gate with LSTTL Compatible Inputs; 四2输入或门与LSTTL兼容输入
| 型号： | MC74HCT32ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2-Input OR Gate with LSTTL Compatible Inputs |
| 文件： | 总8页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT32A
Quad 2-Input OR Gate with
LSTTL Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT32A is identical in pinout to the LS32. The device
inputs are compatible with Standard CMOS or LSTTL outputs.
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MARKING
Features
DIAGRAMS
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 V to 6.0 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 48 FETs or 12 Equivalent Gates
• These are Pb−Free Devices
14
PDIP−14
N SUFFIX
CASE 646
MC74HCT32AN
AWLYYWWG
14
1
1
14
SOIC−14
D SUFFIX
CASE 751A
HCT32AG
AWLYWW
14
1
Pinout: 14−Lead Packages (Top View)
1
V
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
CC
14
14
HCT
TSSOP−14
DT SUFFIX
CASE 948G
14
32A
ALYWG
1
G
1
14
1
2
3
4
5
6
7
SOEIAJ−14
F SUFFIX
CASE 965
74HCT32A
ALYWG
14
A1
B1
Y1
A2
B2
Y2 GND
1
Figure 1. Pinout
1
A
= Assembly Location
1
2
A1
B1
3
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
Y1
4
5
G or G = Pb−Free Package
A2
B2
6
(Note: Microdot may be in either location)
Y2
Y = A+B
9
FUNCTION TABLE
A3
B3
8
Y3
10
Inputs
Output
Y
A
B
12
13
A4
B4
11
L
L
L
H
L
L
H
H
H
Y4
H
H
PIN 14 = V
CC
PIN 7 = GND
H
Figure 2. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
November, 2009 − Rev. 8
MC74HCT32A/D
MC74HCT32A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
–0.5 to +7.0
CC
V
–0.5 to V +0.5
V
in
CC
V
out
–0.5 to V +0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
†
†
†
P
D
Power Dissipation in Still Air,
Plastic DIP
750
500
450
SOIC Package
level (e.g., either GND or V ).
CC
TSSOP Package
Unused outputs must be left open.
T
Storage Temperature
–65 to +150
°C
°C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
L
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating
−
Plastic DIP: – 10 mW/°C from 65° to 125°C
SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
6.0
V , V
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
V
CC
V
in out
T
A
–55
+125
°C
ns
t , t
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
r
f
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2
MC74HCT32A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
−55 to 25°C ≤85°C ≤125°C
Symbol
Parameter
Condition
= 0.1V or V −0.1V
Unit
V
IH
Minimum High−Level Input Voltage
V
out
4.5 to
5.5
2.0
2.0
2.0
V
out
CC
|I | ≤ 20mA
V
Maximum Low−Level Input Voltage
V
out
= 0.1V or V − 0.1V
4.5 to
5.5
0.8
0.8
0.8
V
V
IL
out
CC
|I | ≤ 20mA
V
OH
Minimum High−Level Output
Voltage
V
in
= V or V
IL
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
IH
|I | ≤ 20mA
out
V
in
= V or V
|I | ≤ 4.0mA
out
4.5
3.98
3.84
3.70
IH
IL
V
OL
Maximum Low−Level Output
Voltage
V
out
= V or V
IL
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
|I | ≤ 20mA
V
V
V
= V or V
|I | ≤ 4.0mA
out
4.5
5.5
5.5
0.26
0.1
0.33
1.0
10
0.40
1.0
40
in
in
IH
IL
I
Maximum Input Leakage Current
= V or GND
mA
mA
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
1.0
CC
in
CC
I
= 0mA
out
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns, V = 5.0 V 10%)
L
r
f
CC
Guaranteed Limit
V
CC
V
−55 to 25°C
≤85°C
≤125°C
Unit
Symbol
Parameter
t
,
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
5.0
15
15
10
19
22
ns
PLH
t
PHL
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
5.0
19
10
22
10
ns
TLH
THL
C
Maximum Input Capacitance
pF
in
Typical @ 25°C, V = 5.0 V, V = 0 V
CC
EE
20
C
Power Dissipation Capacitance (Per Buffer)*
pF
PD
2
*Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HCT32ANG
PDIP−14
25 Units / Rail
55 Units / Rail
(Pb−Free)
MC74HCT32ADG
SOIC−14
(Pb−Free)
MC74HCT32ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
MC74HCT32ADTR2G
MC74HCT32AFELG
TSSOP−14*
SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
MC74HCT32A
t
r
t
f
V
CC
90%
INPUT
A OR B
V
10%
m
GND
(V )
I
t
t
V = GND to 3.0 V
I
PLH
PHL
V
m
= 1.3 V
90%
OUTPUT Y
V
m
10%
t
t
THL
TLH
Figure 3. Switching Waveforms
TEST
POIN
T
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 4. Test Circuit
A
B
Y
Figure 5. Expanded Logic Diagram
(1/4 of the Device)
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4
MC74HCT32A
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
N
C
G
H
J
K
L
M
N
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
−T−
SEATING
PLANE
J
_
_
K
0.015
0.039
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
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5
MC74HCT32A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
J
M
K
SEATING
1.27 BSC
D 14 PL
PLANE
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
MC74HCT32A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
MILLIMETERS
INCHES
K1
DIM MIN
MAX
MIN MAX
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
1.20
0.15 0.002 0.006
0.75 0.020 0.030
J J1
−−− 0.047
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
7
MC74HCT32A
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
14
8
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
MILLIMETERS
INCHES
MIN
---
VIEW P
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.008
0.413
0.215
A
e
A
---
0.05
0.35
0.10
9.90
5.10
2.05
c
A
1
b
c
0.20 0.002
0.50 0.014
0.20 0.004
D
E
e
10.50 0.390
5.45 0.201
A
b
1
1.27 BSC
0.050 BSC
H
M
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
0.13 (0.005)
E
L
0.10 (0.004)
L
E
M
0
10
0.90 0.028
10
_
0.035
0.056
0
_
_
_
Q
0.70
---
1
Z
1.42
---
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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For additional information, please contact your local
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MC74HCT32A/D
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