MC74HCT373ADTR2G [ONSEMI]
Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs; 八路三态同相透明锁存器与LSTTL兼容输入型号: | MC74HCT373ADTR2G |
厂家: | ONSEMI |
描述: | Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs |
文件: | 总9页 (文件大小:153K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC74HCT373A
Octal 3-State Noninverting
Transparent Latch with
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
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MARKING
The MC74HCT373A may be used as a level converter for
interfacing TTL or NMOS outputs to High−Speed CMOS inputs.
The HCT373A is identical in pinout to the LS373.
DIAGRAMS
The eight latches of the HCT373A are transparent D−type latches.
While the Latch Enable is high the Q outputs follow the Data Inputs.
When Latch Enable is taken low, data meeting the setup and hold
times becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high−impedance
state. Thus, data may be latched even when the outputs are not
enabled.
The HCT373A is identical in function to the HCT573A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT533A, which has
inverting outputs.
20
20
PDIP−20
N SUFFIX
CASE 738
MC74HCT373AN
AWLYYWWG
1
1
20
SOIC−20
DW SUFFIX
CASE 751D
HCT373A
AWLYYWWG
20
1
1
20
• Output Drive Capability: 15 LSTTL Loads
HCT
373A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
20
• TTL/NMOS−Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 mA
1
1
20
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
• Chip Complexity: 196 FETs or 49 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
SOEIAJ−20
F SUFFIX
CASE 967
20
74HCT373A
AWLYWWG
1
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
†
Device
Package
PDIP−20
SOIC−20
Shipping
18 / Box
38 / Rail
MC74HCT373ANG
MC74HCT373ADWG
MC74HCT373ADWR2G
MC74HCT373AFELG
SOIC−20 1000 / Reel
SOEIAJ−20 2000 / Reel
MC74HCT373ADTR2G TSSOP−20 2500 / Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
June, 2011 − Rev. 12
MC74HCT373A/D
MC74HCT373A
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
1
2
3
4
5
6
7
8
9
20
V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
LOGIC DIAGRAM
D0
D1
Q1
Q2
D2
D3
Q3
2
5
6
9
3
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
8
DATA
NONINVERTING
OUTPUTS
INPUTS
13
12
15
16
19
LATCH
ENABLE
14
17
18
GND 10
11
D5
D6
D7
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable
11
1
PIN 20 = V
CC
PIN 10 = GND
D
Q
LATCH ENABLE
OUTPUT ENABLE
L
L
L
H
H
L
H
L
X
X
H
L
No Change
Z
H
X
X = don’t care
Z = high impedance
Design Criteria
Internal Gate Count*
Value
49
Units
ea.
ns
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
1.5
5.0
mW
pJ
0.0075
*Equivalent to a two−input NAND gate.
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2
MC74HCT373A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
20
35
75
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
°C
°C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
L
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/°C from 65° to 125°C
SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
5.5
V , V
in out
V
CC
V
T
A
– 55 + 125
500
°C
ns
t , t
0
r
f
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
25°C
V
V
CC
v 85°C
2.0
2.0
v 125°C
Symbol
Parameter
Test Conditions
= 0.1 V or V – 0.1 V
|I | v 20 mA
Unit
V
IH
Minimum High−Level Input
V
out
4.5
5.5
2.0
2.0
2.0
2.0
V
out
CC
Voltage
V
Maximum Low−Level Input
V
= 0.1 V or V – 0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IL
out
CC
Voltage
|I | v 20 mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V or V
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
IH
IL
|I | v 20 mA
out
V
out
= V or V
in
IH IL
|I | v 6.0 mA
4.5
3.98
3.84
3.7
V
OL
Maximum Low−Level Output
Voltage
V
= V or V
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
IL
|I | v 20 mA
out
V
out
= V or V
in
IH IL
|I | v 6.0 mA
4.5
5.5
0.26
0.1
0.33
1.0
0.4
1.0
I
Maximum Input Leakage Cur-
rent
V
in
= V or GND
mA
mA
in
CC
I
Maximum Three−State
Leakage Current
Output in High−Impedance State
V = V or V
in
5.5
5.5
0.5
4.0
5.0
40
10
OZ
IL
IH
V
= V or GND
out
CC
I
Maximum Quiescent Supply
Current (per Package)
V
out
= V or GND
160
mA
CC
in
CC
I
= 0 mA
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3
MC74HCT373A
≥ −55°C
25°C to 125°C
DI
CC
Additional Quiescent Supply
Current
V
V
out
= 2.4 V, Any One Input
CC
= 0 mA
5.5
mA
in
in
= V or GND, Other Inputs
2.9
2.4
l
NOTE: 1. Total Supply Current = I + SDI
.
CC
CC
AC ELECTRICAL CHARACTERISTICS (V = 5.0 V 10%, C = 50 pF, Input t = t = 6.0 ns)
CC
L
r
f
Guaranteed Limit
– 55 to
25°C
v 85°C
v 125°C
Symbol
Parameter
Unit
t
t
t
t
,
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
28
32
30
35
12
35
42
ns
PLH
t
PHL
,
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
40
38
44
15
48
45
53
18
ns
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
PLZ
t
PHZ
,
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
PZL
t
PZH
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
TLH
t
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
out
Typical @ 25°C, V = 5.0 V
CC
65
C
Power Dissipation Capacitance (Per Latch)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
TIMING REQUIREMENTS (V = 5.0 V 10%, Input t = t = 6.0 ns)
CC
r
f
Guaranteed Limit
– 55 to
25°C
v 85°C
13
v 125°C
Symbol
Parameter
Unit
t
su
Minimum Setup Time, Input D to Latch Enable
(Figure 4)
10
15
ns
t
Minimum Hold Time, Latch Enable to Input D
(Figure 4)
10
12
13
15
15
18
ns
ns
ns
h
t
w
Minimum Pulse Width, Latch Enable
(Figure 2)
t , t
r
Maximum Input Rise and Fall Times
(Figure 1)
500
500
500
f
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4
MC74HCT373A
EXPANDED LOGIC DIAGRAM
D0
D1
D2
D3
D4
13
D5
14
D6
17
D7
18
3
4
7
8
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE
LE
LE
LE
LE
LE
LE
LE
LATCH
11
1
ENABLE
OUTPUT
ENABLE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
Q0
Q1
Q2
Q3
SWITCHING WAVEFORMS
t
r
t
f
t
w
3 V
3 V
2.7 V
1.3 V
0.3 V
LATCH ENABLE
1.3 V
1.3 V
INPUT D
GND
GND
t
t
PHL
PLH
t
t
PHL
PLH
90%
1.3 V
10%
Q
Q
1.3 V
t
t
THL
TLH
Figure 1.
Figure 2.
3 V
OUTPUT
ENABLE
1.3 V
GND
VALID
t
t
PLZ
PZL
3 V
HIGH
INPUT D
1.3 V
t
IMPEDANCE
1.3 V
GND
3 V
Q
t
h
10%
90%
su
V
OL
t
t
PHZ
PZH
LATCH ENABLE
V
OH
1.3 V
GND
1.3 V
Q
HIGH
IMPEDANCE
Figure 3.
Figure 4.
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5
MC74HCT373A
TEST CIRCUITS
TEST POINT
1 kW
TEST POINT
OUTPUT
CONNECT TO V WHEN
CC
OUTPUT
TESTING t AND t
PLZ
.
PZL
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5.
Figure 6.
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6
MC74HCT373A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
L
C
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
0.050 BSC
1.27 BSC
−T−
SEATING
PLANE
K
0.050
0.100 BSC
0.070
1.27
2.54 BSC
1.77
F
G
J
M
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
N
E
K
L
0.300 BSC
7.62 BSC
G
F
M
N
0
0.020
15
_
0.040
0
_
0.51
15
_
1.01
J 20 PL
_
D 20 PL
M
M
T B
0.25 (0.010)
M
M
T A
0.25 (0.010)
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
B
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
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7
MC74HCT373A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
K
K1
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006) T U
N
A
−V−
MILLIMETERS
INCHES
MIN
F
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
−W−
C
F
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
G
D
J
H
J1
K
DETAIL E
0.100 (0.004)
−T− SEATING
K1
L
6.40 BSC
0.252 BSC
0
PLANE
M
0
8
8
_
_
_
_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
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8
MC74HCT373A
PACKAGE DIMENSIONS
SOEIAJ−20
F SUFFIX
CASE 967−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
20
11
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN
e
A
DIM MIN
MAX
2.05
0.20
0.50
0.25
12.80
5.45
MAX
0.081
0.008
0.020
0.010
0.504
0.215
c
A
---
0.05
0.35
0.15
12.35
5.10
---
0.002
0.014
0.006
0.486
0.201
A
1
b
c
D
E
e
A
b
1
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
10
_
0.035
0.032
0
_
_
_
0.70
---
0.90
0.81
0.028
---
1
Z
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MC74HCT373A/D
相关型号:
MC74HCT373ADWR2
HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 0.300 INCH, PLASTIC, SOIC-20
MOTOROLA
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