MC74HCT4094ADG [ONSEMI]
8-Bit Shift and Store Register with LSTTL Compatible Inputs;
| 型号： | MC74HCT4094ADG |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Shift and Store Register with LSTTL Compatible Inputs |
| 文件： | 总12页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT4094A
8-Bit Shift and Store
Register with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
http://onsemi.com
The MC74HCT4094A is a high speed CMOS 8−bit serial shift and
storage register. This device consists of an 8−bit shift register and latch
with 3−state output buffers. Data is shifted on positive clock (CP)
transitions. The data in the shift register is transferred to the storage
register when the Strobe (STR) input is high. The output buffers are
enabled when the Output Enable (OE) input is set high. Two serial
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
HCT4094AG
AWLYWW
16
outputs (QS , QS ) are available for cascading multiple devices.
1
2
1
1
The MC74HCT4094A can be used to interface TTL or CMOS
outputs to high speed CMOS inputs.
16
Features
HCT
4094A
ALYWG
G
• Wide Operating Voltage Range: 4.5 to 5.5 V
TSSOP−16
DT SUFFIX
CASE 948F
16
• Low Power Dissipation: I = < 10 mA
CC
1
• In Compliance with the Requirements Defined by JEDEC
Standard No. 7A
1
• These are Pb−Free Devices
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
Typical Applications
• Serial−to−Parallel Conversion
• Remote Control Storage Register
WW, W = Work Week
G, G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
March, 2011 − Rev. 0
MC74HCT4094A/D
MC74HCT4094A
1
3
1
C2
15
EN3
CP
STR
SRG8
C1/
3
2
QS1
QS2
QP0
QP1
QP2
QP3
QP4
QP5
QP6
QP7
9
STR
D
1
2
3
4
5
6
7
8
16
V
CC
10
15 OE
14 QP
13 QP
12 QP
11 QP
10 QS
4
4
1 D
2 D
3
CP
4
5
6
7
2
1
5
6
5
QP
QP
QP
QP
0
1
2
3
6
2
D
7
7
14
13
14
13
GND
9
QS
12
11
12
11
Figure 1. Pin Assignment
OE
15
9
10
Figure 2. Logic Symbol
Figure 3. IEC Logic Symbol
2
3
D
QS2
QS1
10
8 – Stage Shift Register
8 – Bit Storage Register
3 – Stage Outputs
CP
9
1
STR
OE
15
QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7
14 13 12 11
4
5
6
7
Figure 4. Functional Diagram
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2
MC74HCT4094A
STAGE 0
STAGES 1 TO 6
STAGE 7
Q
Q
D
D
Q
D
D
QS1
QS2
CP
CP
Q
D
FF7
FF0
CP
CP
CP
latch
D
Q
D
Q
CP
CP
latch
latch
STR
OE
QP0 QP1 QP2 QP3 QP4 QP5 QP6
QP7
Figure 5. Logic Diagram
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3
MC74HCT4094A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
20
35
75
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating
−
SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
5.5
V , V
in out
DC Input Voltage, Output Voltage
(Referenced to GND)
V
CC
V
T
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
–55
0
+125
500
°C
A
t , t
r
ns
f
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4
MC74HCT4094A
FUNCTIONAL TABLE
INPUTS
PARALLEL OUTPUTS
SERIAL OUTPUTS
CP
↑
OE
STR
X
D
X
X
X
L
QP0
Z
QPn
Z
QS1
Q’6
NC
Q’6
Q’6
Q’6
NC
QS2
L
L
NC
QP7
NC
↓
X
Z
Z
↑
H
H
H
H
L
NC
L
NC
↑
H
QPn−1
QPn−1
NC
NC
↑
H
H
H
H
NC
↓
H
NC
QP7
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF−state
NC = no change
↑ = LOW−to−HIGH CP transition
↓ = HIGH−to−LOW CP transition
Q’6 = the information in the seventh register stage is transferred to the 8th register stage and QSn output at the positive clock edge
CLOCK INPUT
CP
DATA INPUT
D
STROBE INPUT
STR
OUTPUT ENABLE INPUT OE
INTERNAL Q’0
OUTPUT
FF0
QP0
Z−state
Z−state
INTERNAL Q’6
OUTPUT
FF6
QP6
SERIAL OUTPUT
SERIAL OUTPUT
QS1
QS2
Figure 6. Timing Diagram
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5
MC74HCT4094A
DC CHARACTERISTICS
Guaranteed Limits
−555C to 255C
≤ 855C
2.0
2.0
0.8
0.8
4.4
5.4
4.2
0.1
0.1
0.3
1
≤ 1255C
2.0
2.0
0.8
0.8
4.4
5.4
4.1
0.1
0.1
0.4
1
Symbol
Parameter
Test Conditions
V
CC
(V)
Unit
V
IH
Minimum High−Level Input
V
= 0.1 V or V – 0.1 V
4.5
2.0
2.0
0.8
0.8
4.4
5.4
4.25
0.1
0.1
0.25
0.1
V
OUT
OUT
CC
Voltage
⎟I
⎟ ≤ 20 mA
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
V
IL
Maximum Low−Level Input
V
= 0.1 V or V – 0.1 V
V
V
OUT
OUT
CC
Voltage
⎟I
⎟ ≤ 20 mA
V
OH
Minimum High−Level Output
V
OUT
= V or V
IH IL
⎟ ≤ 20 mA
IN
Voltage
⎟I
V
V
= V or V , ⎟I
⎟ = 6 mA
= V or V , ⎟I ⎟ ≤ 20 mA
IL OUT
IN
IH
IL OUT
V
OL
Maximum Low−Level Output
V
IN
IH
Voltage
V
V
= V or V , ⎟I ⎟ = 6 mA
IL OUT
IN
IH
I
IN
Maximum Input Leakage
Current
= V or GND
mA
mA
mA
IN
CC
I
Maximum Tri−State Output
Leakage Current
V
V
= V or GND
5.5
5.5
0.5
4.0
5
10
80
OZ
IN
OUT
CC
= V or GND
CC
I
Maximum Quiescent Supply
Current
V
IN
= V or GND
40
CC
CC
DI
CC
Additional Quiescent Supply
Current
V
V
I
= 2.4V, Any One Input
in
in
≥ −55°C
25 to 125°C
2.4
= V or GND, Other Inputs
CC
2.9
= 0mA
mA
5.5
out
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6
MC74HCT4094A
AC CHARACTERISTICS (t = t = 6 ns, C = 50 pF)
f
r
L
Guaranteed Limits
−555C to 255C
≤ 855C
≤ 1255C
Symbol
, t
Parameter
Test Conditions
V
CC
(V)
Unit
t
t
t
t
Maximum Propagation Delay
Figure 7
4.5
30
27
39
36
35
25
38
45
ns
PHL PLH
CP to QS
1
, t
Maximum Propagation Delay
CP to QS
Figure 7
Figure 7
Figure 8
Figure 9
Figure 9
4.5
4.5
4.5
4.5
4.5
34
49
45
44
31
41
59
54
53
38
ns
ns
ns
ns
ns
PHL PLH
2
, t
Maximum Propagation Delay
CP to QP
PHL PLH
n
, t
Maximum Propagation Delay
STR to QP
PHL PLH
n
t
, t
Maximum 3−State Output Enable Time
OE to QP
PZH PZL
n
t
, t
Maximum 3−State Output Enable Time
OE to QP
PHZ PLZ
n
t
, t
Maximum Output Transition Time
Figure 7
Figure 7
4.5
4.5
18
16
22
20
25
24
ns
ns
THL TLH
t
W
Minimum Clock Pulse Width
High or Low
t
Minimum Strobe Pulse Width
High
Figure 8
Figure 10
Figure 8
Figure 10
Figure 8
Figure 7
4.5
4.5
4.5
4.5
4.5
16
10
20
3
20
13
25
3
24
15
30
3
ns
ns
ns
ns
ns
W
t
t
Minimum Set−up Time
D to CP
SU
Minimum Set−up Time
CP to STR
SU
t
t
Minimum Hold Time
D to CP
h
Minimum Hold Time
CP to STR
0
0
0
h
f
Minimum Clock Pulse Frequency
Maximum Input Capacitance
4.5
−
30
10
24
10
20
10
MHz
pF
MAX
C
in
C
Maximum Output Capacitance
Power Dissipation Capacitance (Note 2)
−
15
15
15
pF
out
PD
C
−
140
140
140
pF
2. C is defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated from:
PD
I
(operating) ≈ C x V x f x N
where N
= total number of outputs switching and f = switching frequency.
CC
PD
CC
IN
SW
SW
IN
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7
MC74HCT4094A
AC WAVEFORMS
(V = 1.3 V)
M
1/f
MAX
3.0 V
3.0 V
CP Input
V
M
CP Input
V
M
t
w
t
su
t
h
t
PHL
t
PLH
QPn, QS1
Output
STR Input
50%
50%
t
W
t
THL
t
TLH
t
t
PHL
PLH
t
t
PHL
PLH
QS2 Output
QPn Output
50%
50%
t
t
THL
TLH
Figure 7. Waveforms showing the clock
Figure 8. Waveforms showing the strobe
(CP) to output (QPn, QS1, QS2) propagation
delays, the clock pulse width and the
maximum clock frequency.
(STR) to output (QPn) propagation delays,
the strobe pulse width, the clock set−up
and hold times for the strobe input.
t
f
t
r
3.0 V
3.0 V
90%
V
V
OE Input
CP Input
M
M
10%
t
su
t
su
t
t
PZL
PLZ
t
h
t
h
QPn Output:
Low − to − Off
Off − to − Low
D Input
V
M
50%
10%
90%
t
t
PZH
PHZ
QPn Output:
High − to − Off
Off − to − High
QPn, QS1, QS2
Output
50%
50%
Outputs
Enabled
Outputs
Disabled
Outputs
Enabled
The shaded areas indicate when
the input is permitted to change for
predictable output performance.
Figure 9. Waveforms showing the 3−state
Figure 10. Waveforms showing the data
enable and disable times for input OE.
set−up and hold times for the data input.
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8
MC74HCT4094A
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kW
CONNECT TO V WHEN
CC
OUTPUT
TESTING t AND t
PLZ
.
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 11. AC Characteristics Load Circuits
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HCT4094ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HCT4094ADR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74HCT4094ADT
TSSOP−16*
TSSOP−16*
96 Units / Rail
MC74HCT4094ADTR2G
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
SOLDERING FOOTPRINT
14. COLLECTOR
15. EMITTER
16. COLLECTOR
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
15. EMITTER, #4
16. COLLECTOR, #4
8X
6.40
16. CATHODE
16X
1.12
STYLE 5:
STYLE 6:
STYLE 7:
PIN 1. SOURCE N‐CH
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
1
16
16X
0.58
9. SOURCE P‐CH
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
8
0.25 (0.010)
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
−V−
N
A
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
B
F
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
XXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
= Year
= Work Week
0.65
PITCH
G or G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70247A
TSSOP−16
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ON Semiconductor and
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