MC74HCT541AFG [ONSEMI]
Octal 3−State Non−Inverting Buffer/Line Driver/ Line Receiver With LSTTL−Compatible Inputs; 八路三态非反相缓冲器/线路驱动器/线接收器输入通道兼容输入
| 型号： | MC74HCT541AFG |
| 厂家： | 
ONSEMI |
| 描述： | Octal 3−State Non−Inverting Buffer/Line Driver/ Line Receiver With LSTTL−Compatible Inputs |
| 文件： | 总8页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT541A
Octal 3−State Non−Inverting
Buffer/Line Driver/
Line Receiver With
LSTTL−Compatible Inputs
http://onsemi.com
MARKING DIAGRAMS
High−Performance Silicon−Gate CMOS
The MC74HCT541A is identical in pinout to the LS541. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to high speed CMOS inputs.
The HCT541A is an octal non−inverting buffer/line driver/line
receiver designed to be used with 3−state memory address drivers,
clock drivers, and other bus−oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active−low output enables.
PDIP−20
N SUFFIX
CASE 738
20
1
MC74HCT541AN
AWLYYWWG
1
Features
20
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS−Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1mA
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates
• Pb−Free Packages are Available*
SOIC−20WB
DW SUFFIX
CASE 751D
HCT541A
AWLYYWWG
1
1
20
1
TSSOP−20
DT SUFFIX
CASE 948E
HCT
541A
ALYWG
G
LOGIC DIAGRAM
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
1
20
1
SOEIAJ−20
F SUFFIX
CASE 967
74HCT541A
AWLYWWG
Data
Inputs
Non−Inverting
Outputs
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
1
Output OE1
OE2
PIN 20 = V
CC
PIN 10 = GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Enables
19
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 5
MC74HCT541A/D
MC74HCT541A
PINOUT: 20−LEAD PACKAGES
FUNCTION TABLE
Inputs
V
OE2 Y1
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
CC
20
19
18
Output Y
OE1 OE2
A
L
L
L
L
L
H
X
X
L
H
Z
Z
H
X
X
H
1
2
3
4
5
6
7
9
8
10
Z = High Impedance
X = Don’t Care
OE1 A1
A2
A3
A4
A5
A6
A7
A8 GND
(Top View)
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage due
to high static voltages or electric
fields. However, precautions must be
taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
– 0.5 to V + 0.5
V
out
CC
I
20
35
75
mA
mA
mA
mW
in
circuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
CC
DC Supply Current, V and GND Pins
in
out
CC
CC
Unused inputs must always be tied
to an appropriate logic voltage level
P
Power Dissipation in Still Air Plastic DIP†
750
500
D
SOIC Package†
(e.g., either GND or V ). Unused
CC
outputs must be left open.
T
Storage Temperature Range
– 65 to + 150
260
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package
L
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
DC Supply Voltage (Referenced to GND)
5.5
CC
V , V
in out
DC Input Voltage, Output Voltage
(Referenced to GND)
V
V
CC
T
Operating Temperature Range, All Package Types
Input Rise/Fall Time (Figure 1)
– 55
0
+ 125
500
_C
ns
A
t , t
r
f
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2
MC74HCT541A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
Symbol
Parameter
Condition
= 0.1V or V − 0.1V
|I | ≤ 20mA
−55 to 25°C ≤85°C ≤125°C Unit
V
Minimum High−Level Input Voltage
V
out
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
V
IH
out
CC
V
Maximum Low−Level Input Voltage
Minimum High−Level Output Voltage
V
out
= 0.1V or V − 0.1V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
IL
CC
|I | ≤ 20mA
out
V
V
in
= V or V
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
OH
IH
IL
|I | ≤ 20mA
out
V
= V or V
|I | ≤ 6.0mA
out
4.5
3.98
3.84
3.70
in
IH
IL
IL
V
Maximum Low−Level Output Voltage
V
in
= V or V
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
IH
|I | ≤ 20mA
out
V
= V or V
|I | ≤ 6.0mA
4.5
5.5
5.5
0.26
0.1
0.33
1.0
0.40
1.0
in
in
IH
IL
out
I
Maximum Input Leakage Current
Maximum 3−State Leakage Current
V
= V or GND
mA
mA
in
CC
I
I
Output in High Impedance State
= V or V
0.5
5.0
10.0
OZ
V
in
IL
IH
V
= V or GND
out
CC
Maximum Quiescent Supply Current
(per Package)
V
in
= V or GND
5.5
4
40
160
mA
CC
CC
I
= 0mA
out
DI
Additional Quiescent Supply Current
V
V
I
= 2.4V, Any One Input
≥ −55°C
25 to 125°C
2.4
CC
in
in
= V or GND, Other Inputs
CC
2.9
= 0mA
5.5
mA
out
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2. Total Supply Current = I + ΣDI
.
CC
CC
AC CHARACTERISTICS (V = 5.0V, C = 50 pF, Input t = t = 6 ns)
CC
L
r
f
Guaranteed Limit
Symbol
Parameter
−55 to 25°C
≤85°C
≤125°C Unit
t
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
23
30
30
12
28
32
38
38
18
ns
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
34
34
15
PLZ
t
PHZ
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
PZL
t
PZH
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
TLH
t
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
out
Maximum 3−State Output Capacitance (Output in High Impedance State)
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
55
f + I V . For load considerations, see Chapter 2 of the
CC CC
C
Power Dissipation Capacitance (Per Buffer)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
D
PD CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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3
MC74HCT541A
SWITCHING WAVEFORMS
t
f
t
r
3.0V
GND
90%
1.3V
INPUT A
10%
t
t
PHL
PLH
90%
1.3V
10%
OUTPUT Y
t
t
THL
TLH
Figure 1.
3.0V
OE1 or OE2
OUTPUT Y
1.3V
1.3V
GND
t
t
PLZ
PZL
HIGH
IMPEDANCE
1.3V
10%
90%
V
V
OL
t
t
PHZ
PZH
OH
OUTPUT Y
1.3V
HIGH
IMPEDANCE
Figure 2.
TEST CIRCUITS
TEST
POINT
TEST
POINT
CONNECT TO V WHEN
.
PZL
CC
TESTING t AND t
1kW
OUTPUT
OUTPUT
PLZ
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t and t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
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4
MC74HCT541A
PIN DESCRIPTIONS
INPUTS
outputs are enabled and the device functions as a
non−inverting buffer. When a high voltage is applied to
either input, the outputs assume the high impedance state.
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,
9) — Data input pins. Data on these pins appear in
non−inverted form on the corresponding Y outputs, when
the outputs are enabled.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) — Device outputs. Depending upon the state of
the output enable pins, these outputs are either
non−inverting outputs or high−impedance outputs.
CONTROLS
OE1, OE2 (PINS 1, 19) — Output enables (active−low).
When a low voltage is applied to both of these pins, the
LOGIC DETAIL
To 7 Other
Buffers
V
CC
One of Eight
Buffers
INPUT A
OUTPUT Y
OE1
OE2
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HCT541AN
MC74HCT541ANG
PDIP−20
18 Units / Rail
38 Units / Rail
PDIP−20
(Pb−Free)
MC74HCT541ADW
MC74HCT541ADWG
SOIC−20
SOIC−20
(Pb−Free)
MC74HCT541ADWR2
MC74HCT541ADWR2G
SOIC−20
1000 / Tape & Reel
SOIC−20
(Pb−Free)
MC74HCT541ADTR2
MC74HCT541ADTR2G
MC74HCT541AFG
TSSOP−20*
TSSOP−20*
2500 / Tape & Reel
40 Units / Rail
SOEIAJ−20
(Pb−Free)
MC74HCT541AFEL
MC74HCT541AFELG
SOEIAJ−20
2000 / Tape & Reel
SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*These packages are inherently Pb−Free.
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5
MC74HCT541A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
L
C
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
0.050 BSC
1.27 BSC
−T−
SEATING
PLANE
K
0.050
0.070
1.27
1.77
G
J
0.100 BSC
2.54 BSC
M
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
N
E
K
L
0.300 BSC
7.62 BSC
G
F
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
J 20 PL
_
_
_
D 20 PL
M
M
B
0.25 (0.010)
T
M
M
A
0.25 (0.010)
T
SO−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
B
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
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6
MC74HCT541A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE B
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T
U
S
U
0.15 (0.006) T
K
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
K1
20
11
2X L/2
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
0.25 (0.010)
N
S
0.15 (0.006) T
U
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
−−− 0.047
0.002
0.020
0.026 BSC
0.011
0.004
0.004
0.007
0.007
DETAIL E
C
D
0.05
0.50
0.006
0.030
−W−
F
C
G
H
0.65 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.015
0.008
0.006
0.012
0.010
J
G
D
J1
K
H
DETAIL E
0.100 (0.004)
K1
L
6.40 BSC
0.252 BSC
0
−T− SEATING
PLANE
M
0
8
8
_
_
_
_
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7
MC74HCT541A
PACKAGE DIMENSIONS
SOEIAJ−20
F SUFFIX
CASE 967−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
20
11
E
Q
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
1
H
E
E
_
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
1
10
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
A
−−−
0.05
0.35
0.15
12.35
5.10
2.05
A
1
A
b
1
0.20 0.002
0.50 0.014
0.25 0.006
12.80 0.486
5.45 0.201
0.008
0.020
0.010
0.504
0.215
b
c
M
0.10 (0.004)
0.13 (0.005)
D
E
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
0.70
−−−
10
0.90 0.028
10
0.035
0
_
_
_
_
1
Z
0.81
−−− 0.032
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC74HCT541A/D
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