MC74LCX373DTG [ONSEMI]

Low-Voltage CMOS Octal Transparent Latch; 低电压CMOS八路透明锁存器
MC74LCX373DTG
型号: MC74LCX373DTG
厂家: ONSEMI    ONSEMI
描述:

Low-Voltage CMOS Octal Transparent Latch
低电压CMOS八路透明锁存器

锁存器 逻辑集成电路 光电二极管 驱动
文件: 总9页 (文件大小:121K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
MC74LCX373  
Low-Voltage CMOS  
Octal Transparent Latch  
With 5 V-Tolerant Inputs and Outputs  
(3-State, Non-Inverting)  
http://onsemi.com  
MARKING  
DIAGRAMS  
The MC74LCX373 is a high performance, non-inverting octal  
transparent latch operating from a 2.3 to 3.6 V supply. High  
impedance TTL compatible inputs significantly reduce current  
loading to input drivers while TTL compatible outputs offer improved  
20  
switching noise performance. A V specification of 5.5 V allows  
I
MC74LCX373 inputs to be safely driven from 5 V devices.  
SOIC-20  
DW SUFFIX  
CASE 751D  
20  
LCX373  
AWLYYWWG  
The MC74LCX373 contains 8 D-type latches with 3-state outputs.  
When the Latch Enable (LE) input is HIGH, data on the Dn inputs  
enters the latches. In this condition, the latches are transparent, i.e., a  
latch output will change state each time its D input changes. When LE  
is LOW, the latches store the information that was present on the D  
inputs a setup time preceding the HIGH-to-LOW transition of LE.  
The 3-state standard outputs are controlled by the Output Enable (OE)  
input. When OE is LOW, the standard outputs are enabled. When OE  
is HIGH, the standard outputs are in the high impedance state, but this  
does not interfere with new data entering into the latches.  
1
1
20  
LCX  
373  
TSSOP-20  
DT SUFFIX  
CASE 948E  
20  
ALYWG  
1
G
1
Features  
ꢀDesigned for 2.3 to 3.6 V V Operation  
ꢀ5 V Tolerant - Interface Capability With 5 V TTL Logic  
ꢀSupports Live Insertion and Withdrawal  
CC  
20  
SOEIAJ-20  
M SUFFIX  
CASE 967  
74LCX373  
AWLYWWG  
20  
ꢀI  
Specification Guarantees High Impedance When V = 0 V  
CC  
OFF  
1
1
ꢀLVTTL Compatible  
ꢀLVCMOS Compatible  
ꢀ24 mA Balanced Output Sink and Source Capability  
A
= Assembly Location  
= Wafer Lot  
= Year  
L, WL  
Y, YY  
ꢀNear Zero Static Supply Current in all Three Logic States (10 mA)  
W, WW = Work Week  
Substantially Reduces System Power Requirements  
G or G  
= Pb-Free Package  
(Note: Microdot may be in either location)  
ꢀLatchup Performance Exceeds 500 mA  
ꢀESD Performance:  
Human Body Model >2000 V  
Machine Model >200 V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
ꢀPb-Free Packages are Available*  
*For additional information on our Pb-Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©ꢀ Semiconductor Components Industries, LLC, 2007  
November, 2007 - Rev. 8  
1
Publication Order Number:  
MC74LCX373/D  
MC74LCX373  
1
OE  
LE  
11  
2
5
nLE  
D
V
O7 D7 D6 O6 O5 D5 D4 O4 LE  
19 18 17 16 15 14 12  
CC  
O0  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
3
4
Q
Q
Q
Q
Q
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
20  
13  
11  
nLE  
D
6
nLE  
D
1
2
3
4
5
6
7
9
8
10  
7
OE O0 D0 D1 O1 O2 D2 D3 O3 GND  
Figure 1. Pinout (Top View)  
9
nLE  
D
8
12  
15  
16  
19  
nLE  
D
13  
14  
17  
18  
PIN NAMES  
PINS  
FUNCTION  
nLE  
D
Q
Q
Q
OE  
Output Enable Input  
Latch Enable Input  
Data Inputs  
LE  
D0-D7  
O0-O7  
nLE  
D
3-State Latch Outputs  
nLE  
D
Figure 2. Logic Diagram  
TRUTH TABLE  
INPUTS  
LE  
OUTPUTS  
On  
OE  
Dn  
OPERATING MODE  
L
L
H
H
H
L
H
L
Transparent (Latch Disabled); Read Latch  
Latched (Latch Enabled) Read Latch  
L
L
L
L
h
l
H
L
L
L
L
X
X
NC  
Z
Hold; Read Latch  
H
Hold; Disabled Outputs  
H
H
H
H
H
L
Z
Z
Transparent (Latch Disabled); Disabled Outputs  
Latched (Latch Enabled); Disabled Outputs  
H
H
L
L
h
l
Z
Z
H
h
L
=
=
=
=
=
=
=
High Voltage Level  
High Voltage Level One Setup Time Prior to the Latch Enable High-to-Low Transition  
Low Voltage Level  
Low Voltage Level One Setup Time Prior to the Latch Enable High-to-Low Transition  
No Change, State Prior to the Latch Enable High-to-Low Transition  
High or Low Voltage Level or Transitions are Acceptable  
High Impedance State  
l
NC  
X
Z
For I Reasons DO NOT FLOAT Inputs  
CC  
http://onsemi.com  
2
MC74LCX373  
MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
Condition  
Unit  
V
V
V
V
DC Supply Voltage  
-0.5 to +7.0  
CC  
I
DC Input Voltage  
-0.5 V +7.0  
V
I
DC Output Voltage  
-0.5 V +7.0  
Output in 3-State  
V
O
O
-0.5 V V + 0.5  
Output in HIGH or LOW State (Note 1)  
V
O
CC  
I
I
DC Input Diode Current  
DC Output Diode Current  
-50  
V < GND  
I
mA  
mA  
mA  
mA  
mA  
mA  
°C  
IK  
-50  
+50  
50  
V < GND  
O
OK  
V
O
> V  
CC  
I
I
I
DC Output Source/Sink Current  
DC Supply Current Per Supply Pin  
DC Ground Current Per Ground Pin  
Storage Temperature Range  
O
100  
100  
CC  
GND  
T
-65 to +150  
STG  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
1. I absolute maximum rating must be observed.  
O
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
V
CC  
Supply Voltage  
Operating  
Data Retention Only  
2.0  
1.5  
2.5, 3.3  
2.5, 3.3  
3.6  
3.6  
V
V
V
Input Voltage  
0
5.5  
V
V
I
Output Voltage  
(HIGH or LOW State)  
(3-State)  
0
0
V
CC  
5.5  
O
I
HIGH Level Output Current  
LOW Level Output Current  
V
V
V
= 3.0 V - 3.6 V  
= 2.7 V - 3.0 V  
= 2.3 V - 2.7 V  
- 24  
- 12  
- 8  
mA  
mA  
OH  
CC  
CC  
CC  
I
OL  
V
CC  
V
CC  
V
CC  
= 3.0 V - 3.6 V  
= 2.7 V - 3.0 V  
= 2.3 V - 2.7 V  
+ 24  
+ 12  
+ 8  
T
Operating Free-Air Temperature  
-40  
0
+85  
10  
°C  
A
Dt/DV  
Input Transition Rise or Fall Rate, V from 0.8 V to 2.0 V, V = 3.0 V  
IN CC  
ns/V  
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3
 
MC74LCX373  
DC ELECTRICAL CHARACTERISTICS  
T
A
= -40°C to +85°C  
Symbol  
Characteristic  
Condition  
Min  
1.7  
2.0  
Max  
Unit  
V
IH  
HIGH Level Input Voltage (Note 2)  
V
2.3 V V 2.7 V  
CC  
2.7 V V 3.6 V  
CC  
V
LOW Level Input Voltage (Note 2)  
HIGH Level Output Voltage  
V
V
2.3 V V 2.7 V  
CC  
0.7  
0.8  
IL  
2.7 V V 3.6 V  
CC  
V
OH  
2.3 V V 3.6 V; I = 100 mA  
V
CC  
ꢀ-ꢀ0.2  
CC  
OL  
V
= 2.3 V; I = -8 mA  
OH  
1.8  
2.2  
2.4  
2.2  
CC  
V
CC  
V
CC  
V
CC  
= 2.7 V; I = -12 mA  
OH  
= 3.0 V; I = -18 mA  
OH  
= 3.0 V; I = -24 mA  
OH  
V
LOW Level Output Voltage  
V
2.3 V V 3.6 V; I = 100 mA  
0.2  
0.6  
0.4  
0.4  
0.55  
5
OL  
CC  
OL  
V
CC  
= 2.3 V; I = 8 mA  
OL  
V
= 2.7 V; I = 12 mA  
OL  
CC  
CC  
CC  
V
V
= 3.0 V; I = 16 mA  
OL  
= 3.0 V; I = 24 mA  
OL  
I
I
Input Leakage Current  
3-State Output Current  
2.3 V V 3.6 V; 0 V V 5.5 V  
mA  
mA  
CC  
I
I
2.3 V 3.6 V; 0V V 5.5 V;  
5
OZ  
CC  
O
V = V or V  
I
IH  
IL  
I
I
Power-Off Leakage Current  
Quiescent Supply Current  
V
= 0 V; V or V = 5.5 V  
I
10  
10  
mA  
mA  
OFF  
CC  
O
2.3 V 3.6 V; V = GND or V  
CC  
CC  
CC  
I
2.3 V 3.6 V; 3.6 V or V 5.5 V  
10  
CC  
I
O
DI  
CC  
Increase in I per Input  
CC  
2.3 V 3.6 V; V = V - 0.6 V  
500  
mA  
CC  
IH  
CC  
2. These values of V are used to test DC electrical characteristics only.  
I
AC CHARACTERISTICS t = t = 2.5 ns; R = 500 W  
R
F
L
Limits  
= -40°C to +85°C  
T
A
V
CC  
= 3.3 V 0.3 V  
V
CC  
= 2.7 V  
V = 2.5 V 0.2 V  
CC  
C = 50 pF  
L
C = 30 pF  
L
C = 50 pF  
L
Min  
Max  
Min  
Max  
Min  
Max  
Symbol  
Parameter  
Waveform  
Unit  
t
t
Propagation Delay  
D to O  
1
1.5  
1.5  
8.0  
8.0  
1.5  
1.5  
9.0  
9.0  
1.5  
1.5  
9.6  
9.6  
ns  
PLH  
PHL  
n
n
t
t
Propagation Delay  
LE to O  
3
2
2
3
3
3
1.5  
1.5  
8.5  
8.5  
1.5  
1.5  
9.5  
9.5  
1.5  
1.5  
10.5  
10.5  
ns  
ns  
ns  
PLH  
PHL  
n
t
t
Output Enable Time to HIGH  
and LOW Level  
1.5  
1.5  
8.5  
8.5  
1.5  
1.5  
9.5  
9.5  
1.5  
1.5  
10.5  
10.5  
PZH  
PZL  
t
t
Output Disable Time From  
High and Low Level  
1.5  
1.5  
7.5  
7.5  
1.5  
1.5  
8.5  
8.5  
1.5  
1.5  
9.0  
9.0  
PHZ  
PLZ  
t
t
t
Setup TIme, HIGH or LOW  
D to LE  
2.5  
1.5  
3.3  
2.5  
1.5  
3.3  
4.0  
2.0  
4.0  
s
n
Hold TIme, HIGH or LOW  
D to LE  
h
n
LE Pulse Width, HIGH  
w
t
t
Output-to-Output Skew  
(Note 3)  
1.0  
1.0  
ns  
OSHL  
OSLH  
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.  
); parameter  
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t  
guaranteed by design.  
) or LOW-to-HIGH (t  
OSHL  
OSLH  
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4
 
MC74LCX373  
DYNAMIC SWITCHING CHARACTERISTICS  
T
A
= +25°C  
Symbol  
Characteristic  
Condition  
Min  
Typ  
Max  
Unit  
V
OLP  
Dynamic LOW Peak Voltage (Note 4)  
V
V
= 3.3 V, C = 50 pF, V = 3.3 V, V = 0 V  
0.8  
0.6  
V
V
CC  
L
IH  
= 2.5 V, C = 30 pF, V = 2.5 V, V = 0 V  
IL  
CC  
L
IH  
IL  
V
OLV  
Dynamic LOW Valley Voltage (Note 4)  
V
V
= 3.3 V, C = 50 pF, V = 3.3 V, V = 0 V  
-0.8  
-0.6  
V
V
CC  
L
IH  
= 2.5 V, C = 30 pF, V = 2.5 V, V = 0 V  
IL  
CC  
L
IH  
IL  
4. Number of outputs defined as “n”. Measured with “n-1” outputs switching from HIGH-to-LOW or LOW-to-HIGH. The remaining output is  
measured in the LOW state.  
CAPACITIVE CHARACTERISTICS  
Symbol  
Parameter  
Input Capacitance  
Condition  
= 3.3 V, V = 0 V or V  
Typical  
Unit  
pF  
C
C
C
V
V
7
8
IN  
CC  
I
CC  
CC  
Input/Output Capacitance  
= 3.3 V, V = 0 V or V  
I
pF  
I/O  
PD  
CC  
Power Dissipation Capacitance  
10 MHz, V = 3.3 V, V = 0 V or V  
I
25  
pF  
CC  
CC  
V
CC  
OE  
On  
Vmi  
Vmi  
V
0 V  
CC  
t
t
PHZ  
PZH  
Vmi  
Vmi  
Dn  
V
V
OH  
0 V  
HZ  
Vmo  
t
t
PHL  
PLH  
V
OH  
OL  
t
t
PLZ  
PZL  
Vmo  
Vmo  
On  
V
Vmo  
On  
V
V
LZ  
WAVEFORM 1 - PROPAGATION DELAYS  
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns  
OL  
t
R
F
W
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES  
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns  
t
R
F
W
2.7 V  
1.5 V  
Dn  
LE  
V
CC  
0 V  
Symbol 3.3 V 0.3 V  
2.7 V  
1.5 V  
1.5 V  
2.5 V 0.2 V  
t
s
t
h
Vmi  
1.5 V  
1.5 V  
V
/2  
/2  
CC  
CC  
2.7 V  
Vmo  
V
t
w
1.5 V  
1.5 V  
V
HZ  
V
LZ  
V
+ 0.3 V  
V
+ 0.3 V  
V
OL  
+ 0.15 V  
- 015 V  
OL  
OL  
0 V  
t , t  
PLH PHL  
V
OH  
- 0.3 V  
V
OH  
- 0.3 V  
V
OH  
V
OH  
OL  
On  
1.5 V  
V
WAVEFORM 3 - LE to On PROPAGATION DELAYS, LE MINIMUM  
PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES  
t
R
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns except when noted  
F W  
Figure 3. AC Waveforms  
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5
 
MC74LCX373  
V
CC  
6 V  
OPEN  
GND  
R
1
PULSE  
GENERATOR  
DUT  
R
T
C
R
L
L
TEST  
SWITCH  
t
t
, t  
PLH PHL  
Open  
, t  
PZL PLZ  
6 V at V = 3.3 0.3 V  
CC  
6 V at V = 2.5 0.2 V  
CC  
Open Collector/Drain t  
and t  
6 V  
PLH  
PHL  
t , t  
PZH PHZ  
GND  
C = 50 pF at V = 3.3 0.3 V or equivalent (includes jig and probe capacitance)  
L
CC  
C = 30 pF at V = 2.5 0.2 V or equivalent (includes jig and probe capacitance)  
L
CC  
R = R = 500 W or equivalent  
L
R = Z  
1
of pulse generator (typically 50 W)  
T
OUT  
Figure 4. Test Circuit  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC74LCX373DWR2  
MC74LCX373DWR2G  
SOIC-20  
1000 Tape & Reel  
1000 Tape & Reel  
SOIC-20  
(Pb-Free)  
MC74LCX373DT  
TSSOP-20*  
75 Units / Rail  
75 Units / Rail  
MC74LCX373DTG  
TSSOP-20*  
(Pb-Free)  
MC74LCX373DTR2  
MC74LCX373DTR2G  
TSSOP-20*  
2500 Tape & Reel  
2500 Tape & Reel  
TSSOP-20*  
(Pb-Free)  
MC74LCX373MEL  
MC74LCX373MELG  
SOEIAJ-20  
2000 Tape & Reel  
2000 Tape & Reel  
SOEIAJ-20  
(Pb-Free)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
*This package is inherently Pb-Free.  
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6
MC74LCX373  
PACKAGE DIMENSIONS  
SOIC-20  
DW SUFFIX  
CASE 751D-05  
ISSUE G  
NOTES:  
D
1. DIMENSIONS ARE IN MILLIMETERS.  
2. INTERPRET DIMENSIONS AND TOLERANCES  
PER ASME Y14.5M, 1994.  
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD  
PROTRUSION.  
20  
11  
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.  
5. DIMENSION B DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE PROTRUSION  
SHALL BE 0.13 TOTAL IN EXCESS OF B  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
E
B
1
10  
MILLIMETERS  
DIM MIN  
MAX  
2.65  
0.25  
0.49  
0.32  
12.95  
7.60  
A
A1  
B
C
D
E
2.35  
0.10  
0.35  
0.23  
12.65  
7.40  
20X B  
M
S
S
B
T
0.25  
A
e
1.27 BSC  
H
h
10.05  
0.25  
0.50  
0
10.55  
0.75  
0.90  
7
A
L
q
_
_
SEATING  
PLANE  
18X e  
A1  
C
T
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7
MC74LCX373  
PACKAGE DIMENSIONS  
TSSOP-20  
DT SUFFIX  
CASE 948E-02  
ISSUE C  
NOTES:  
ꢁꢂ1. DIMENSIONING AND TOLERANCING  
PER ANSI Y14.5M, 1982.  
ꢁꢂ2. CONTROLLING DIMENSION:  
MILLIMETER.  
20X K REF  
M
S
S
V
0.10 (0.004)  
T U  
S
0.15 (0.006) T U  
K
ꢁꢂ3. DIMENSION A DOES NOT INCLUDE  
MOLD FLASH, PROTRUSIONS OR GATE  
BURRS. MOLD FLASH OR GATE BURRS  
SHALL NOT EXCEED 0.15 (0.006) PER  
SIDE.  
ꢁꢂ4. DIMENSION B DOES NOT INCLUDE  
INTERLEAD FLASH OR PROTRUSION.  
INTERLEAD FLASH OR PROTRUSION  
SHALL NOT EXCEED 0.25 (0.010) PER  
SIDE.  
K1  
20  
11  
2X L/2  
J J1  
B
L
-U-  
PIN 1  
IDENT  
SECTION N-N  
ꢁꢂ5. DIMENSION K DOES NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08  
(0.003) TOTAL IN EXCESS OF THE K  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
1
10  
0.25 (0.010)  
N
S
0.15 (0.006) T U  
ꢁꢂ6. TERMINAL NUMBERS ARE SHOWN  
FOR REFERENCE ONLY.  
M
A
ꢁꢂ7. DIMENSION A AND B ARE TO BE  
DETERMINED AT DATUM PLANE -W-.  
-V-  
N
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN  
MAX  
0.260  
0.177  
0.047  
0.006  
0.030  
F
A
B
6.40  
4.30  
---  
6.60 0.252  
4.50 0.169  
DETAIL E  
C
1.20  
---  
D
0.05  
0.50  
0.15 0.002  
0.75 0.020  
-W-  
F
C
G
H
0.65 BSC  
0.026 BSC  
0.27  
0.09  
0.09  
0.19  
0.19  
0.37  
0.011  
0.015  
0.008  
0.006  
0.012  
0.010  
J
0.20 0.004  
0.16 0.004  
0.30 0.007  
0.25 0.007  
G
D
J1  
K
H
DETAIL E  
0.100 (0.004)  
-T- SEATING  
PLANE  
K1  
L
6.40 BSC  
0.252 BSC  
0
M
0
8
8
_
_
_
_
SOLDERING FOOTPRINT  
7.06  
1
0.65  
PITCH  
16X  
0.36  
16X  
1.26  
DIMENSIONS: MILLIMETERS  
http://onsemi.com  
8
MC74LCX373  
PACKAGE DIMENSIONS  
SOEIAJ-20  
M SUFFIX  
CASE 967-01  
ISSUE A  
NOTES:  
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.  
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE  
MOLD FLASH OR PROTRUSIONS AND ARE  
MEASURED AT THE PARTING LINE. MOLD FLASH  
OR PROTRUSIONS SHALL NOT EXCEED 0.15  
(0.006) PER SIDE.  
L
E
20  
11  
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
H
E
_
E
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT  
INCLUDE DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)  
TOTAL IN EXCESS OF THE LEAD WIDTH  
DIMENSION AT MAXIMUM MATERIAL CONDITION.  
DAMBAR CANNOT BE LOCATED ON THE LOWER  
RADIUS OR THE FOOT. MINIMUM SPACE  
BETWEEN PROTRUSIONS AND ADJACENT LEAD  
TO BE 0.46 ( 0.018).  
L
1
10  
DETAIL P  
Z
D
VIEW P  
MILLIMETERS  
INCHES  
MIN  
---  
e
A
DIM MIN  
MAX  
MAX  
0.081  
0.008  
0.020  
0.010  
0.504  
0.215  
c
A
---  
0.05  
0.35  
0.15  
12.35  
5.10  
2.05  
A
1
0.20 0.002  
0.50 0.014  
0.25 0.006  
b
c
D
E
e
12.80 0.486  
5.45 0.201  
A
b
1
1.27 BSC  
0.050 BSC  
M
0.10 (0.004)  
0.13 (0.005)  
H
7.40  
0.50  
1.10  
8.20 0.291  
0.85 0.020  
1.50 0.043  
0.323  
0.033  
0.059  
E
L
L
E
M
Q
0
10  
0.90 0.028  
10  
_
0.035  
0.032  
0
_
_
_
0.70  
---  
1
Z
0.81  
---  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800-282-9855 Toll Free  
ꢃUSA/Canada  
Europe, Middle East and Africa Technical Support:  
ꢃPhone: 421 33 790 2910  
Japan Customer Focus Center  
ꢃPhone: 81-3-5773-3850  
ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
ꢃLiterature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada  
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
MC74LCX373/D  

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