MC74LCX540MR2 [ONSEMI]
LVC/LCX/Z SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, EIAJ, PLASTIC, SOIC-20;型号: | MC74LCX540MR2 |
厂家: | ONSEMI |
描述: | LVC/LCX/Z SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, EIAJ, PLASTIC, SOIC-20 驱动 光电二极管 输出元件 逻辑集成电路 |
文件: | 总8页 (文件大小:125K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC74LCX540
Low-Voltage CMOS
Octal Buffer
Flow Through Pinout
With 5 V−Tolerant Inputs and Outputs
(3−State, Inverting)
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MARKING
The MC74LCX540 is a high performance, inverting octal buffer
operating from a 2.3 to 3.6 V supply. This device is similar in function
to the MC74LCX240, while providing flow through architecture.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
DIAGRAMS
20
20
1
LCX540
switching noise performance. A V specification of 5.5 V allows
AWLYYWWG
I
SOIC−20 WB
DW SUFFIX
CASE 751D
MC74LCX540 inputs to be safely driven from 5 V devices. The
MC74LCX540 is suitable for memory address driving and all TTL
level bus oriented transceiver applications.
1
Current drive capability is 24 mA at the outputs. The Output Enable
(OE1, OE2) inputs, when HIGH, disables the outputs by placing them
in a HIGH Z condition.
20
20
1
LCX
540
ALYW G
Features
TSSOP−20
DT SUFFIX
CASE 948E
G
• Designed for 2.3 to 3.6 V V Operation
CC
1
• 5 V Tolerant − Interface Capability With 5 V TTL Logic
• Supports Live Insertion and Withdrawal
A
L, WL
Y, YY
=
=
=
Assembly Location
Wafer Lot
• I
Specification Guarantees High Impedance When V = 0 V
CC
• LVTTL Compatible
OFF
Year
W, WW = Work Week
G or G
= Pb−Free Package
• LVCMOS Compatible
• 24 mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (10 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500 mA
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
• ESD Performance:
♦ Human Body Model >2000 V
♦ Machine Model >200 V
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
October, 2012 − Rev. 8
MC74LCX540/D
MC74LCX540
1
OE1
OE2
19
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
D0
O0
O1
O2
O3
O4
O5
O6
O7
V
OE2 O0
O1
17
O2
16
O3
15
O4
14
O5
13
O6
12
O7
11
CC
20
19
18
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
9
8
10
OE1 D0
D1
D2
D3
D4
D5
D6
D7 GND
Figure 1. Pinout: 20−Lead (Top View)
PIN NAMES
Pins
OEn
Dn
Function
Output Enable Inputs
Data Inputs
Figure 2. Logic Diagram
On
3−State Outputs
TRUTH TABLE
Inputs
Outputs
OE1
L
OE2
L
Dn
L
On
H
L
L
L
H
X
X
H
Z
H
X
X
Z
H = High Voltage Level
L = Low Voltage Level
Z = High Impedance State
X = High or Low Voltage Level and Transitions are Acceptable
For I reasons, DO NOT FLOAT Inputs
CC
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2
MC74LCX540
MAXIMUM RATINGS
Symbol
Parameter
Condition
Value
Units
V
V
CC
DC Supply Voltage
−0.5 to +7.0
V
I
DC Input Voltage
−0.5 ≤ V ≤ +7.0
V
I
V
O
DC Output Voltage
Output in 3−State
−0.5 ≤ V ≤ +7.0
V
O
(Note 1)
−0.5 ≤ V ≤ V + 0.5
V
O
CC
I
DC Input Diode Current
DC Output Diode Current
V < GND
−50
mA
mA
mA
mA
mA
mA
°C
IK
I
I
V
O
< GND
−50
+50
50
OK
V
O
> V
CC
I
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current Per Ground Pin
Storage Temperature Range
Moisture Sensitivity
O
I
100
100
CC
I
GND
T
−65 to +150
STG
MSL
Level 1
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Output in HIGH or LOW State. I absolute maximum rating must be observed.
O
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Supply Voltage
Operating
Data Retention Only
V
2.0
1.5
3.3
3.3
3.6
3.6
V
Input Voltage
0
5.5
V
V
I
V
O
Output Voltage
(HIGH or LOW State)
(3−State)
0
0
V
CC
5.5
−24
24
I
I
HIGH Level Output Current, V = 3.0 V − 3.6 V
mA
mA
mA
mA
°C
OH
CC
I
OL
LOW Level Output Current, V = 3.0 V − 3.6 V
CC
HIGH Level Output Current, V = 2.7 V − 3.0 V
−12
12
OH
CC
I
OL
LOW Level Output Current, V = 2.7 V − 3.0 V
CC
T
A
Operating Free−Air Temperature
−40
+85
10
Dt/DV
Input Transition Rise or Fall Rate, V from 0.8 V to 2.0 V, V = 3.0 V
0
ns/V
IN
CC
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LCX540DWR2G
SOIC−20 WB
(Pb−Free)
1000 Tape & Reel
75 Units / Rail
MC74LCX540DTG
TSSOP−20
(Pb−Free)
MC74LCX540DTR2G
TSSOP−20
(Pb−Free)
2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
MC74LCX540
DC ELECTRICAL CHARACTERISTICS
T
A
= −40°C to +85°C
Symbol
Characteristic
HIGH Level Input Voltage (Note 2)
LOW Level Input Voltage (Note 2)
HIGH Level Output Voltage
Condition
2.7 V ≤ V ≤ 3.6 V
Min
2.0
Max
Units
V
IH
V
V
V
CC
V
IL
2.7 V ≤ V ≤ 3.6 V
0.8
CC
V
OH
2.7 V ≤ V ≤ 3.6 V; I = −100 mA
V
− 0.2
CC
OH
CC
V
CC
V
CC
V
CC
= 2.7 V; I = −12 mA
2.2
OH
= 3.0 V; I = −18 mA
2.4
2.2
OH
= 3.0 V; I = −24 mA
OH
V
LOW Level Output Voltage
2.7 V ≤ V ≤ 3.6 V; I = 100 mA
0.2
0.4
V
OL
OZ
CC
OL
V
CC
V
CC
V
CC
= 2.7 V; I = 12 mA
OL
= 3.0 V; I = 16 mA
0.4
OL
= 3.0 V; I = 24 mA
0.55
OL
I
3−State Output Current
V
CC
= 3.6 V, V = V or V ,
OUT
5
mA
IN
IH
IL
V
= 0 to 5.5 V
I
Power Off Leakage Current
Input Leakage Current
V
= 0, V = 5.5 V or V = 5.5 V
OUT
10
5
mA
mA
mA
mA
OFF
CC
IN
I
IN
V
V
= 3.6 V, V = 5.5 V or GND
IN
CC
CC
I
Quiescent Supply Current
= 3.6 V, V = 5.5 V or GND
10
500
CC
IN
DI
Increase in I per Input
2.3 ≤ V ≤ 3.6 V; V = V − 0.6 V
CC IH CC
CC
CC
2. These values of V are used to test DC electrical characteristics only.
I
AC CHARACTERISTICS (t = t = 2.5 ns; C = 50 pF; R = 500 W)
R
F
L
L
Limits
T
A
= −40°C to +85°C
V
= 3.0 V to 3.6 V
Max
V
CC
= 2.7 V
CC
Symbol
Parameter
Waveform
Min
Max
Units
t
t
Propagation Delay
Input to Output
1
1.5
1.5
6.5
6.5
7.5
7.5
ns
PLH
PHL
t
Output Enable Time to
High and Low Level
2
2
1.5
1.5
8.5
8.5
9.5
9.5
ns
ns
ns
PZH
PZL
t
t
Output Disable Time From
High and Low Level
1.5
1.5
7.5
7.5
8.5
8.5
PHZ
t
PLZ
t
t
Output−to−Output Skew (Note 3)
1.0
1.0
OSHL
OSLH
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
) or LOW−to−HIGH (t
); parameter
OSHL
OSLH
guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
T
A
= +25°C
Typ
Symbol
Characteristic
Condition
= 3.3 V, C = 50 pF, V = 3.3 V, V = 0 V
Min
Max
Units
V
V
Dynamic LOW Peak Voltage (Note 4)
Dynamic LOW Valley Voltage (Note 4)
V
V
0.8
V
V
OLP
CC
L
IH
IL
= 3.3 V, C = 50 pF, V = 3.3 V, V = 0 V
0.8
OLV
CC
L
IH
IL
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Input Capacitance
Condition
= 3.3 V, V = 0 V or V
Typical
Units
pF
C
V
V
7
8
IN
CC
I
CC
CC
C
Output Capacitance
= 3.3 V, V = 0 V or V
pF
OUT
CC
I
C
Power Dissipation Capacitance
10 MHz, V = 3.3V, V = 0 V or V
CC
25
pF
PD
CC
I
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4
MC74LCX540
2.7 V
0 V
1.5 V
1.5 V
Dn
t
t
PLH
PHL
V
OH
OL
1.5 V
1.5 V
On
V
WAVEFORM 1 - PROPAGATION DELAYS
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns
t
R
F
W
2.7 V
0 V
1.5 V
OEn
t
t
PHZ
PZH
V
V
CC
- 0.3 V
OH
1.5 V
On
≈ 0 V
t
t
PLZ
PZL
≈ 3.0 V
1.5 V
On
V + 0.3 V
OL
GND
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
t
R
= t = 2.5 ns, 10% to 90%; f = 1 MHz; t = 500 ns
F W
Figure 3. AC Waveforms
V
CC
6 V
OPEN
GND
R
1
PULSE
GENERATOR
DUT
R
T
C
R
L
L
Test
, t
Switch
Open
6 V
t
PLH PHL
t
, t
PZL PLZ
Open Collector/Drain t
and t
6 V
PLH
PZH PHZ
PHL
t
, t
GND
C = 50 pF or equivalent (Includes jig and probe capacitance)
L
R = R = 500 W or equivalent
L
1
OUT
R = Z
T
of pulse generator (typically 50 W)
Figure 4. Test Circuit
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5
MC74LCX540
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE G
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
MILLIMETERS
20X B
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
T
0.25
A
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
L
18X e
A1
C
q
T
_
_
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6
MC74LCX540
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
K
K1
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T
U
S
T U
0.15 (0.006)
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006)
T U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
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7
MC74LCX540
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Order Literature: http://www.onsemi.com/orderlit
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For additional information, please contact your local
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MC74LCX540/D
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