MC74LVX541DTR2G [ONSEMI]
Octal Bus Buffer; 八路总线缓冲器
| 型号： | MC74LVX541DTR2G |
| 厂家： | 
ONSEMI |
| 描述： | Octal Bus Buffer |
| 文件： | 总7页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVX541
Octal Bus Buffer
The MC74LVX541 is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74LVX541 is a noninverting type. When either OE1 or OE2
are high, the terminal outputs are in the high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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MARKING
DIAGRAMS
20
Features
SOIC−20
DW SUFFIX
CASE 751D
LVX541
AWLYYWWG
20
• High Speed: t = 5.0 ns (Typ) at V = 3.3 V
PD
CC
1
• Low Power Dissipation: I = 4 ꢀ A (Max) at T = 25°C
CC
A
1
• High Noise Immunity: V
= V
= 28% V
NIL CC
NIH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
20
LVX
541
• Designed for 2 V to 3.6 V Operating Range
TSSOP−20
DT SUFFIX
CASE 948E
20
• Low Noise: V
= 1.2 V (Max)
OLP
ALYWG
1
G
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
1
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates
• ESD Performance:
20
Human Body Model > 2000 V;
Machine Model > 200 V
SOEIAJ−20
M SUFFIX
CASE 967
LVX541
AWLYWWG
20
• These Devices are Pb−Free and are RoHS Compliant
1
1
LVX541
A
WL, L
Y
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
WW, W
G or G
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2011 − Rev. 4
MC74LVX541/D
MC74LVX541
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
DATA
INPUTS
NONINVERTING
OUTPUTS
A8
1
OE1
OUTPUT
ENABLES
19
OE2
Figure 1. LOGIC DIAGRAM
&
1
QE1
EN
OE1
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
20
V
CC
19
QE2
19 OE2
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 Y8
18
17
16
15
14
13
12
11
2
3
4
5
6
7
8
9
A1
A2
A3
A4
1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A5
A6
A7
A8
GND 10
Figure 2. PIN ASSIGNMENT
Figure 3. IEC LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Output Y
OE1 OE2
A
L
L
L
L
L
H
X
X
L
H
Z
Z
H
X
X
H
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2
MC74LVX541
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
– 0.5 to V + 0.5
V
out
IK
CC
I
− 20
20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
Output Diode Current
OK
V
out
should be constrained to the
range GND v (V or V ) v V
.
I
DC Output Current, per Pin
25
in
out
CC
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
DC Supply Current, V and GND Pins
50
CC
level (e.g., either GND or V ).
P
D
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
3.6
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
in
5.5
V
V
out
0
V
CC
V
T
Operating Temperature, All Package Types
Input Rise and Fall Time = 3.3V 0.3V
−40
0
+ 85
100
°C
ns/V
A
t , t
r
V
CC
f
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
CC
Min
Typ
Max
Min
Max
V
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level Input Voltage
2.0
3.0
3.6
1.50
2.0
2.4
1.50
2.0
2.4
V
V
Maximum Low−Level Input Voltage
2.0
3.0
3.6
0.50
0.80
0.80
0.50
0.80
0.80
V
V
V
IL
V
OH
Minimum High−Level Output Voltage
= V or V
I
I
I
= − 50 ꢀ A
= − 50 ꢀ A
= − 4 mA
2.0
3.0
3.0
1.9
2.9
2.58
2.0
3.0
1.9
2.9
2.48
OH
OH
OH
V
in
IH
IL
V
OL
Maximum Low−Level Output Voltage
= V or V
I
OL
I
OL
I
OL
= 50 ꢀ A
= 50 ꢀA
= 4 mA
2.0
3.0
3.0
0.0
0.0
0.1
0.1
0.36
0.1
0.1
0.44
V
in
IH
IL
I
Maximum Input Leakage Current
V
= 5.5 V or GND
0 to
3.6
0.1
1.0
2.5
ꢀ A
ꢀ A
ꢀ A
in
in
I
Maximum Three−State Leakage
Current
V
in
= V or V
IH
3.6
0.2
5
OZ
IL
V
= V or GND
out CC
I
Maximum Quiescent Supply Current
V
in
= V or GND
3.6
4.0
40.0
CC
CC
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3
MC74LVX541
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
A
= 25°C
T = − 40 to 85°C
A
Min
Typ
Max
Min
1.0
Max
Symbol
Parameter
Test Conditions
Unit
t
t
t
,
Maximum Propagation Delay,
A to Y
ns
V
V
V
= 2.7 V
C = 15 pF
L
5.0
7.5
7.0
10.5
8.5
12.0
PLH
t
CC
CC
CC
C = 50 pF
L
1.0
PHL
= 3.3 0.3 V
= 2.7 V
C = 15 pF
C = 50 pF
L
3.5
5.0
5.0
7.0
1.0
1.0
6.0
8.0
L
,
Output Enable TIme,
OE to Y
ns
ns
C = 15 pF
L
6.8
9.3
10.5
14.0
1.0
1.0
12.5
16.0
PZL
t
R = 1 kꢁ
C = 50 pF
L
PZH
L
V
CC
= 3.3 0.3 V
C = 15 pF
L
4.7
6.2
7.2
9.2
1.0
1.0
8.5
10.5
R = 1 kꢁ
C = 50 pF
L
L
,
Output Disable Time,
OE to Y
V
CC
= 2.7 V
C = 50 pF
L
11.2 15.4
1.0
17.5
10.0
1.5
PLZ
t
R = 1 kꢁ
PHZ
L
V
CC
= 3.3 0.3 V
C = 50 pF
L
6.0
8.8
1.5
1.0
10
1.0
R = 1 kꢁ
L
t
,
Output to Output Skew
V
CC
= 2.7 V
C = 50 pF
L
ns
ns
OSLH
t
(Note 1)
OSHL
V
CC
= 3.3 0.3 V
C = 50 pF
L
1.0
(Note 1)
C
Maximum Input Capacitance
4.0
6.0
10
pF
pF
in
C
Maximum Three−State Output
Capacitance
out
(Output in High Impedance
State)
Typical @ 25°C, V = 5.0V
CC
18
C
Power Dissipation Capacitance (Note 2)
= |t
pF
PD
1. Parameter guaranteed by design. t
− t
|, t
= |t
− t
PHLn
|.
OSLH
PLHm
PLHn OSHL
PHLm
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
dynamic power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I /8 (per bit). C is used to determine the no−load
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 3.3 V)
r
f
L
CC
T
A
= 25°C
Typ
0.5
Max
Symbol
Parameter
Unit
V
V
Quiet Output Maximum Dynamic V
0.8
−0.8
2.0
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
−0.5
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
0.8
V
SWITCHING WAVEFORMS
V
CC
OE1 or OE2
V
CC
50%
50%
GND
A
50%
t
t
PLZ
PZL
HIGH
IMPEDANCE
GND
t
t
PHL
PLH
50% V
t
Y
Y
CC
V
V
+0.3 V
-0.3 V
OL
t
50% V
PZH
PHZ
CC
Y
OH
50% V
CC
HIGH
IMPEDANCE
Figure 4.
Figure 5.
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4
MC74LVX541
TEST CIRCUITS
TEST
POINT
TEST
POINT
CONNECT TO V WHEN
.
CC
TESTING t AND t
1 kꢁ
OUTPUT
OUTPUT
PLZ
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6.
Figure 7.
INPUT
Figure 8. INPUT EQUIVALENT CIRCUIT
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LVX541DWG
SOIC−20
(Pb−Free)
38 Units / Rail
2500 Tape & Reel
40 Units / Rail
MC74LVX541DTR2G
MC74LVX541MG
TSSOP−20*
(Pb−Free)
SOEIAJ−20
(Pb−Free)
MC74LVX541MELG
SOEIAJ−20
(Pb−Free)
2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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5
MC74LVX541
PACKAGE DIMENSIONS
SOIC−20
CASE 751D−05
ISSUE G
NOTES:
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
B
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
SOEIAJ−20
CASE 967−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
20
11
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN
e
A
DIM MIN
MAX
2.05
0.20
0.50
0.25
12.80
5.45
MAX
0.081
0.008
0.020
0.010
0.504
0.215
c
A
---
0.05
0.35
0.15
12.35
5.10
---
0.002
0.014
0.006
0.486
0.201
A
1
b
c
D
E
e
A
b
1
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
10
_
0.035
0.032
0
_
_
_
0.70
---
0.90
0.81
0.028
---
1
Z
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6
MC74LVX541
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
K
K1
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
0.25 (0.010)
IDENT
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006) T U
N
A
−V−
MILLIMETERS
INCHES
MIN
F
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
−W−
C
F
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
G
D
J
H
J1
K
DETAIL E
0.100 (0.004)
−T− SEATING
K1
L
6.40 BSC
0.252 BSC
0
SOLDERING FOOTPRINT
PLANE
M
0
8
8
_
_
_
_
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
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MC74LVX541/D
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