MC74LVXT4051DTG [ONSEMI]
Analog Multiplexer Demultiplexer; 模拟多路复用器多路解复用器
| 型号： | MC74LVXT4051DTG |
| 厂家： | 
ONSEMI |
| 描述： | Analog Multiplexer Demultiplexer |
| 文件： | 总15页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVXT4051
Analog Multiplexer/
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVXT4051 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low leakage
currents. This analog multiplexer/demultiplexer controls analog
voltages that may vary across the complete power supply range (from
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MARKING
DIAGRAMS
V
CC
to V ).
EE
The LVXT4051 is similar in pinout to the LVX8051, the HC4051A,
16
and the metal−gate MC14051B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
TTL levels. These inputs are over−voltage tolerant (OVT) for level
translation from 6.0 V down to 3.0 V.
SOIC−16
D SUFFIX
CASE 751B
LVXT4051G
AWLYWW
1
16
LVXT
4051
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
This device has been designed so the ON resistance (R ) is more
ON
linear over input voltage than the R of metal−gate CMOS analog
ON
switches and High−Speed CMOS analog switches.
1
Features
16
• Select Pins Compatible with TTL Levels
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
SOEIAJ−16
M SUFFIX
CASE 966
LVXT4051
ALYWG
• Analog Power Supply Range (V − V ) = *3.0 V to )3.0 V
1
CC
EE
• Digital (Control) Power Supply Range (V − GND) = 2.5 to 6.0 V
CC
LVXT4051 = Specific Device Code
• Improved Linearity and Lower ON Resistance Than Metal−Gate,
A
WL, L
Y
= Assembly Location
= Wafer Lot
= Year
HSL, or VHC Counterparts
• Low Noise
WW, W
G or G
= Work Week
= Pb−Free Package
• Designed to Operate on a Single Supply with V = GND, or Using
EE
Split Supplies up to 3.0 V
(Note: Microdot may be in either location)
• Break−Before−Make Circuitry
• These Devices are Pb−Free and are RoHS Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2011 − Rev. 5
MC74LVXT4051/D
MC74LVXT4051
FUNCTION TABLE
Control Inputs
V
X2
15
X1
14
X0
13
X3
12
A
B
C
9
CC
Select
B
16
11
10
Enable
C
A
ON Channels
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X0
X1
X2
X3
X4
X5
X6
X7
NONE
L
H
H
H
H
X
1
2
3
4
5
6
7
8
L
X4
X6
X
X7
X5 Enable V
GND
EE
H
H
X
Figure 1. Pin Connection and Marking Diagram
(Top View)
X = Don’t Care
13
X0
14
X1
15
X2
3
COMMON
OUTPUT/INPUT
X
12
X3
ANALOG
INPUTS/OUTPUTS
MULTIPLEXER/
DEMULTIPLEXER
1
X4
5
X5
X6
2
4
X7
A
11
10
9
CHANNEL
SELECT INPUTS
PIN 16 = V
CC
B
C
PIN 8 = GND
PIN 7 = V
EE
6
ENABLE
Figure 2. Logic Diagram
Single−Pole, 8−Position Plus Common Off
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LVXT4051DG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74LVXT4051DR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74LVXT4051DTG
MC74LVXT4051DTR2G
MC74LVXT4051MG
TSSOP−16*
TSSOP−16*
96 Units / Rail
2500 Tape & Reel
50 Units / Rail
SOEIAJ−16
(Pb−Free)
MC74LVXT4051MELG
SOEIAJ−16
(Pb−Free)
2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74LVXT4051
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
EE
CC
Negative DC Supply Voltage
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
*7.0 to )0.5
V
*0.5 to )7.0
*0.5 to )7.0
V
(Referenced to V
)
EE
V
Analog Input Voltage
V
EE *0.5 to V )0.5
V
V
IS
CC
V
IN
Digital Input Voltage
(Referenced to GND)
*0.5 to 7.0
$20
I
DC Current, Into or Out of Any Pin
Storage Temperature Range
mA
T
STG
*65 to )150
260
_C
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
_C
L
T
)150
_C
J
ꢀ
SOIC
TSSOP
143
164
°C/W
JA
P
D
Power Dissipation in Still Air,
SOIC
TSSOP
500
450
mW
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
R
Oxygen Index: 30% − 35%
UL 94−V0 @ 0.125 in
V
ESD
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
u2000
u200
u1000
V
I
Latchup Performance
Above V and Below GND at 125°C (Note 4)
$300
mA
LATCHUP
CC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
V
EE
CC
Negative DC Supply Voltage
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
*6.0
GND
V
2.5
2.5
6.0
6.0
V
(Referenced to V
)
EE
V
Analog Input Voltage
Digital Input Voltage
V
V
CC
V
V
IS
EE
V
IN
(Note 5) (Referenced to GND)
0
6.0
T
Operating Temperature Range, All Package Types
*55
125
_C
ns/V
A
t , t
r
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
CC
V
CC
= 3.0 V $ 0.3 V
= 5.0 V $ 0.5 V
0
0
100
20
f
5. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
DEVICE JUNCTION TEMPERATURE VERSUS
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
1
100
110
120
130
140
20.4
9.4
1
10
100
1000
37,000
4.2
TIME, YEARS
17,800
2.0
Figure 3. Failure Rate vs. Time Junction Temperature
8,900
1.0
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3
MC74LVXT4051
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Guaranteed Limit
V
CC
*55 to 25°C v85°C v125°C
V
Symbol
Parameter
Condition
Unit
V
IH
Minimum High−Level Input
Voltage,
Channel−Select or Enable Inputs
3.0
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low−Level Input
Voltage,
Channel−Select or Enable Inputs
3.0
4.5
5.5
0.5
0.8
0.8
0.5
0.8
0.8
0.5
0.8
0.8
V
I
Maximum Input Leakage Current,
V
= 6.0 or GND
0 V to 6.0 V
$0.1
$1.0
$1.0
ꢁ A
ꢁ A
IN
IN
Channel−Select or Enable Inputs
I
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
= V or GND
6.0
4.0
40
80
CC
V
IS
CC
DC ELECTRICAL CHARACTERISTICS − Analog Section
Guaranteed Limit
V
CC
V
EE
*55 to 25°C v85_C v125_C
V
V
Symbol
Parameter
Test Conditions
= V or V
Unit
R
Maximum “ON” Resistance
V
V
S
3.0
4.5
3.0
0
0
86
37
26
108
46
120
55
ꢂ
ON
IN
IS
IL
IH
= ½ (V − V
)
CC
EE
|I | = 2.0 mA (Figure 4)
*3.0
33
37
ꢃ
R
Maximum Difference in “ON” Res-
istance Between Any Two
Channels in the Same Package
V
V
S
= V or V
IH
3.0
4.5
3.0
0
0
15
13
10
20
18
15
20
18
15
ꢂ
ON
IN
IS
IL
= ½ (V − V
)
CC
EE
|I | = 2.0 mA
*3.0
I
off
Maximum Off−Channel Leakage
Current, Any One Channel
V
V
= V or V ;
IH
5.5
+3.0
0
−3.0
0.1
0.1
0.5
0.5
1.0
1.0
ꢁ
A
in
IL
= V or GND;
IO
CC
Switch Off (Figure 3)
Maximum Off−Channel
Leakage Current,
V
V
= V or V ;
IH
5.5
+3.0
0
−3.0
0.2
0.2
2.0
2.0
4.0
4.0
in
IL
= V or GND;
IO
CC
Common Channel
Switch Off (Figure 4)
I
on
Maximum On−Channel
Leakage Current,
V
= V or V
;
IH
5.5
+3.0
0
−3.0
0.2
0.2
2.0
2.0
4.0
4.0
ꢁ
A
in
IL
Switch−to−Switch =
Channel−to−Channel
V
CC
or GND; (Figure 5)
AC CHARACTERISTICS (Input t = t = 3 ns)
r
f
Guaranteed Limit
*55 to 25_C
V
V
V
EE
V
CC
Min
Typ*
Symbol
Parameter
Test Conditions
v85_C v125_C Unit
t
Minimum Break−Before−Make
V
V
= V or V
3.0
4.5
3.0
0.0
0.0
1.0
1.0
6.5
5.0
3.5
−
−
−
−
−
−
ns
BBM
IN
IS
L
IL
IH
Time
= V
CC
R = 300 ꢂ ꢄ C = 35 pF
L
*3.0 1.0
(Figures 12 and 13)
*Typical Characteristics are at 25_C.
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4
MC74LVXT4051
AC CHARACTERISTICS (C = 50 pF, Input t = t = 3 ns)
L
r
f
Guaranteed Limit
*55 to 25°C
v85°C
v125°C
V
V
V
EE
V
CC
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Unit
t
t
t
,
Maximum Propagation Delay, Channel−Select
2.5
3.0
4.5
3.0
0
0
0
40
28
23
23
45
30
25
25
50
35
30
28
ns
PLH
t
to Analog Output (Figures 16 and 17)
PHL
*3.0
,
Maximum Propagation Delay, Enable to Analog
Output (Figures 14 and 15)
2.5
3.0
4.5
3.0
0
0
0
40
28
23
23
45
30
25
25
50
35
30
28
ns
ns
PLZ
t
PHZ
*3.0
,
Maximum Propagation Delay, Enable to Analog
Output (Figures 14 and 15)
2.5
3.0
4.5
3.0
0
0
0
40
28
23
23
45
30
25
25
50
35
30
28
PZL
t
PZH
*3.0
Typical @ 25°C, V = 5.0 V, V = 0V
CC
EE
45
pF
pF
C
Power Dissipation Capacitance (Figure 18) (Note 6)
PD
C
Maximum Input Capacitance, Channel−Select or Enable Inputs
10
IN
10
10
1.0
C
Maximum Capacitance
(All Switches Off)
Analog I/O
Common O/I
Feedthrough
I/O
pF
2
6. Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Typ
V
CC
V
EE
V
V
25°C
Symbol
Parameter
Condition
Unit
BW
Maximum On−Channel Bandwidth or
Minimum Frequency Response
V
= ½ (V − V
EE
)
80
80
80
80
MHz
3.0
4.5
6.0
3.0
0.0
0.0
0.0
IS
CC
Ref and Test Attn = 10 dB
Source Amplitude = 0 dB
(Figure 7)
*3.0
V
Off−Channel Feedthrough Isolation
f = 1 MHz; V = ½ (V − V
EE
)
*70
*70
*70
*70
dB
dB
3.0
4.5
6.0
3.0
0.0
0.0
0.0
ISO
IS
CC
Adjust Network Analyzer output to 10 dBm
on each output from the power splitter.
(Figures 8 and 9)
*3.0
V
ONL
Maximum Feedthrough On Loss
V
IS
= ½ (V − V )
EE
*2
*2
*2
*2
3.0
4.5
6.0
3.0
0.0
0.0
0.0
CC
Adjust Network Analyzer output to 10 dBm on
each output from the power splitter.
(Figure 11)
*3.0
Q
Charge Injection
V
R
= V to V
f
= 1 kHz, t = t = 3 ns
5.0
3.0
0.0
*3.0
9.0
12
pC
%
IN
CC
EE, IS
r
f
= 0 ꢂ, C = 1000 pF, Q = C * ꢃ V
IS
L
L
OUT
(Figure 10)
f = 1 MHz, R = 10 Kꢂ, C = 50 pF,
IS
THD
Total Harmonic Distortion THD + Noise
L
L
V
V
= 5.0 V sine wave
6.0
3.0
0.0
*3.0
0.10
0.05
IS
PP
= 6.0 V sine wave
IS
PP
(Figure 19)
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5
MC74LVXT4051
PLOTTER
PROGRAMMABLE
POWER
MINI
COMPUTER
DC ANALYZER
SUPPLY
*
)
V
CC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
GND
Figure 4. On Resistance, Test Set−Up
V
CC
V
CC
V
CC
16
A
V
CC
ON
16
V
EE
N/C
COMMON O/I
V
EE
OFF
OFF
OFF
A
A
V
V
CC
V
CC
ANALOG I/O
NC
COMMON O/I
V
IL
6
7
8
V
EE
6
7
8
IH
V
EE
Figure 5. Maximum Off Channel Leakage Current,
Figure 6. Maximum On Channel Leakage Current,
Any One Channel, Test Set−Up
Channel to Channel, Test Set−Up
HP4195A
Network Anl
S1 R1 T1
0.1 ꢁ F
V
IS
HP11667B
Pwr Splitter
V
CC
100 Kꢂ
0.1 ꢁ F
ON
All untested Analog I/O pins
OFF
50 Kꢂ
Channel Selects
V
EE
6
7
8
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
9 − 11
Figure 7. Maximum On Channel Bandwidth, Test Set−Up
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6
MC74LVXT4051
HP4195A
Network Anl
S1 R1 T1
0.1 ꢁ F
HP11667B
Pwr Splitter
0.1 ꢁ F
V
IS
V
CC
100 Kꢂ
16
OFF
ON
All untested Analog I/O pins
50 Kꢂ
Channel Selects
V
EE
6
7
8
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
9 − 11
Config = Network
Format = T/R (dB)
CAL = Trans Cal
V
ISO
(dB) = 20 log (V /V
)
T1 R1
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
Trig = Cont Mode
Source Amplitude = )13 dB
Reference Attenuation = 20 dB
Test Attenuation = 0 dB
Figure 8. Maximum Off Channel Feedthrough Isolation, Test Set−Up
HP4195A
Network Anl
S1 R1 T1
0.1 ꢁ F
V
IS
HP11667B
Pwr Splitter
V
CC
100 Kꢂ
0.1 ꢁ F
16
OFF
ON
50 Kꢂ
All untested Analog I/O pins
Channel Selects
V
EE
50 ꢂ
6
7
8
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
9 − 11
Config = Network
Format = T/R (dB)
CAL = Trans Cal
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
V
(dB) = 20 log (V /V
)
ISOC
T1 R1
Trig = Cont Mode
Source Amplitude = )13 dB
Reference Attenuation = 20 dB
Test Attenuation = 0 dB
Figure 9. Maximum Common−Channel Feedthrough Isolation, Test Set−Up
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MC74LVXT4051
V
CC
16
ON/OFF
OFF/ON
V
OUT
C *
L
Enable
6
V
EE
Bias Channel Selects to
test each combination of
analog inputs to common
analog output.
7
8
R
9 − 11
V
IN
IS
*Includes all probe and jig capacitance.
V
V
IH
V
IS
IL
Q = C * ꢃ V
L
OUT
ꢃ V
OUT
V
OUT
Figure 10. Charge Injection, Test Set−Up
HP4195A
Network Anl
S1 R1 T1
0.1 ꢁ F
HP11667B
Pwr Splitter
0.1 ꢁ F
V
IS
V
CC
100 Kꢂ
16
ON
All untested Analog I/O pins
OFF
50 ꢂ
Channel Selects
V
EE
6
7
8
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
9 − 11
Config = Network
Format = T/R (dB)
CAL = Trans Cal
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
V
ONL
(dB) = 20 log (V /V
)
T1 R1
Trig = Cont Mode
Source Amplitude = )13 dB
Reference Attenuation = 20 dB
Test Attenuation = 20 dB
Figure 11. Maximum On Channel Feedthrough On Loss, Test Set−Up
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MC74LVXT4051
Tek 11801B
DSO
V
CC
COM INPUT
V
CC
V
IN
V
OH
16
80%
OFF
ON
80% of
C
V
OH
L
R
L
Channel Selects connected
V
EE
to V and appropriately
configured to test each switch.
IN
6
7
8
9 − 11
GND
t
BBM
V
IN
50 ꢂ
Figure 12. Break−Before−Make, Test Set−Up
Figure 13. Break−Before−Make Time
V
CC
V
CC
16
COMMON
O/I
V
CC
ON/OFF
OFF/ON
TEST
POINT
ANALOG I/O
CHANNEL
SELECT
50%
GND
C *
L
6
7
8
t
t
PHL
PLH
ANALOG
OUT
50%
CHANNEL SELECT
*Includes all probe and jig capacitance.
Figure 14. Propagation Delays, Channel Select
to Analog Out
Figure 15. Propagation Delay, Test Set−Up
Channel Select to Analog Out
GND
t
f
t
r
POSITION 1 WHEN TESTING t
POSITION 2 WHEN TESTING t
AND t
AND t
PHZ
PLZ
PZH
PZL
V
CC
1
2
90%
50%
10%
ENABLE
V
CC
GND
1 Kꢂ
V
CC
t
t
t
16
PZL
PLZ
HIGH
IMPEDANCE
1
2
ANALOG I/O
TEST
POINT
ON/OFF
ANALOG
OUT
50%
50%
10%
V
OL
C *
L
t
PHZ
PZH
ENABLE
6
V
OH
90%
ANALOG
OUT
7
8
HIGH
IMPEDANCE
Figure 16. Propagation Delays, Enable to
Analog Out
Figure 17. Propagation Delay, Test Set−Up
Enable to Analog Out
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MC74LVXT4051
V
CC
A
V
CC
ON/OFF
OFF/ON
NC
V
IL
15
10 − 11,
13 − 14
12
Channel
Select
Figure 18. Power Dissipation Capacitance, Test Set−Up
HP3466
)V
DMM
COM
HP3466
DMM
)V
COM
HP E3630A
DC Pwr Supply
HP 339
Distortion Measurement Set
COM )20 V
*20 V
Analyzer
Oscillator
Input COM Output COM
16
ON
R
C
L
L
OFF
50 Kꢂ
Channel Selects connected
to DC bias supply or ground
and appropriately configured
to test each switch.
6
7
8
9 − 11
Figure 19. Total Harmonic Distortion, Test Set−Up
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MC74LVXT4051
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
or GND logic levels. V being recognized as a logic
outputs to V or GND through a low value resistor helps
CC
minimize crosstalk and feedthrough noise that may be
V
CC
CC
high and GND being recognized as a logic low. In this
example:
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
V
CC
= )5 V = logic high
GND = 0 V = logic low
V
V
V
− GND = 0 to *6 volts
− GND = 2.5 to 6 volts
EE
The maximum analog voltage swing is determined by the
CC
supply voltages V and V . The positive peak analog
CC
EE
− V = 2.5 to 6 volts
CC
EE
voltage should not exceed V . Similarly, the negative peak
CC
and V v GND
EE
analog voltage should not go below V . In this example,
EE
the difference between V and V is five volts. Therefore,
When voltage transients above V and/or below V are
CC EE
CC
EE
using the configuration of Figure 21, a maximum analog
signal of five volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
anticipated on the analog channels, external Germanium or
Schottky diodes (D ) are recommended as shown in
x
Figure 22. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
)3.0 V
)5 V
)5 V
)3.0 V
*3.0 V
16
16
)3.0 V
*3.0 V
)5 V
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ON
ON
GND
GND
TO EXTERNAL CMOS
CIRCUITRY 0 to 3.0 V
DIGITAL SIGNALS
TO EXTERNAL CMOS
CIRCUITRY 0 to 5 V
DIGITAL SIGNALS
6
7
8
11
10
9
6
7
8
11
10
9
*3.0 V
Figure 20. Application Example
Figure 21. Application Example
V
CC
V
CC
V
CC
D
D
x
16
ON/OFF
x
D
D
x
x
V
EE
V
EE
7
8
V
EE
Figure 22. External Germanium or Schottky Clipping Diodes
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11
MC74LVXT4051
11
10
9
13
14
15
12
1
LEVEL
SHIFTER
A
X0
X1
X2
X3
X4
X5
X6
X7
X
LEVEL
SHIFTER
B
C
LEVEL
SHIFTER
5
6
2
LEVEL
SHIFTER
ENABLE
4
3
Figure 23. Function Diagram, LVXT4051
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12
MC74LVXT4051
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T B
SOLDERING FOOTPRINT
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
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13
MC74LVXT4051
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
N
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
F
1.20
−−− 0.047
DETAIL E
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
−W−
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
C
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
6.40 BSC
0.252 BSC
D
G
M
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
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14
MC74LVXT4051
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
16
9
E
Q
1
H
E
M
_
E
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
2.05
0.20
0.50
0.20
10.50
5.45
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
---
0.05
0.35
0.10
9.90
5.10
---
0.002
0.014
0.007
0.390
0.201
A
1
A
1
b
c
b
0.13 (0.005)
D
E
0.10 (0.004)
M
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
0
10
10
_
0.035
0.031
M
Q
0
_
_
_
0.70
---
0.90
0.78
0.028
---
1
Z
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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